Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Response to Arguments
Applicant’s arguments with respect to claims 1-13 have been considered but are moot in view of the new ground(s) of rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites, “a switching frequency”, however no switching element has been introduced within the integrated circuit embodiment of claim 1 for a switching frequency to pertain to. Similarly, the limitation “a switching element size” refers to a size of a switching element that has not been properly introduced within the claim.
Claims 2-13 inherit the indefinite rejection of claim 1 due to their dependencies.
For examination purposes, the claimed “internal parameters” will be interpreted as any parameter/setting that can be configured/set when providing power to a device connected to a power supply device.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over More et al. U.S. PGPUB No. 2011/0022859 in view of Nonaka, U.S. PGPUB No. 2009/0102444.
Per Claim 1, More discloses:
a semiconductor integrated circuit device (Paragraph 147; power management integrated circuit (PMIC) 102) forming at least a portion of a power supply device (Paragraph 147, Figure 1; PMIC 102 in combination with battery 104, and AC connection 105 form a power supply device for device 101.),
the power supply device configured to convert an input voltage into an output voltage (Paragraph 147, “converts the AC supply to suitable DC supply”; Paragraph 150, “DC-DC Buck (step-down) converters, DC-DC Boost (step-up) converters”),
the semiconductor integrated circuit device comprising:
a memory configured to store a plurality of settings regarding a plurality of types of internal parameters (Paragraph 153, registers 114; Paragraphs 158, and 159, NVM 115; Paragraph 173, Registers 114 and NVM 115 can be used interchangeably depending on their state which is affected by the power cycles of the device (i.e. volatile memory vs. non-volatile memory).);
a receiver configured to receive an instruction transmitted from outside the semiconductor integrated circuit device (Paragraph 147 discusses device-to-device interface 106, such as a USB interface. Paragraphs 152 and 153; “The control signal lines may also be used to communicate control information back to the power domains. As illustrated some control signal information may also be received via the device-to-device interface 106”.;
and a controller configured to select one of the plurality of settings on the basis of the instruction and to enable the selected setting (Paragraphs 152 and 153; “The control circuitry 111 determines which power blocks are active in the PMIC and also the output of the active power blocks. Some power domains, when active, may require a fixed voltage supply but for others the voltage requirements may vary with usage of the device. The control circuitry may therefore be arranged to receive, via command and control signal lines 112, information regarding the power requirements of the power domains 103a-d from one or more of the various device sub-systems 117a-d and to control the outputs of power blocks 109a-d accordingly.”).
More does not elaborate on the content of the settings stored in the PMIC registers 114 that are updated by the processor (Paragraph 153) and therefore does not specifically teach the switching frequency/element size limitations.
However, Nonaka teaches a DC-DC converter where switching conditions such as phase compensation and frequency settings are set to provide a stable output voltage (Paragraphs 34-41).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the registers of More to comprise switching frequency and phase information, such as the information taught by Nonaka, because phase compensation and switching circuits are commonly used in power converters to provide a stable output voltage (Paragraphs 34 and 41).
Per Claim 2, More discloses the semiconductor integrated circuit device according to claim 1, wherein the memory, which is a multiple-time programmable memory, is configured to store of which the plurality of settings is enabled (Paragraph 158; “MTP (multi-time programmable, e.g. Flash memory)”).
Per Claim 3, More discloses the semiconductor integrated circuit device according to claim 1, further comprising: a read-only memory configured to store the set values regarding the plurality of internal parameters respectively corresponding to the plurality of settings (Paragraph 158; “non-volatile memory (NVM) 115 (e.g. ROM)”).
Per Claim 4, More discloses the semiconductor integrated circuit device according to claim 1, wherein the receiver is configured to receive the instruction through wired communication (Paragraph 147; Device-to-device interface 106 is a USB interface which is a wired interface.).
Per Claim 5, More discloses the semiconductor integrated circuit device according to claim 1, wherein the instruction includes information regarding a maximum load current of the power supply device (Paragraph 64; “Additionally or alternatively the control circuitry may be arranged to provide control over the configuration settings of the external power blocks so as to allow control over any or all of the voltage output, any operating limits such as current limits or voltage settings or operating mode of the device.”).
* * * * * * *
Claims 6-13 are rejected under 35 U.S.C. 103 as being unpatentable over More et al. U.S. PGPUB No. 2011/0022859 in view of Nonaka, U.S. PGPUB No. 2009/0102444, in further view of Lee, U.S. PGPUB No. 2023/0107998.
Per Claim 6, More discloses an electrical apparatus (Paragraphs 147 and 217 discuss types of devices represented by numeral 1.) comprising: a power supply device (Paragraph 147, Figure 1; PMIC 102 in combination with battery 104, and AC connection 105 form a power supply device for device 101.); and a processor configured to execute software using an output voltage of the power supply device as a power supply voltage (Paragraphs 58, 149, and 150; CPU core 117a), wherein the power supply device includes the semiconductor integrated circuit device according to claim 1 (See above rejection of claim 1).
More does not specifically teach the processor is configured to make it possible to update the software through communication.
However, Lee teaches a PMIC 530 in communication with a core unit 542 and further teaches wherein the core unit helps facilitate a software update (Paragraph 51, “the server 100 may provide new SW necessary to perform a software update on the MDPS controller 500 by transmitting the new SW to the MDPS SW update apparatus 200 by using an over the air (OTA) method in response to a request from the MDPS SW update apparatus 200”; Paragraphs 85 and 86; “Furthermore, when receiving new SW through the communication unit 548, the core unit 542 may download the new SW to the second memory 546 in which an old version of SW has not been stored, and may check the integrity of the new SW downloaded to the second memory 546.”)
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform the update operations described by More in the manner taught by Lee because over-the-air (OTA) updates offer a method for rapidly updating the software of an electronic device (Lee; Paragraph 150).
Per Claim 7, the electrical apparatus according to claim 6, wherein the update of the software is executed through wireless communication (Paragraph 51; “transmitting the new SW to the MDPS SW update apparatus 200 by using an over the air (OTA) method”). The motivation to combine the references remains the same as outlined in the rejection of claim 6.
Per Claims 8/9, Lee further teaches the electrical apparatus according to claim 6/7, wherein the processor is configured to transmit the instruction to the semiconductor integrated circuit in response to the update of the software (Paragraph 88; “when the update of the new SW is completed, the core unit 542 may control the MCU 540 to operate in the normal sleep mode by deactivating the communication transceiver 510 and transmitting a latch signal control-off command to the power management unit 530”). The motivation to combine the references remains the same as outlined in the rejection of claim 6.
Per Claims 10-13, please see the above rejection of claims 6-9 for details on More’s teaching of the claimed electrical apparatus of claims 6-9.
More does not specifically teach that the electrical apparatus is comprised within a vehicle.
However, Lee teaches performing the software update teachings of claim 6 on system circuitry that is resident of a vehicle (Paragraph 55, Fig. 1).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement the electrical apparatus of More as a vehicular embodiment because the devices (GPS, navigation devices, etc.) of More (Paragraph 133) are also commonly used within the vehicle of Lee and would benefit from the ease and speed of OTA updates as taught by Lee (Lee; Paragraph 150).
Prior Art
The prior art made of record but not relied upon in the Examiner’s rejections is cited as being pertinent to the applicant’s disclosure due to various teachings including switched power supplies, commonly assigned applications to Rohm featuring phase compensation, switching elements and/or frequencies.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889. The examiner can normally be reached on M-F: 8-4:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175
Prosecution Insights