Prosecution Insights
Last updated: July 31, 2026
Application No. 18/764,685

METHOD FOR OBTAINING DIFFERENT ADDRESSES BY CHANGING INTERNAL LOGIC VALUES OF CHIP THROUGH LIGHT

Final Rejection §102
Filed
Jul 05, 2024
Priority
May 28, 2024 — CN 202410673624.3
Examiner
LUQUE, RENAN
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Shenzhen Hsg Electronics Co. Ltd.
OA Round
2 (Final)
78%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
422 granted / 541 resolved
+10.0% vs TC avg
Strong +17% interview lift
Without
With
+16.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
18 currently pending
Career history
551
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
76.6%
+36.6% vs TC avg
§102
13.3%
-26.7% vs TC avg
§112
3.6%
-36.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 541 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Objections Claim(s) 2 is/are objected to because of the following informalities: With regards to claim(s) 2: in line 5, “wherein the software input module is used for inputting a program for changing”, was recited perhaps - -wherein the software input module is configured for inputting a program for changing- - was meant. With regards to claim(s) 2: in line 11, “wherein the MUC chip is used for extracting the program for changing the internal”, was recited perhaps - - wherein the MUC chip is configured for extracting the program for changing the internal- - was meant. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 and 3-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (CN 116801446 A; see translation). With regards to claim 1. Yang disclose(s): A method (figs 1-8) for obtaining different addresses by changing internal logic values of a chip through light (fig 6; [lines 19-25 in page 8]), wherein a light containing address information is irradiated on a LED lamp bead (see figs 3-4; [lines 26-28 in page 5]), and then is transmitted to an IC chip inside the LED lamp bead (see figs 7-8; [lines 5-12 in page 10]), and after receiving electric current containing the address information, the IC chip automatically decodes to generate a logical address consistent with the address information carried by the light (lines 24-32 in page 10). With regards to claim 3. Yang disclose(s): An LED lamp bead, comprising an IC chip, wherein a logical address in the IC chip is obtained by using the method for obtaining different addresses by changing internal logic values of a chip through light according to claim 1 (see fig 8 for changing logic values of LED chip; see addresses in fig 6; [lines5-12 in page 10] [lines 19-25 in page 8]). With regards to claim 4. Yang disclose(s): The LED lamp bead according to claim 3, wherein the LED lamp bead has three-primary-color light-emitting units (see figs 3-4), and the three-primary-color light-emitting units are an R light-emitting unit (OUTR; RLED), a G light-emitting unit (OUTG; GLED)and a B light-emitting unit (OUTB; BLED), respectively . With regards to claim 5. Yang disclose(s): The LED lamp bead according to claim 4, wherein the three-primary-color light-emitting units (see figs 3-4) are all electrically connected to a VDD pin (VDD in fig 3), and are then electrically connected to a positive electrode of a power supply through the VDD pin (lines 20-21 in page 6). With regards to claim 6. Yang disclose(s): The LED lamp bead according to claim 5, wherein the IC chip is electrically connected to a controller for controlling the LED lamp bead through a DIN pin (see control data; [lines 33-34 in page 10] [lines 2531 in page 11]), and the IC chip is further electrically connected to a positive and negative electrodes of the power supply through the VDD and a VSS pin (see VDD and GND in fig 3), respectively. Allowable Subject Matter Claim(s) 2 is/are allowed. The following is an examiner’s statement of reasons for allowance: With regards to claim(s) 2: the prior art fails to disclose a/an programming device requiring: wherein the MUC chip is used for extracting the program for changing the internal logical values of the chip inputted by the software input module, and transmitting the program to the optical signal encoding modulator; and the optical signal encoding modulator controls the light source to emit optical signals with a certain frequency according to the program for changing the internal logical values of the chip inputted by the software input module, in combination with other limitations of the claim. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments Applicant's arguments filed 5/29/2026 have been fully considered but they are not persuasive. Applicant asserts that the prior art, Yang, fails to disclose “after receiving electric current containing the address information, the IC chip automatically decodes to generate a logical address consistent with the address information carried by the light” as recited in claim 1. To support this position, Applicant relies on paragraphs [0032, 0033, 0044] of Yang which discloses detail of the operation of burning fuses (by receiving optical information by photosensitive diodes) to store information. The examiner respectfully disagrees; Yang discloses optical detection of address code burning circuit [lines 26-28 in page 5]. Such circuit involves receiving logic values though light ([lines 26-34 in page 8], [lines 1-27 in page 9]). Yang clearly discloses that the received information can be any of multiple different address code [lines 26-27 in line 9]. Further, Yang discloses that the address code is being decoded [lines 28-30 in page 9]. For that reason, Yang discloses the required limitation by claim 1 “after receiving electric current containing the address information, the IC chip automatically decodes to generate a logical address consistent with the address information carried by the light” [lines 24-32 in page 10]. Although claim 1 recites “a method for obtaining different addresses”, such limitation does not require the different addresses being stored after one initial address has been stored as alleged in page 7 of the remarks. For at least reasons above, the examiner maintains the rejection of records. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Renan Luque whose telephone number is (571)270-1044. The examiner can normally be reached M-F 9:30AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at (571) 272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RENAN LUQUE/Primary Examiner, Art Unit 2845
Read full office action

Prosecution Timeline

Jul 05, 2024
Application Filed
Mar 16, 2026
Non-Final Rejection mailed — §102
May 29, 2026
Response Filed
Jun 29, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+16.7%)
2y 0m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 541 resolved cases by this examiner. Grant probability derived from career allowance rate.

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