DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 11075604, claims 1-21 of U.S. Patent No. 11601092, and claims 1-17 of U.S. Patent No. 12034406. Although the claims at issue are not identical, they are not patentably distinct from each other because the patents’ claims and application’s claims recite similar limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Depaoli et al. (US 20140361815) in view of Jindrich (CS 2735522), Applicant admitted prior art (AAPA) figure 1, and Caffee (US 20170179881).
As to claim 1, Depaoli et al.’s figure 4 shows radio frequency mixer driver circuit including an input configured (capable of) to receive a base oscillator signal (V+/V-); a first frequency multiplier module (P1 and P2) and second frequency multiplier module (N1 and N2). The figure fails to show that the first and second frequency multiplier modules are complementary frequency multiplier modules. However, Jinndrich’s figure shows a frequency multiplier comprises complementary frequency multiplier module (7 and 8). Therefore, it would have been obvious to one having ordinary skill in the art to Use complementary frequency multiplier module for each of Depaoli et al.’s frequency multiplier modules for the purpose of saving cost. It is noted that MOSFET is well known in the art. It would have been obvious to one having ordinary skill in the art to use MOSFETs for the complementary frequency multiplier modules for the purpose of saving space. Thus, the modified Depaoli et al.’s figure further shows that the first complementary frequency multiplier module coupled to the input and configured to generate a first output signal (OUT+) at a higher frequency than the applied lower frequency base oscillator signal, the first complementary frequency multiplier module including an N- type transistor including a gate controlled by the base oscillator signal, a drain configured to be coupled to a first voltage potential, and a source; a P-type transistor including a gate controlled by the base oscillator signal, a source configured to be coupled to the first voltage potential , and a drain. Depaoli et al.’s figure fails to show first and second amplifiers connected as claimed. However, AAPA’s figure 1 shows amplifier M3n coupled between frequency multiplier module (Min and M2n) and filter (L, 124). Therefore, it would have been obvious to one having ordinary skill in the art to further add amplifier between each of Depaoli et al.’s frequency multiplier modules and filter/coupling circuit for the purpose of achieving desired output amplitude. Thus, the modified Depaoli et al.’s figure further shows a first amplifier (the add first amplifier) including a first amplifier input coupled to the source of the N-type transistor and to the drain of the P-type transistor, and a first amplifier output; the second complementary frequency multiplier module coupled to the input and configured to generate a second output signal (OUT-) at a higher frequency than the applied lower frequency base oscillator signal, the second complementary frequency multiplier module including an N-type transistor including a gate controlled by the base oscillator signal, a source configured to be coupled to a second voltage potential, and a drain; a P-type transistor including a gate controlled by the base oscillator signal, a drain configured to be coupled to the second voltage potential, and a source; and a second amplifier (the added second amplifier) including a second amplifier input coupled to the drain of the N-type transistor and to the source of the p-type transistor, and a second amplifier output; and a parallel resonant filter/coupling circuit (16, see figure 5) including a first terminal coupled to the first amplifier output to receive the first output signal and a second terminal coupled to the second amplifier output to receive the second output signal; the parallel resonant filter/coupling circuit being configured to provide a high impedance (when the inductor or capacitors are not shorted) to the frequency of the first and second output signals and a low impedance (when the inductor Lor capacitors are shorted) at other frequencies (high frequency that causes the capacitors to be shorted or low frequency that causes the inductor to be shorted), to provide a DC short between the first and second complementary frequency multiplier modules, and to output the first and second output signals as balanced first and second output signals having opposite phasing. The modified circuit fails to show that the parallel resonant filter/coupling circuit is configured to provide a ground return path to circuit ground for current from intermediate frequencies applied to the first and second terminals of the parallel resonant filter/coupling circuit. However, Caffee’s figure 7 shows a similar LC oscillator (see Depaoli et al.’s figures 7 and 8). It would have been obvious to one having ordinary skill in the art to use Caffee’s LC oscillator for Depaoli et al.’s oscillator for the purpose of providing more precise oscillating signals. Thus, the modified Depaoli et al.’s figure shows that the parallel resonant filter/coupling circuit provides a ground return path (via Caffee’s CBypass) to circuit ground for current from intermediate frequencies applied to the first and second terminals of the parallel resonant filter/coupling circuit.
As to claim 2, the modified Depaoli et al.’s figure 4 shows the parallel resonant filter/coupling circuit includes: (a) a first inductor (Caffee’s left LT/2. It would have been obvious to one having ordinary skill in the art to select inductor for LT for the purpose of providing more precise inductance, see Depaoli’s figures 7 and 8) and a second inductor (right LT/2) series coupled between the first terminal and the second terminal of the parallel resonant filter/coupling circuit; (b) a capacitor (Caffee’s 3/4CT) coupled between the first terminal and the second terminal of the parallel resonant filter/coupling circuit and in parallel with the first and a second inductors; and (c) a shunt capacitor (CBYpass. It would have been obvious to one having ordinary skill in the art to select capacitor for CBpass for the purpose of providing more precise capacitance) coupled between circuit ground and a node between the first and a second inductors.
As to claim 3, the modified Depaoli et al.’s figure shows that the DC short provides a common bias current for the N-type and P-type transistors in the first and second complementary frequency multipliers.
As to claim 4, the modified Depaoli et al.’ figure shows that the first output signal and the second output signal are at twice the frequency of the base oscillator signal.
As to claim 5, the modified Depaoli et al.’s figure shows that the N-type transistor and P-type transistor each comprise one or more series-coupled FET devices.
6. The radio frequency mixer driver circuit of claim 1, wherein the first and second amplifiers are common-gate FET amplifiers.
As to claims 7-11, AAPA figure 1 further shows that the circuit includes at least one receiver path Rx or transmitter path Tx, the signal path including at least one frequency mixer circuit configured to shift signals from a first frequency range to a second frequency range, wherein the at least one frequency mixer circuit includes first and second complementary frequency multiplier modules and parallel resonant filter/coupling circuit as claimed (see the rejection of claim 2); and a mixer core 100 coupled to frequency double circuit 120 via filter (L, 124) to provide higher frequency signal. It would have been obvious to one having ordinary skill in the art to further add a mixer circuit coupled to the outputs of Depaoli et al.’s figure for the purpose of providing higher output frequency (note that the balun 102 shown in AAPA’s figure 1 is for converting single end signal to differential signal. Since Depaoli et al.’s figure 4 generates differential signals, the balun is seen not required in the mixer circuit).
As to claim 12, the modified Depaoli et al.’s figure 4 shows that the mixer core includes: (a) a balun (AAPA’s 106) having a first port and a second port on a balanced side, and a third port and a fourth port on an unbalanced side; and (b) a mixer ring (104) having a first node coupled to the first terminal of the parallel resonant filter/coupling circuit, a second node coupled to the second terminal of the parallel resonant filter/coupling circuit, a third node coupled to the first port of the balun, and a fourth node coupled to the second port of the balun.
As to claim 13, the modified Depaoli et al.’s figure 4 shows that the mixer ring is a diode-ring.
As to claim 14, FET connected diode is well known in the art. It would have been obvious to one having ordinary skill in the art to use FETs for the diode in the mixer ring for the purpose of reducing space. Therefore, the modified figure shows that the mixer ring is a quad-FET ring.
As to claim 15, filter coupled between electronic devices is well known in the art. It would have been obvious to one having ordinary skill in the art to add filter respectively coupled to the mixer ring outputs for the purpose of reducing noise. Therefore, the modified circuit shows a first filter between the third node of the mixer ring and the first port of the balun, and a second filter between the fourth node of the mixer ring and the second port of the balun.
As to claim 16, the modified Depaoli et al.’s figure shows that the integrated circuit transmitter and/or receiver is part of a radio frequency wireless device.
As to claim 17, the modified Depaoli et al.’s figure shows that the N-type transistor and P-type transistor each comprise one or more series-coupled FET devices.
As to claim 18, the modified Depaoli et al.’s figure shows that the first and second amplifiers are each common-gate FET amplifiers.
As to claim 19, a FET comprises a stack of series-coupled FET a stack of series-coupled FET is well known in the art. It would have been obvious to one having ordinary skill in the art to use a stack of series-coupled FET for the amplifier The integrated circuit transmitter and/or receiver of claim 18, wherein the common-gate FET for the first and second amplifiers for the purpose of achieving desired impedance/gain.
Claims 20 recites similar limitations in claims above. Therefore, it is rejected for the same reasons.
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/QUAN TRA/
Primary Examiner
Art Unit 2842