DETAILED ACTION
This action is responsive to 12/13/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 18/193003, filed on 03/30/2023.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-10, and 13-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Patent 11,664,355) in view of Kim et al. (US Pub. 2017/0005077), hereinafter Kim, and Lim et al. (US Pub. 2020/0091376), hereinafter Lim.
Regarding claim 1, Lee discloses an electronic device (a display apparatus-see fig. 1), comprising: a first substrate (support substrate 160-see figs. 1-2); a first electronic unit arranged on the first substrate (drive devices (thin film transistors) for driving light emitting devices may be formed together with wires on a lower surface of a module substrate 120 (i.e., on the module substrate-see fig. 6 and [col. 7, ll. 47-64]); a package unit (light emitting device 130 (130a, 130b, and 130c)-see fig. 2A with description in, for example, [col. 6, ll. 26-52]) including a second substrate overlapped with the first substrate (module substrate 120 for each display module 110-see figs. 1-2 with description in [col. 6, ll. 8-38]) and a second electronic unit arranged on the second substrate (light emitting device 130-see figs. 2-5); a first pad and a second pad overlapped with the second substrate (interconnect portions 125, directly connected to contact pads 137a, 137b of each light emitting device-see figs. 2b and 3 with description in [col. 9, ll. 20-30]), wherein the first pad is separated from the second pad by a space (see figs. 2-3), and at least one of the first pad and the second pad is electrically connected to the first electronic unit and the second electronic unit (see [col. 7, ll. 57-64] and [col. 9, ll. 39-52]-drive devices for driving light emitting devices 130 may be thin film transistors, each of which may be connected to the corresponding light emitting device 130).
Lee does not appear to expressly disclose a first pad and a second pad arranged between the first substrate and the second substrate and a protective layer overlapped with the first layer and in contact with a part of sidewalls of the package unit.
Kim is relied upon to teach a first pad and a second pad arranged between the first substrate and the second substrate (see, for example, fig. 9, which illustrates electrical components 24 (see [0056]) comprising electrical devices 30 (second electronic unit) on a substate 32 (second substrate), contact pads 56(56’/50’/54) disposed between the substrate 32 and substrate 44 (first substrate) and a protective layer overlapped with the first layer and in contact with a part of sidewalls of the package unit (see figs. 13 and 15-16 with description in [0079]-[0083]-encapsulating layers 64, 68, or 72 … openings may be formed in the layers (64, 68 or 72) that are aligned with some or all of light emitting components 24 (see [0083])).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to form the first and the second pads between the first and the second substrates, and to provide a protective layer for protecting underlying components, as taught by Kim, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., electrically coupling component 24 to pads on the substrate 44, and providing encapsulation to protect underlying components).
Lee in view of Kim does not appear to expressly teach a first layer arranged between the first substrate and the second substrate; wherein a portion of the first layer is in the space.
Lim is relied upon to teach a first layer arranged between the first substrate and the second substrate (see, for example, figs. 2-4 and 6-9 with description in [0072]-[0074], which teaches a protective layer 223 formed on a substrate 220 … the protective layer may be a light absorption layer (see [0074])); wherein a portion of the first layer is in the space (see figs. 2 and 6-9, wherein, the protective layer may also be formed between contact electrodes (pads) 17/227 and 19/229).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Lim with the inventions of Lee and Kim by forming a protective layer, such as a light absorption layer, on a substrate in which light-emitting diodes are coupled, as taught by Lim, for protecting the plurality of electrodes 227 and 229 (see [0072]).
Regarding claim 2, Lee discloses further comprising a conductor electrically connected to the first electronic unit, wherein the first substrate has a through hole, and a first portion of the conductor is in the through hole (see figs. 2B and 6-7 with description in [col. 9, ll. 53-col. 10, ll. 67]-through hole 121 is formed with a via 123 that includes lower pad 123c, upper pad 123a, and inner electrode 123b (fig. 6), and in fig. 7, conductive electrode portion 163 extends the via through the support substrate 160).
Regarding claim 3, Lee discloses wherein a second portion of the conductor is outside the through hole of the first substrate and electrically connected to the first portion of the conductor, and the second portion is greater than the first portion in width (see figs. 6-7, for example, in fig. 6, upper pad 123a has a larger width than middle electrode 123b).
Regarding claim 5, Lim is further relied upon to teach wherein the first substrate comprises inorganic material (see, for example, [0073], which teaches that substrate 44 may be formed from transparent dielectrics (e.g., glass, transparent ceramic)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Lim with the inventions of Lee and Kim, such that the first substrate is made of an inorganic material, such as glass or ceramics, which constitutes combining prior art elements according to known methods to yield predictable results.
Regarding claim 6, Lim is further relied upon to teach wherein the first substrate comprises glass (i.e., substrate 44 may be formed from transparent dielectrics (e.g., glass)).
Regarding claim 7, Kim is further relied upon to each further comprising a third substrate, wherein the first substrate is arranged between the second substrate and the third substrate (see, for example, fig. 9, which illustrates electrical components 24 (see [0056]) comprising electrical devices 30 (second electronic unit) on a substate 32 (second substrate), contact pads 56(56’/50’/54) disposed between the substrate 32 and substrate 44 (first substrate), and, in for example fig. 14 with description in [0080], substate 44 and components 24 have been mounted on a support structure 66 (herein third substate)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Kim with the inventions of Lee and Lim, by further attaching a third substrate below the first substrate, which, as taught by Kim, functions as a support substrate (see [0080]).
Regarding claim 8, Kim is further relied upon to teach further comprising a second layer arranged between the first substrate and the third substrate (adhesive (second layer) may be used in attaching substrate 44 to layer 66-see [0080]).
Regarding claim 9, Lee discloses further comprising a conductor electrically connected to the first electronic unit, wherein the first substrate has a through hole, and a first portion of the conductor is in the through hole (see figs. 2B and 6-7 with description in [col. 9, ll. 53-col. 10, ll. 67]-through hole 121 is formed with a via 123 that includes lower pad 123c, upper pad 123a, and inner electrode 123b (fig. 6), and in fig. 7, conductive electrode portion 163 extends the via through the support substrate 160).
Regarding claim 10, Lee discloses wherein a second portion of the conductor is outside the through hole of the first substrate and electrically connected to the first portion of the conductor, and the second portion is greater than the first portion in width (see figs. 6-7, for example, in fig. 6, upper pad 123a has a larger width than middle electrode 123b).
Regarding claim 13, Lee discloses wherein the first electronic unit comprises a transistor (i.e., drive devices (thin film transistors) for driving light emitting devices-see [col. 7, ll. 47-64]).
Regarding claim 14, Lim is further relied upon to teach wherein the first layer is configured to absorb a light (i.e., protective layer 223 may be a light-absorbing layer-see [0074]).
Regarding claim 15, Lee discloses wherein the second electronic unit comprises a diode (light emitting device 130-see figs. 2-5).
Regarding claim 16, Kim is further relied upon to teach wherein the first substrate has a first surface, the second substrate has a second surface adjacent to the first surface of the first substrate, and the first pad and the second pad are arranged between the first surface of the first substrate and the second surface of the second substrate (interconnects 56 (solder pads 56’ and solder 54) are disposed between the interposer substrate 32 and substrate 44 (first substrate)-see fig. 9).
Regarding claim 17, Lee discloses an electronic device (a display apparatus-see fig. 1), comprising: a first substrate (support substrate 160-see figs. 1-2); a first electronic unit arranged on the first substrate (drive devices (thin film transistors) for driving light emitting devices may be formed together with wires on a lower surface of a module substrate 120 (i.e., on the module substrate-see fig. 6 and [col. 7, ll. 47-64]); a package unit including a second electronic unit (light emitting device 130 is an LED package including first to third light emitting devices (130a, 130b, and 130c)-see fig. 2A with description in [col. 6, ll. 62-67]) on a second substrate (module substrate 120 for each display module 110-see figs. 2A-2B with description in [col. 6, ll. 88-10]); a first pad and a second pad, wherein the first pad is separated from the second pad by a space (interconnect portions 125 (separated by a space), directly connected to contact pads 137a, 137b of each light emitting device-see figs. 2B and 3 with description in [col. 9, ll. 20-30]), and at least one of the first pad and the second pad is electrically connected to the first electronic unit and the second electronic unit (see fig. 3, [col. 7, ll. 57-64] and [col. 9, ll. 39-52]-drive devices for driving light emitting devices 130 may be thin film transistors, each of which may be connected to the corresponding light emitting device 130).
Lee does not appear to expressly disclose a first pad and a second pad arranged between the first substrate and the second substrate and a protective layer overlapped with the first layer and in contact with a part of sidewalls of the package unit.
Kim is relied upon to teach a first pad and a second pad arranged between the first substrate and the second substrate (see, for example, fig. 9, which illustrates electrical components 24 (see [0056]) comprising electrical devices 30 (second electronic unit) on a substate 32 (second substrate), contact pads 56(56’/50’/54) disposed between the substrate 32 and substrate 44 (first substrate) and a protective layer overlapped with a first layer and in contact with a part of sidewalls of the package unit (see figs. 13 and 15-16 with description in [0079]-[0083]-encapsulating layers 64, 68, or 72 … openings may be formed in the layers (64, 68 or 72) that are aligned with some or all of light emitting components 24 (see [0083])).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to form the first and the second pads between the first and the second substrates, and to provide a protective layer for protecting underlying components, as taught by Kim, which constitutes combining prior art elements according to known methods to yield predictable results (i.e., electrically coupling component 24 to pads on the substrate 44, and providing encapsulation to protect underlying components).
Lee in view of Kim does not appear to expressly teach a first layer arranged between the first substrate and the package unit; wherein a portion of the first layer is in the space.
Lim is relied upon to teach a first layer arranged between the first substrate and the package unit (see, for example, figs. 2-4 and 6-9 with description in [0072]-[0074], which teaches a protective layer 223 formed on a substrate 220 … the protective layer may be a light absorption layer (see [0074])); wherein a portion of the first layer is in the space (see figs. 2 and 6-9, wherein, the protective layer may also be formed between contact electrodes (pads) 17/227 and 19/229).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Lim with the inventions of Lee and Kim by forming a protective layer, such as a light absorption layer, on a substrate in which light-emitting diodes are coupled, as taught by Lim, for protecting the plurality of electrodes 227 and 229 (see [0072]).
Claim 4 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim and Lim, and further in view of Iguchi (US Pub. 2018/0254226).
Regarding claim 4, Lee in view of Kim and Lim does not appear to expressly teach wherein the conductor comprises copper.
Iguchi is relied upon to teach wherein the conductor comprises copper (see, for example, fig. 11, which illustrates a plurality of pixel substrates 200 disposed on a base substrate 110, via holes 215 through a film substrate 201 are electrically connected to wiring layers (111, 112) on a surface 110a of the base substrate 110, through conductors formed by filling the via holes 215 with conductive material (e.g., copper plating), the conductive material forms a connection point (or pad-see, for example, fig. 13) on a principal surface 201a of the film substrate 201. Wiring (111, 112) is made of copper-(see [0104]-[0106])).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Iguchi with the inventions of Lee, Kim, and Lim such that the conductor comprises copper, as taught by Iguchi, as a simple substitution of one known element for another to yield predictable results.
Regarding claim 11, Iguchi is further relied upon to teach wherein a portion of the second layer is not overlapped with the first portion of the conductor (for example, fig. 11, which illustrates a plurality of pixel substrates 200 disposed on a base substrate 110, via holes 215 through a film substrate 201 (herein equated to claimed array substrate) are electrically connected to wiring layers (111, 112) on a surface 110a of the base substrate 110, through conductors formed by filling the via holes 215 with conductive material. As shown in fig. 11(1), the insulating resin 221 between base substrate 110 and film substate 201(herein equated to claimed second layer) does not overlap conductive paste 220 and/or 104 (or via hole 215)).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Iguchi with the inventions of Lee, Kim, and Lim such that a portion of insulating material used for bonding the first and the second substrate does not overlap connecting structures and corresponding vias that supply electrical signals between substrates, as taught by Iguchi, which constitutes combining prior art elements according to known methods to yield predictable results.
Claim 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Kim and Lim, and further in view of Mathies et al. (US Patent 6,476,783), hereinafter Mathies.
Regarding claim 12, Lee in view of Kim and Lim does not appear to expressly teach further comprising a circuit arranged on the third substrate.
Mathies is relied upon to teach further comprising a circuit arranged on the third substrate (see, for example, fig. 19, with description in [col. 17, ll. 49-col. 18, ll. 6], which teaches a OLED display having an electronics section 102 and a display section 104 each composed of multiple layers, the display section includes a glass substrate (second substrate), while the electronics section includes material 1924 (herein equated to claimed first substrate), and an insulating substrate 110 (herein equated to claimed third substrate). Column vias 112 through the substrate 110 connect electronics module (e.g., 134) below the substrate 112 to circuits on the insulating substrate 110).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Iguchi with the inventions of Lee, Kim, and Lim by including circuits arranged on the third substrate, which constitutes combining prior art elements according to known methods to yield predictable results.
Response to Arguments
Applicant's arguments filed 12/13/2025 have been fully considered but they are not persuasive. Applicant argued (see applicant remarks, pg. 7-10) that the applied references (Lee in view of Kim and Lim) fail to teach or suggest the amended features of “a protective layer overlapped with the first layer and in contact with a part of sidewalls of the package unit”.
The examiner respectfully disagrees with applicant for at least the following reasons: According to [0043] of the specification of the instant application “a protective layer 58 is optionally disposed in the electronic device 10 to cover the light absorption layer 24, part of the package units (60a and 60b), and the electrical connection structure 20b. In some embodiments, the material of the protective layer 58 may include any suitable material for planarization, protecting or isolating the underlying components, or for light absorption or light reflection”. Please, note that the optional protective layer 58 is essentially made of the same material as the first layer (light absorption layer 24), so for all intent and purposes, the protective layer can simply be an extension of the light absorption layer, i.e., the limitation of “a protective layer overlapped with the first layer” has no patentable weight because the first layer (light absorption layer 24) needs no protection.
Accordingly, Lee in view of Lim teaches a light absorption layer (first layer) and Kim further teaches an encapsulation (protection layer) layer (64, 68, or 72) that encases substrate 44 and devices 24 (see [0079] and figs. 13 and 15-16), wherein, if desired, openings may be formed in the layers 64, 68, and 72 that are aligned with some or all of the components 24 (i.e., the encapsulation layer may be formed to cover side walls of the components 24).
The examiner therefore contends that amended claims 1 and 17 are still obvious in view of the applied references Lee, Kim, and Lim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hsieh et al. (US Patent 10,643,980 B2)-supporting structure 76-see figs. 10A-10D).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571)272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SARDIS F AZONGHA/Primary Examiner, Art Unit 2627