DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Foreign Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 07/25/2024.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/22/2024 and 07/05/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claim 13 is objected to because of the following informalities: Claim 13 recites” the first diameter and the second diameter is different.” The Office suggests amending the claim to read “the first diameter and the second diameter are different.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-9 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated Liu et al. (PG Pub 2017/0125346; hereinafter Liu).
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Regarding claim 1, refer to Fig. 3 through Fig. 8 and Fig. 12 through Fig. 13 (primary emphasis on Fig. 13 provided above). Liu teaches a method of manufacturing a semiconductor package, comprising:
preparing a metal foil (seed layer; not shown; para [0024]) on a substrate 300; forming a first redistribution pattern 308 directly on the metal foil (para [0024]);
forming a vertical conductive structure 306 directly on the first redistribution pattern (see Fig. 3); removing the metal foil except for a portion vertically overlapping with the first redistribution pattern (para [0024]);
providing a semiconductor chip 200 having a chip pad 102 on the substrate (indirectly on; see Fig. 3);
removing the substrate (para [0048]); and
forming a second redistribution pattern 1000 on the chip pad and the first redistribution pattern (see Fig. 13).
Regarding to claim 2, refer to the figures cited above, Liu teaches forming an encapsulant 500 on the semiconductor chip 200 and the vertical conductive structure 306 before removing the substrate (see Fig. 12 and Fig. 13).
Regarding to claim 3, refer to the figures cited above, Liu teaches the metal foil (not shown) comprises copper (para [0024]).
Regarding to claim 4, refer to the figures cited above, Liu teaches providing an adhesive layer 302 between the metal foil (not shown) and the substrate 300 (para [0021]).
Regarding to claim 8, refer to the figures cited above, Liu teaches forming a third redistribution pattern (not numbered; para [0043]) directly on the vertical conductive structure 306, wherein the third redistribution pattern is spaced apart from the first redistribution pattern 308 with the vertical conductive structure in between (see Fig. 13).
Regarding to claim 9, refer to the figures cited above, Liu teaches providing the semiconductor chip 200 includes positioning the semiconductor chip laterally spaced apart from the first redistribution pattern 308 (see Fig. 13).
Regarding to claim 13, refer to the figures cited above, Liu teaches forming the vertical conductive structure 306 comprises forming a lower structure (within 308) on the first redistribution pattern 308 and forming an upper structure (306 within 500) on the lower structure (se Fig. 13), wherein the lower structure has a first diameter, wherein the upper structure has a second diameter, and wherein the first diameter and the second diameter is different from each other (see Fig. 13).
Regarding claim 14, refer to Fig. 3 through Fig. 8 and Fig. 12 through Fig. 13 (primary emphasis on Fig. 13 provided above). Liu teaches a method of manufacturing a semiconductor package, comprising:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
2. Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Liu, as applied to claim 1 above, and further in view of Karhade et al. (PG Pub 2016/0181218; hereinafter Karhade).
Regarding to claim 12, refer to the figures cited above, Liu teaches the substrate 300. Liu does not teach the material composition of the substrate as comprising a tape comprising polyimide.
In the same field of endeavor, Karhade teaches a semiconductor device comprising: a substrate; wherein the substrate comprises a polyimide tape 210 comprising polyimide (para [0015]; “tape substrate 210 may be a polyamide or polyimide.”)
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the temporary substrate of Lui comprise a polyimide tape, as taught by Karhade, for the purpose of choosing a suitable and well-known substrate material composition.
Prior Art
3. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
a. Buckalew et al. (PG Pub 2017/0243839) teaches a semiconductor device.
b. Yeh et al. (PG Pub 2022/0020700) teaches a semiconductor device.
Allowable Subject Matter
4. Claims 14-20 are allowable.
Claims 5-7 and 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 5 f providing the semiconductor chip comprises placing it directly on the adhesive layer.
Claim 6 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 6 forming the first redistribution pattern comprises: forming a first photo mask pattern having a first opening that defines a space for the first redistribution pattern; and performing an electroplating process using the metal foil as an electrode to form the first redistribution pattern in the first opening.
Claim 7 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 7, a second microelectronic die package over the plurality of passive device contacts, the second package having a plurality of package contacts to connect to the plurality of passive device contacts.
Claim 10 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 10, the first redistribution pattern comprises a first pad portion, a second pad portion horizontally separated from the first pad portion, and a first interconnection portion connecting the first pad portion and the second pad portion, wherein a diameter of the first pad portion is larger than a diameter of the second pad portion, wherein the vertical conductive structure is in contact with the first pad portion. Claim 11 would be allowable, because it depends on allowable claim 10.
Claim 14 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 14, forming a first redistribution pattern having a first surface and a second surface facing each other; forming a vertical conductive structure on the first surface of the first redistribution pattern; providing a semiconductor chip having an active surface chip pad laterally spaced apart from the first redistribution pattern; forming an encapsulant directly on the first surface of the first redistribution pattern and a side surface of the first redistribution pattern; and forming a lower redistribution substrate including a lower insulating layer and a second redistribution pattern directly on the second surface of the first redistribution pattern and the active surface of the semiconductor chip. Claims 15-19 would be allowable, because they depend on allowable claim 14.
Claim 20 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 20, providing a tape substrate including an adhesive layer; adhering a metal foil onto the adhesive layer, forming a first photo mask pattern on the metal foil, the first photo mask pattern having an opening for forming a first redistribution pattern; forming the first redistribution pattern in the opening; removing the first photo mask pattern; forming a second photo mask pattern exposing a portion of the first redistribution pattern, the second photo mask pattern having an opening for forming a vertical conductive structure; forming the vertical conductive structure on the first redistribution pattern; removing the second photo mask pattern; patterning the exposed metal foil to form a seed pattern by etching and removing a remaining portion of the metal foil except for a portion vertically overlapping with the first redistribution pattern; providing a first semiconductor chip on the exposed adhesive layer such that an active surface having a first chip pad faces the adhesive layer; forming an encapsulant to cover the first semiconductor chip and the vertical conductive structure; providing a first carrier substrate on the encapsulant; removing the adhesive layer and the tape substrate to expose a lower surface of the encapsulant, the seed pattern, and the first chip pad; forming a redistribution substrate on the first redistribution pattern and the first chip pad, the redistribution substrate including a first insulating layer and the first redistribution pattern.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTINA A SYLVIA/Examiner, Art Unit 2817
/ALI NARAGHI/Primary Examiner, Art Unit 2817
