Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/20/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Aikawa (U.S. Publication No 2007/0018625 A1).
Regarding claim 1, Aikawa teaches a voltage regulator with diode retention (e.g. Fig. 2), comprising:
an input terminal (e.g. 30/VDD)(Fig. 2), receiving a supply voltage (e.g. VDD)(Fig. 2);
an output terminal (e.g. 35)(Fig. 2), providing a regulated voltage (e.g. REG)(Fig. 2); and
a main circuit (e.g. 20, 31, 32, 33 )(Fig. 2), coupled between the input terminal and the output terminal to transform the supply voltage to a first voltage in a normal mode (e.g. REG output from main circuit)(Fig. 2)(Para [0052], ”perform a normal operation by the reference voltage circuit 10, the operational amplifier 20, the PMOS 31 and the resistances 32, 33. Meanwhile, the PMOS 51 and the NMOS 52 are both turned off in the switch circuit 50, to cut off the sub-regulator circuit 40 from the output terminal 35.”), wherein the first voltage is provided as the regulated voltage in the normal mode;
wherein in a sleep mode (e.g. 40)(Fig. 2)(Para [0053], “In sleep mode, power-down signals are provided as PD="L", PD1="H" and PD2="L", the reference voltage circuit 10 and the operational amplifier 20 are ceased from operating. Meanwhile, the PMOS 51 and the NMOS 52 are both turned on in the switch circuit 50, to output a power voltage SOUT of the sub-regulator circuit 40 through the output terminal 35”) the voltage regulator provides a diode (e.g. 41/46)(Fig. 2) connected between the input terminal and the output terminal, to generate a second voltage (e.g. Reg from circuit 40)(Fig. 2) as the regulated voltage,
wherein the second voltage is lower than the first voltage (Para [0012], “The voltage regulator according to the invention has the reference voltage circuit and amplifier circuit that ceases operation in sleep mode, and a sub-regulator circuit that, in sleep mode, generates the lower power voltage different from the internal power voltage and supplies same to the output terminal”).
Regarding claim 2, Aikawa teaches the main circuit has a power transistor (e.g. 31)(Fig. 2) connected between the input terminal and the output terminal of the voltage regulator, to generate an active current (Para [0034], “…the internal power voltage REG on the output terminal 35 is maintained constant in voltage regardless of the variations in the power voltage VDD or the load current flowing through the output terminal 35”) in the normal mode (Para [0033], “In normal operation mode, power-down signals are provided as PD="L", PD1="L" and PD2="H", to normally operate the reference voltage circuit 10 and power amplifier 20”), wherein the active current is fed to a load device (Para [0025], “The output terminal 35 is connected with a load circuit, not shown.”) connected to the output terminal of the voltage regulator; and
in the sleep mode, the power transistor is biased to turn off the active current (Para [0035], “…in sleep mode… to turn off the PMOS 31 and hence cut off the output terminal 35 from the power voltage VDD”), and the diode, which is another device different from the power transistor, is connected between the input terminal and the output terminal of the voltage regulator to provide a standby current to the load device (Para [0036], “At this time, in the sub-regulator circuit 40, because the power-down signal PD2 assumes "L" to turn the NMOS 48a and PMOS 48b off, the PMOS 41 of the reference-current circuit has a reference current to flow in a magnitude depending upon the power voltage VDD and the value of the resistance 43. Thus, the corresponding current to the reference current is caused to flow through the PMOS 46 of the current source constituting a current mirror relative to the PMOS 41. The current through the PMOS 46 flows to the ground GND through the PMOS 45 and NMOS 44 of the threshold-voltage output circuit, thus outputting to the node N3 a voltage in a magnitude corresponding to the threshold voltage VT of the PMOS 45 and NMOS 44. The voltage at the node N3 is outputted as a power voltage SOUT to the output terminal 35 through the operational amplifier 47”), wherein the standby current is lower than the active current (Para [0039], “The sub-regulator circuit 40 is provided to output, in sleep mode, a power voltage SOUT in a magnitude different from and basically lower than the internal power voltage REG in the normal operation”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Aikawa (U.S. Publication No 2007/0018625 A1) in view of Yang (U.S. Publication No 2022/0337158 A1).
Regarding claim 3, Aikawa teaches the main circuit has a power transistor (e.g. 31)(Fig. 2),
in the normal mode, the power transistor is biased to provide an active current to a load device connected to the output terminal of the voltage regulator (Para [0057], “in normal operation mode, to turn on the NMOS 34. Thus, the normal operation based on the reference voltage circuit 10, operational amplifier 20, PMOS 31 and resistances 32, 33. Meanwhile, the switch circuit 50 becomes off and the sub-regulator circuit 40A is cut off from the output terminal 35.); and
in the sleep mode, the power transistor is biased to turn off the active current, and the diode, which is another device different from, is connected between the input terminal and the output terminal of the voltage regulator to provide a standby current to the load device (Para [0035], “in sleep mode, the power-down signal PD1 is "H" and the reference voltage circuit 10 and operational amplifier 20 is cut off from the ground voltage GND and hence ceased from operating. Thus, no current flows to the reference voltage circuit 10 and operational amplifier 20. Meanwhile, the operational amplifier 20 has a detection voltage VD in "H", to turn off the PMOS 31 and hence cut off the output terminal 35 from the power voltage VDD”), wherein the standby current is lower than the active current (Para [0039], “The sub-regulator circuit 40 is provided to output, in sleep mode, a power voltage SOUT in a magnitude different from and basically lower than the internal power voltage REG in the normal operation”).
Aikawa does not teach wherein the power transistor is a metal-oxide-semiconductor field-effect transistor having a drain terminal coupled to the input terminal of the voltage regulator, and a source terminal coupled to the output terminal of the voltage regulator;
However, Yang discloses wherein the power transistor is a metal-oxide-semiconductor field-effect transistor (Para [0026], “…circuit 140 includes a PMOS transistor MP1”) having a drain terminal coupled to the input terminal (e.g. VDD2)(Fig. 1) of the voltage regulator, and a source terminal coupled to the output terminal (e.g. Out)(Fig. 1) of the voltage regulator (Fig. 2).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “Voltage regulator” teachings of Aikawa such that it comprises “wherein the power transistor is a metal-oxide-semiconductor field-effect transistor having a drain terminal coupled to the input terminal of the voltage regulator, and a source terminal coupled to the output terminal of the voltage regulator” as taught by Yang. The reason for doing so would be because it allows for a specific design choice, which can provide a reduction in component variance, thus increasing operational efficiencies.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Aikawa (U.S. Publication No 2007/0018625 A1) and Yang (U.S. Publication No 2022/0337158 A1) in further view of Mathur (U.S. Patent No 10637446).
Regarding claim 4, although Aikawa and Yang teach the limitations found in claim 3. They do not teach wherein the power transistor is a core device operated within a limited voltage range that is narrower than an operational range corresponding to the supply voltage.
However, Mathur discloses wherein the power transistor (e.g. MP5A)(Fig. 5) is a core device operated within a limited voltage range that is narrower than an operational range corresponding to the supply voltage (Col 6, Lines 59-62, “FIG. 9 in more detail for an exemplary 0.0V-1.8V IN signal at the input signal terminal of the receiver. The voltage range of the internal signals IN18, PSW18, and NSW18 are limited to 1.8V”).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “Voltage regulator” teachings of Aikawa and Yang such that it comprises “wherein the power transistor is a core device operated within a limited voltage range that is narrower than an operational range corresponding to the supply voltage” as taught by Mathur. The reason for doing so would be to operate the power transistor in a safe voltage range to prevent component damage.
Regarding claim 5, Mathur discloses without any high-voltage device, operated within a wider high-voltage range than the limited voltage range (Col 6, Lines 51-53, “Note that IN has a voltage range of 3.3V but the internal signals INH, PSW33, INL, and NSW33 are limited to a voltage range of 2.0V”), between the input terminal of the voltage regulator and the drain terminal of the power transistor.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Aikawa (U.S. Publication No 2007/0018625 A1) and Yang (U.S. Publication No 2022/0337158 A1) in further view of Coban (U.S. Publication No 2024/0393819 A1).
Regarding claim 6, although Aikawa and Yang teach the limitations found in claim 3. They do not teach wherein the diode is formed by a p-channel metal-oxide-semiconductor field-effect transistor having a source terminal coupled to the input terminal of the voltage regulator, a drain terminal coupled to the output terminal of the voltage regulator, and a gate terminal coupled to the drain terminal of the p-channel metal-oxide-semiconductor field-effect transistor.
However, Coban teaches wherein the diode is formed by a p-channel metal-oxide-semiconductor field-effect transistor (e.g. M4)(Fig. 2) having a source terminal coupled to the input terminal (e.g. VDD)(Fig. 2) of the voltage regulator, a drain terminal coupled to the output terminal (e.g. VSS)(Fig. 2) of the voltage regulator, and a gate terminal coupled to the drain terminal (e.g. 212)(Fig. 2) of the p-channel metal-oxide-semiconductor field-effect transistor.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “Voltage regulator” teachings of Aikawa and Yang such that it comprises “wherein the diode is formed by a p-channel metal-oxide-semiconductor field-effect transistor having a source terminal coupled to the input terminal of the voltage regulator, a drain terminal coupled to the output terminal of the voltage regulator, and a gate terminal coupled to the drain terminal of the p-channel metal-oxide-semiconductor field-effect transistor” as taught by Coban. The reason for doing so would be because it allows for a specific design choice, which can provide a reduction in component variance, thus increasing operational efficiencies.
Regarding claim 7, Yang teaches a current-to-voltage component (e.g. R2)(Fig. 3) coupled between the input terminal of the voltage regulator (e.g. VDD2)(Fig. 3) and the source terminal of the p-channel metal-oxide-semiconductor field-effect transistor (e.g. MP30)(Fig. 3).
Regarding claim 8, Coban teaches wherein the diode is formed by an n-channel metal-oxide-semiconductor field-effect transistor (e.g. M2)(Fig. 3) having a drain terminal (e.g. M2 drain)(Fig. 3) coupled to the input terminal (e.g. VDD)(Fig. 3) of the voltage regulator, a source terminal (e.g. M2 source)(Fig. 3) coupled to the output terminal (e.g. VSS)(Fig. 3) of the voltage regulator, and a gate terminal coupled to the drain terminal (e.g. 312)(Fig. 3) of the n-channel metal-oxide-semiconductor field-effect transistor.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Aikawa (U.S. Publication No 2007/0018625 A1), Yang (U.S. Publication No 2022/0337158 A1), and Coban (U.S. Publication No 2024/0393819 A1)in further view of Uehara (U.S. Publication No 2014/0368178 A1).
Regarding claim 9, although Aikawa, Yang, and Coban teach the limitations found in claim 8. They do not teach a current-to-voltage component coupled between the source terminal of the n-channel metal-oxide-semiconductor field-effect transistor and the output terminal of the voltage regulator.
However, Uehara teaches a current-to-voltage component (e.g. 105)(Fig. 4) coupled between the source terminal of the n-channel metal-oxide-semiconductor field-effect transistor (e.g. 401 source)(Fig. 4) and the output terminal (e.g. 110)(Fig. 4) of the voltage regulator.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “Voltage regulator” teachings of Aikawa, Yang, and Coban such that it comprises “a current-to-voltage component coupled between the source terminal of the n-channel metal-oxide-semiconductor field-effect transistor and the output terminal of the voltage regulator” as taught by Uehara. The reason for doing so would be because it provides for an output (load) transient control means, thus increasing operational efficiencies.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Aikawa (U.S. Publication No 2007/0018625 A1) and Yang (U.S. Publication No 2022/0337158 A1) in further view of Uehara (U.S. Publication No 2014/0368178 A1).
Regarding claim 10, although Aikawa and Yang teach the limitations found in claim 3. They do not teach wherein the diode is formed by a two-end component having an anode coupled to the input terminal of the voltage regulator and a cathode coupled to the output terminal of the voltage regulator.
However, Uehara teaches wherein the diode is formed by a two-end component (e.g. 201)(Fig. 2) having an anode coupled to the input terminal (e.g. 101)(Fig. 2) of the voltage regulator and a cathode coupled to the output terminal (e.g. 110)(Fig. 2) of the voltage regulator.
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “Voltage regulator” teachings of Aikawa and Yang such that it comprises “wherein the diode is formed by a two-end component having an anode coupled to the input terminal of the voltage regulator and a cathode coupled to the output terminal of the voltage regulator” as taught by Uehara. The reason for doing so would be because it provides for an output (load) transient control means, thus increasing operational efficiencies.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Aikawa (U.S. Publication No 2007/0018625 A1) and Yang (U.S. Publication No 2022/0337158 A1) in further view of Van Winkelhoff et. al. (U.S. Publication No 2012/0140585 A1).
Regarding claim 11, although Aikawa and Yang teach the limitations found in claim 3. They do not teach wherein the diode is formed by a core device as well as an input and output device connected in parallel with the core device; and the core device operates within a limited voltage range, and the input and output device operates within a wider high-voltage range than the limited voltage range.
However, Van Winkelhoff et. al. teaches wherein the diode is formed by a core device (e.g. 145)(Fig. 2) as well as an input and output device (e.g. 140)(Fig. 2) connected in parallel with the core device; and the core device operates within a limited voltage range, and the input and output device operates within a wider high-voltage range than the limited voltage range (Para [0009], “at least one p-type threshold device and at least one n-type threshold device, said p-type threshold devices and said n-type threshold devices respectively having a characteristic threshold voltage, wherein said at least one p-type threshold device and said at least one n-type threshold device in said retention voltage generation circuitry are connected in parallel between said supply voltage node and said retention voltage node, wherein a variation in said characteristic threshold voltage of either said at least one p-type threshold device or said at least one n-type threshold device in said functional circuitry, is accompanied by a corresponding variation in said characteristic threshold voltage of either said at least one p-type threshold device or said at least one n-type threshold device respectively in said retention voltage generation circuitry, thus maintaining at least said minimum voltage between said retention voltage node and said reference voltage node and thus keeping said functional circuitry in said data retention state”)(See Fig. 3A).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “Voltage regulator” teachings of Aikawa and Yang such that it comprises “wherein the diode is formed by a core device as well as an input and output device connected in parallel with the core device; and the core device operates within a limited voltage range, and the input and output device operates within a wider high-voltage range than the limited voltage range” as taught by Van Winkelhoff et. al. The reason for doing so would be because it provides for an output (load) transient control means, thus increasing operational efficiencies.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Aikawa (U.S. Publication No 2007/0018625 A1) and Yang (U.S. Publication No 2022/0337158 A1) in further view of Van Winkelhoff et. al. (U.S. Publication No 2012/0140585 A1).
Regarding claim 12, although Aikawa and Yang teach the limitations found in claim 3. They do not teach wherein the diode is formed by an n-channel metal-oxide-semiconductor field-effect transistor and a p-channel metal-oxide-semiconductor field-effect transistor; the n-channel metal-oxide-semiconductor field-effect transistor has a drain terminal coupled to the input terminal of the voltage regulator, a source terminal coupled to the output terminal of the voltage regulator, and a gate terminal coupled to the drain terminal of the n-channel metal-oxide-semiconductor field-effect transistor; and
the p-channel metal-oxide-semiconductor field-effect transistor has a source terminal coupled to the input terminal of the voltage regulator, a drain terminal coupled to the output terminal of the voltage regulator, and a gate terminal coupled to the drain terminal of the p-channel metal-oxide-semiconductor field-effect transistor.
However, Van Winkelhoff et. al. teaches wherein: the diode is formed by an n-channel metal-oxide-semiconductor field-effect transistor (e.g. 145)(Fig. 2) and a p-channel metal-oxide-semiconductor field-effect transistor (e.g. 140)(Fig. 2);
the n-channel metal-oxide-semiconductor field-effect transistor has a drain terminal coupled to the input terminal of the voltage regulator (e.g. 145 drain to 115)(Fig. 2), a source terminal coupled to the output terminal (e.g. 145 source to 120 )(Fig. 2) of the voltage regulator, and a gate terminal coupled to the drain terminal of the n-channel metal-oxide-semiconductor field-effect transistor (e.g. 145 drain connects to gate)(Fig. 2); and the p-channel metal-oxide-semiconductor field-effect transistor has a source terminal coupled to the input terminal of the voltage regulator (e.g. 140 source to 115)(Fig. 2), a drain terminal coupled to the output terminal (e.g. 140 drain to 120)(Fig. 2) of the voltage regulator, and a gate terminal coupled to the drain terminal of the p-channel metal-oxide-semiconductor field-effect transistor (e.g. 140 gate connects to drain)(Fig. 2). (Para [0039], “The retention voltage generation circuitry 100 comprises a PMOS transistor 140 and an NMOS transistor 145”).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “Voltage regulator” teachings of Aikawa and Yang such that it comprises “the diode formation” as taught by Van Winkelhoff et. al. The reason for doing so would be because it provides for an output (load) transient control means, thus increasing operational efficiencies.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Aikawa (U.S. Publication No 2007/0018625 A1) and Yang (U.S. Publication No 2022/0337158 A1) in further view of Guan et. al. (WO Publication No 2016/160324 A1).
Regarding claim 13, although Aikawa and Yang teach the limitations found in claim 3. They do not teach all the limitations found in claim 13. Aikawa teaches a first resistor (e.g. 32)(Fig. 3) and a first switch (e.g. 34)(Fig. 3) coupled in series between the source terminal of the power transistor and a ground terminal, wherein the first switch is closed in the normal mode, and is open in the sleep mode (Para [0046], “in normal operation mode, operates similarly to that of FIG. 2 because the NMOS 34 is turned on”, Para [0047], “ In sleep mode, because the power-down signal PD2 is "L", the NMOS 34 turns off”).
Aikawa and Yang do not teach a second switch placed between a gate terminal of the power transistor and the source terminal of the power transistor, wherein the second switch is open in the normal mode, and is closed in the sleep mode;
an operational amplifier, having a first input terminal receiving a reference voltage, and a second input terminal coupled to the source terminal of the power transistor; and
a third switch, coupled between an output terminal of the operational amplifier and the gate terminal of the power transistor, wherein the third switch is closed in the normal mode, and open in the sleep mode.
However, Guan et. al. teaches a second switch (e.g. 112)(Fig. 1) placed between a gate terminal (e.g. gate of 104)(Fig. 1) of the power transistor and the source terminal (e.g. source of 104 to 106/108)(Fig. 1) of the power transistor, wherein the second switch is open in the normal mode, and is closed in the sleep mode (Espacenet WO2016160324, Para [0040], “Switch110 can be open while external conditions are static (e.g. sleep mode). Then the quiescent current of LDO 100 can be zero. Gate charge may be lost due to leakage current or load current may fluctuate to cause a non-static case. Charge is adjusted on the gate of pass transistor 104 to compensate for the changes by charging up and down the gate with switches 111 and 112”);
an operational amplifier (e.g. 102)(Fig. 1), having a first input terminal receiving a reference voltage (e.g. Vref)(Fig. 1), and a second input terminal coupled to the source terminal of the power transistor (e.g. source of 104 to 106/108)(Fig. 1); and
a third switch (e.g. 110)(Fig. 1), coupled between an output terminal (e.g. output of 102)(Fig. 1) of the operational amplifier and the gate terminal of the power transistor (e.g. gate of 104)(Fig. 1), wherein the third switch is closed in the normal mode, and open in the sleep mode (Espacenet WO2016160324, Para [0038], “In the ultra-low power mode, switch 110 disconnects an output of error amplifier 102 from the gate of pass transistor 104”, Para [0039], “In the normal mode, switch 110 is closed”).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “Voltage regulator” teachings of Aikawa and Yang such that it comprises “the main circuit components” as taught by Guan et. al. The reason for doing so would be because it provides for an output (load) transient control means, thus increasing operational efficiencies.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Aikawa (U.S. Publication No 2007/0018625 A1) in further view of Van Winkelhoff et. al. (U.S. Publication No 2012/0140585 A1).
Regarding claim 20, although Aikawa teaches the limitations in claim 1. Aikawa does not teach a digital device including digital flip-flops, wherein the digital device is powered by the regulated voltage provided by the voltage regulator, with data retention in the sleep mode.
However, Van Winkelhoff et. al. teaches a digital device including digital flip-flops (e.g 110/125)(Fig. 2, 4B), wherein the digital device is powered by the regulated voltage provided by the voltage regulator (e.g. node 120 to 110 where flip flop is located)(fig. 2)(Para [0048], “…it will be appreciated that these techniques are not only applicable to a memory bitcell, but may be equally applied to any other circuitry component which requires the provision of a stable retention voltage in order for it to maintain a data retention state … Similarly, FIG. 4b schematically illustrates a retention flip flop which is similarly configured”), with data retention in the sleep mode (Figs. 5A and 5B).
Therefore, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the “Voltage regulator” teachings of Aikawa and Yang such that it comprises “a digital device” as taught by Van Winkelhoff et. al. The reason for doing so would be because it provide a regulated power to a digital load to prevent component damage, thus increasing operational efficiencies.
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 14, Aikawa teaches the main circuit has a power transistor (e.g. 31)(Fig. 2) connected between the input terminal and the output terminal of the voltage regulator, to generate an active current (Para [0034], “…the internal power voltage REG on the output terminal 35 is maintained constant in voltage regardless of the variations in the power voltage VDD or the load current flowing through the output terminal 35”) in the normal mode (Para [0033], “In normal operation mode, power-down signals are provided as PD="L", PD1="L" and PD2="H", to normally operate the reference voltage circuit 10 and power amplifier 20”), wherein the active current is fed to a load device (Para [0025], “The output terminal 35 is connected with a load circuit, not shown.”) connected to the output terminal of the voltage regulator.
Aikawa does not teach, in the sleep mode, a gate terminal of the power transistor is coupled to a drain terminal of the power transistor to form the diode that provides a standby current to the load device, wherein the standby current is lower than the active current. Prior art Guan et. al. (WO Publication No 2016/160324 A1) fig. 1 is considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “in the sleep mode, a gate terminal of the power transistor is coupled to a drain terminal of the power transistor to form the diode that provides a standby current to the load device, wherein the standby current is lower than the active current”. Claims 15-19 are indicated as allowable, as they depend on allowable claim 14.
Conclusion
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/JONATHAN WALTER SOILEAU/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838