DETAILED ACTION
INFORMATION CONCERNING RESPONSES
Response to Amendment
This Office Action is in response to applicant’s communication filed on April 26, 2026, in response to PTO Office Action mailed on February 27, 2026. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
In response to the last Office Action, claims 1, 8, and 15 have been amended. As a result, claims 1-20 are now pending in this application.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 25, 2026, has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on April 26, 2026, in response to PTO Office Action mailed on February 27, 2026, have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further review a new ground of rejection has been made in view of Strasser et al. (Publication Number US 2014/0056068 A1).
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1-2, 4-9, 11-16, and 18-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Biran et al. (Publication Number US 2006/0190668 A1) in view of Cheng et al. (Publication Number US 2005/0022046 A1) and Strasser et al. (Publication Number US 2014/0056068 A1).
As per claim 1, Biran et al. discloses “A system for data communication in a system-on-chip (SoC) (computer system architecture including a single chip computer system; Paragraph 0060), comprising: a first router in the SoC, the first router having a master request input port configured to receive register access request packets from an initiator and a master response output port configured to provide register access response packets to the initiator (through a register interface unit (RIU) 530 that handles input and outputs (denoted by the presence of two-way arrows between the RIU and the register rings 536 and 538); Paragraph 0035; FIG. 5), the first router further having a first ring interface including a first ring request output port and a first ring response input port, the first router still further having a second ring interface including a second ring request output port and a second ring response input port (The register interface unit (RIU) 530 is responsible for accepting Read/Write commands from the pervasive unit and delivering them on the respective register ring (emphasis on the word ‘respective’ indicating that the RIU is capable of routing/directing commands to the appropriate register ring); Paragraph 0035).” While Biran et al. discloses “and a plurality of register rings in the SoC, including a first register ring and a second register ring (register rings 536 and 538),” Biran et al. does not explicitly disclose the structure of the register ring as disclosed in the limitation “each register ring having a unidirectional data communication path between a ring input end and a ring output end, each register ring having at least one register in the unidirectional data communication path configured to receive register access request packets addressed to the register, the ring input end of the first register ring coupled to the first ring request output port, the ring output end of the first register ring coupled to the first ring response input port, the ring input end of the second register ring coupled to the second ring request output port, the ring output end of the second register ring coupled to the second ring response input port” or “and each register ring comprises at least one node, each node comprises a request packet decoder for decoding packets received from a ring interface or another node, and a request response packetizer for forming and sending packets to a ring interface or another node, the request packet decoder and request response packetizer being coupled to a plurality of control and status registers within a respective node.”
Cheng et al. discloses the structure of the register ring as disclosed in the limitation “each register ring having a unidirectional data communication path between a ring input end and a ring output end (where each ring has a single direction; FIG. 2-3), each register ring having at least one register in the unidirectional data communication path configured to receive register access request packets addressed to the register (By using the IP address of the node as part of the ID field 272; Paragraph 0129), the ring input end of the first register ring coupled to the first ring request output port, the ring output end of the first register ring coupled to the first ring response input port, the ring input end of the second register ring coupled to the second ring request output port, the ring output end of the second register ring coupled to the second ring response input port (as shown in [FIG. 5] where unidirectional rings connect to nodes 101 through ports 1 to 4; Paragraph 0085).”
Cheng et al. discloses “and each register ring in the SoC comprises at least one node, each node comprises a request packet decoder for decoding packets received from a ring interface or another node (Paragraph 0125), and a request response packetizer for forming and sending packets to a ring interface or another node (encapsulating packets; Paragraphs 0108 and 0123), the request packet decoder and request response packetizer being coupled to a plurality of control and status registers within a respective node (see the buffer used to stored data within a DR-enabled node; Paragraph 0092).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Biran et al. and Cheng et al. to enable efficient persistent data within a system of distributed processors [Paragraphs 0001-0002 and 0014].
However, Biran et al. and Cheng et al. do not disclose that each control and status register are storing data accessible by other components as disclosed in the limitation “each control and status register storing data accessible by the request packet decoder and request response packetizer.”
Strasser et al. discloses that each control and status register are storing data accessible by other components as disclosed in the limitation “each control and status register storing data accessible by the request packet decoder and request response packetizer (where the control & status register(s) 340 are accessible, through the control queues 342, to other components including a packetizer 302 and decoder 322; FIG. 3A; Paragraph 0084).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Biran et al. and Cheng et al. with elements of Strasser et al. to help determine usage history [Paragraph 0007].
As per claim 2, Cheng et al. discloses “The system of claim 1 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above), further comprising: a second router having a master request input port and a master response output port, and wherein the first router further includes a master request output port and a master response input port, the master request output port of the first router coupled to the master request input port of the second router and configured to provide the register access request packets, the master request input port of the first router coupled to the master response output port of the second router and configured to receive the register access response packets (as shown in [FIG. 5] where unidirectional rings connect to nodes 101 through ports 1 to 4; Paragraph 0085).”
As per claims 4 and 18, Biran et al. discloses “The system of claim 1 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above), wherein each ring interface includes an arbiter configured to arbitrate among register access request packets received from a plurality of initiators (Paragraph 0035).”
As per claims 5 and 19, Biran et al. discloses “The system of claim 1 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above), wherein each ring interface includes a first-in-first-out (FIFO) buffer (see the use of queues; Paragraphs 0033 and 0058).”
As per claims 6 and 20, Biran et al. discloses “The system of claim 1 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above), wherein: the master request input port is configured to receive a register access request packet from the initiator when the master request input port provides an asserted Master Request Ready signal to the initiator and the master request input port receives an asserted Master Request Valid signal from the initiator (valid marks; Paragraphs 0044 and 0056-0057).” Biran et al. discloses “and the master response output port is configured to provide a register access response packet to the initiator when the master response output port provides an asserted Master Response Valid signal to the initiator and the master response output port receives an asserted Master Response Ready signal from the initiator (valid marks; Paragraphs 0044 and 0056-0057).”
As per claim 7, Biran et al. discloses “The system of claim 1 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above), wherein: the first ring request output port is configured to provide the register access request packet to the ring input end of the first register ring while providing an asserted first Ring Request Valid signal to the ring input end of the first register ring (valid marks; Paragraphs 0044 and 0056-0057).” Biran et al. discloses “the second ring request output port is configured to provide the register access request packet to the ring input end of the second register ring while providing an asserted second Ring Request Valid signal to the ring input end of the second register ring (valid marks; Paragraphs 0044 and 0056-0057).” Biran et al. discloses “the first ring response input port is configured to receive the register access response packet from the ring output end of the first register ring when a first Ring Response Valid signal is asserted (valid marks; Paragraphs 0044 and 0056-0057).” Biran et al. discloses “and the second ring response input port is configured to receive the register access response packet from the ring output end of the second register ring when a second Ring Response Valid signal is asserted (valid marks; Paragraphs 0044 and 0056-0057).”
As per claim 8, Biran et al. discloses “A method for data communication in a system-on-chip (SoC) (computer system architecture including a single chip computer system; Paragraph 0060), comprising: receiving, by a master request input port of a first router in the SoC, a register access request packet from an initiator (through a register interface unit (RIU) 530 that handles input and outputs (denoted by the presence of two-way arrows between the RIU and the register rings 536 and 538); Paragraph 0035; FIG. 5).”
Biran et al. discloses “providing, by at least one of a first ring request output port of a first ring interface and a second ring request output port of a second ring interface, the register access request packet to a ring input end of one of a first register ring and a second register ring (The register interface unit (RIU) 530 is responsible for accepting Read/Write commands from the pervasive unit and delivering them on the respective register ring (emphasis on the word ‘respective’ indicating that the RIU is capable of routing/directing commands to the appropriate register ring); Paragraph 0035).” Biran et al. discloses “receiving, by one of a first ring response input port of the first ring interface and a second ring response input port of the second ring interface, a register access response packet from a ring output end of one of the first register ring and the second register ring (The register interface unit (RIU) 530 is responsible for accepting Read/Write commands from the pervasive unit and delivering them on the respective register ring (emphasis on the word ‘respective’ indicating that the RIU is capable of routing/directing commands to the appropriate register ring); Paragraph 0035).” Biran et al. discloses “and providing, by a master response output port of the first router, the register access response packet to the initiator (The register interface unit (RIU) 530 is responsible for accepting Read/Write commands from the pervasive unit and delivering them on the respective register ring (emphasis on the word ‘respective’ indicating that the RIU is capable of routing/directing commands to the appropriate register ring); Paragraph 0035).”
However, Biran et al. does not disclose “wherein each register ring comprises at least one node, each node comprises a request packet decoder for decoding packets from a ring interface or another node, and a request response packetizer for creating and sending packets to a ring interface or another node, the request packet decoder and request response packetizer being coupled to a plurality of control and status registers within a respective node.”
Cheng et al. discloses “wherein each register ring in the SoC comprises at least one node, each node comprises a request packet decoder for decoding packets from a ring interface or another node (Paragraph 0125), and a request response packetizer for creating and sending packets to a ring interface or another node (encapsulating packets; Paragraphs 0108 and 0123), the request packet decoder and request response packetizer being coupled to a plurality of control and status registers within a respective node (see the buffer used to stored data within a DR-enabled node; Paragraph 0092).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Biran et al. and Cheng et al. to enable efficient persistent data within a system of distributed processors [Paragraphs 0001-0002 and 0014].
However, Biran et al. and Cheng et al. do not disclose that each control and status register are storing data accessible by other components as disclosed in the limitation “each control and status register storing data accessible by the request packet decoder and request response packetizer.”
Strasser et al. discloses that each control and status register are storing data accessible by other components as disclosed in the limitation “each control and status register storing data accessible by the request packet decoder and request response packetizer (where the control & status register(s) 340 are accessible, through the control queues 342, to other components including a packetizer 302 and decoder 322; FIG. 3A; Paragraph 0084).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Biran et al. and Cheng et al. with elements of Strasser et al. to help determine usage history [Paragraph 0007].
As per claim 9, Cheng et al. discloses “The method of claim 8 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above) further comprising: providing, by a master request output port of the first router, the register access request packet to a master request input port of a second router (as shown in [FIG. 5] where unidirectional rings connect to nodes 101 through ports 1 to 4; Paragraph 0085).”
Cheng et al. discloses “providing, by a third ring request output port of the second router, the register access request packet to a ring input end of a third register ring (as shown in [FIG. 5] where unidirectional rings connect to nodes 101 through ports 1 to 4; Paragraph 0085).”
Cheng et al. discloses “and receiving, by a third ring response input port of the second router, the register access response packet from a ring output end of the third register ring (as shown in [FIG. 5] where unidirectional rings connect to nodes 101 through ports 1 to 4; Paragraph 0085).”
Cheng et al. discloses “and receiving, by a master response input port of the first router, the register access request packet from a master response output port of the second router (as shown in [FIG. 5] where unidirectional rings connect to nodes 101 through ports 1 to 4; Paragraph 0085).”
As per claim 11, Biran et al. discloses “The system of claim 1 (a as disclosed by Biran et al., Cheng et al., and Strasser et al. above), wherein each ring interface includes an arbiter configured to arbitrate among register access request packets received from a plurality of initiators (Paragraph 0035).”
As per claim 12, Biran et al. discloses “The method of claim 8 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above), further comprising, buffering, by a first-in-first-out (FIFO) buffer of each ring interface, a plurality of register access request packets (see the use of queues; Paragraphs 0033 and 0058).”
As per claim 13, Biran et al. discloses “The method of claim 8 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above), wherein: receiving the register access request packet from the initiator includes providing, by the master request input port, an asserted Master Request Ready signal to the initiator, and receiving, by the master request input port, an asserted Master Request Valid signal from the initiator (valid marks; Paragraphs 0044 and 0056-0057).” Biran et al. discloses “and providing the register access response packet to the initiator include providing, by the master response output port, an asserted Master Response Valid signal to the initiator, and receiving, by the master response output port, an asserted Master Response Ready signal from the initiator (valid marks; Paragraphs 0044 and 0056-0057).”
As per claim 14, Biran et al. discloses “The method of claim 8 (a as disclosed by Biran et al., Cheng et al., and Strasser et al. above), wherein: providing the register access request packet to the ring input end of one of the first register ring and the second register ring includes providing an asserted Ring Request Valid signal to the ring input end of the one of the first register ring and the second register ring (valid marks; Paragraphs 0044 and 0056-0057).” Biran et al. discloses “receiving the register access response packet includes receiving a Ring Response Valid signal from the ring output end of the one of the first register ring and the second register ring (valid marks; Paragraphs 0044 and 0056-0057).”
As per claim 15, Biran et al. discloses “A system-on-chip (SoC) (computer system architecture including a single chip computer system; Paragraph 0060), comprising: a plurality of registers (see the register rings 536 and 538; FIG. 5; Paragraph 0035).” Biran et al. discloses “a plurality of logic circuitry components configured to access the plurality of registers (through a register interface unit (RIU) 530 that handles input and outputs (denoted by the presence of two-way arrows between the RIU and the register rings 536 and 538); Paragraph 0035; FIG. 5).” Biran et al. discloses “and a first router, the first router having a master request input port configured to receive register access request packets from an initiator addressed to the plurality of registers and a master response output port configured to provide register access response packets to the initiator (through a register interface unit (RIU) 530 that handles input and outputs (denoted by the presence of two-way arrows between the RIU and the register rings 536 and 538); Paragraph 0035; FIG. 5), the first router further having a first ring interface including a first ring request output port and a first ring response input port, the first router still further having a second ring interface including a second ring request output port and a second ring response input port (The register interface unit (RIU) 530 is responsible for accepting Read/Write commands from the pervasive unit and delivering them on the respective register ring (emphasis on the word ‘respective’ indicating that the RIU is capable of routing/directing commands to the appropriate register ring); Paragraph 0035).” While Biran et al. discloses “wherein the plurality of registers are included in a plurality of register rings including a first register ring and a second register ring (register rings 536 and 538),” Biran et al. does not explicitly disclose the structure of the register ring as disclosed in the limitation “each register ring having at least one of the plurality of registers in a unidirectional data communication path between a ring input end and a ring output end,” “each register ring further comprises at least one node, each node comprises a request packet decoder for decoding packets received from a ring interface or another node, and a request response packetizer for creating and sending packets to a ring interface or another node, each respective request packet decoder and each respective request response packetizer being coupled to the plurality registers in a respective unidirectional data communication path of a respective node within a respective ring,” or “the ring input end of the first register ring coupled to the first ring request output port, the ring output end of the first register ring coupled to the first ring response input port, the ring input end of the second register ring coupled to the second ring request output port, the ring output end of the second register ring coupled to the second ring response input port.”
Cheng et al. discloses the structure of the register ring as disclosed in the limitation “each register ring having at least one of the plurality of registers in a unidirectional data communication path between a ring input end and a ring output end (as shown in [FIG. 5] where unidirectional rings connect to nodes 101 through ports 1 to 4; Paragraph 0085).”
Cheng et al. discloses “each register ring in the SoC further comprises at least one node, each node comprises a request packet decoder for decoding packets received from a ring interface or another node (Paragraph 0125), and a request response packetizer for creating and sending packets to a ring interface or another node (encapsulating packets; Paragraphs 0108 and 0123), each respective request packet decoder and each respective request response packetizer being coupled to the plurality registers in a respective unidirectional data communication path of a respective node within a respective register ring (see the buffer used to stored data within a DR-enabled node; Paragraph 0092).”
Cheng et al. discloses “the ring input end of the first register ring coupled to the first ring request output port, the ring output end of the first register ring coupled to the first ring response input port, the ring input end of the second register ring coupled to the second ring request output port, the ring output end of the second register ring coupled to the second ring response input port (as shown in [FIG. 5] where unidirectional rings connect to nodes 101 through ports 1 to 4; Paragraph 0085).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Biran et al. and Cheng et al. to enable efficient persistent data within a system of distributed processors [Paragraphs 0001-0002 and 0014].
However, Biran et al. and Cheng et al. do not disclose that each control and status register are storing data accessible by other components as disclosed in the limitation “each control and status register storing data accessible by the request packet decoder and request response packetizer.”
Strasser et al. discloses that each control and status register are storing data accessible by other components as disclosed in the limitation “each control and status register storing data accessible by the request packet decoder and request response packetizer (where the control & status register(s) 340 are accessible, through the control queues 342, to other components including a packetizer 302 and decoder 322; FIG. 3A; Paragraph 0084).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Biran et al. and Cheng et al. with elements of Strasser et al. to help determine usage history [Paragraph 0007].
As per claim 16, Cheng et al. discloses “The SoC of claim 15 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above), further comprising: a second router having a master request input port and a master response output port, and wherein the first router further includes a master request output port and a master response input port, the master request output port of the first router coupled to the master request input port of the second router and configured to provide the register access request packets, the master request input port of the first router coupled to the master response output port of the second router and configured to receive the register access response packets (as shown in [FIG. 5] where unidirectional rings connect to nodes 101 through ports 1 to 4; Paragraph 0085).” Cheng et al. discloses “and a third register ring of the plurality of register rings, the ring input end of the third register ring coupled to a ring request output port of the second router, the ring output end of the second register ring coupled to a ring response input port of the second router (as shown in [FIG. 5] where unidirectional rings connect to nodes 101 through ports 1 to 4; Paragraph 0085).”
Claims 3, 10, and 17 are rejected under 35 U.S.C. 103(a) as being unpatentable over Biran et al. (Publication Number US 2006/0190668 A1), Cheng et al. (Publication Number US 2005/0022046 A1), and Strasser et al. (Publication Number US 2014/0056068 A1) in view of Greenblat et al. (Publication Number US 2003/0172257 A1).
As per claims 3 and 17, Biran et al., Cheng et al., and Strasser et al. disclose “The system of claim 1 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above).” However, Biran et al., Cheng et al., and Strasser et al. do not disclose “wherein the first router is in a different clock domain or a different voltage domain from at least one of the first and second register rings.”
Greenblat et al. discloses “wherein the first router is in a different clock domain or a different voltage domain from at least one of the first and second register rings (see staggered clocking arrangement within a ring architecture; Paragraph 0092).”
Biran et al., Cheng et al., and Greenblat et al. are analogous art in that they in the field of register ring topology.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Biran et al., Cheng et al., and Strasser et al. with elements of Greenblat et al. to allow for extending a ring topology to external devices [Paragraph 0092].
As per claim 10, Biran et al., Cheng et al., and Strasser et al. disclose “The method of claim 8 (as disclosed by Biran et al., Cheng et al., and Strasser et al. above e).” However, Biran et al., Cheng et al., and Strasser et al. do not disclose “wherein the first router is in a different clock domain or a different voltage domain from at least one of the first and second register rings.”
Greenblat et al. discloses “wherein the first router is in a different clock domain or a different voltage domain from at least one of the first and second register rings (see staggered clocking arrangement within a ring architecture; Paragraph 0092).”
Biran et al., Cheng et al., and Greenblat et al. are analogous art in that they in the field of register ring topology.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Biran et al., Cheng et al., and Strasser et al. with elements of Greenblat et al. to allow for extending a ring topology to external devices [Paragraph 0092].
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach data transfer as they pertain to access to a buffer/register:
U.S. PATENT NUMBERS:
6,700,895 B1 – where the jitter buffer is accessible by the de-packetizer and the decoder [FIG. 5]
CONCLUDING REMARKS
Conclusion
The examiner requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
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/H.W.Y/Examiner, Art Unit 2181 August 4, 2026
/Farley Abad/Primary Examiner, Art Unit 2181
Prosecution Insights