DETAILED ACTION
This is a continuation of application 17/218,611.
Claims 1-20 rejected under non-statutory double patenting.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,056,499 B2. Although the claims at issue are not identical, they are not patentably distinct from each other as follows:
Claim 1
Present Application
‘499 Patent
“A computer system comprising:”
Claim 1: “A computer system comprising:”
“a plurality of operating systems (OS) each operating system including a graphics processing unit (GPU) driver; and”
Claim 1: “a plurality of operating systems, each operating system including a GPU driver;”
“a GPU including GPU firmware for controlling the execution of tasks at the GPU, wherein the GPU has access to a timer and further comprises a watchdog process and, for each operating system, a firmware timer register and an OS return register, wherein:”
Claim 1: “a graphics processing unit (GPU) including GPU firmware for controlling the execution of tasks at the graphics processing unit and, for each operating system:”
Claim 10: “the GPU having access to a timer and further comprising a watchdog process and, for each operating system, a firmware timer register and a OS return register wherein:”
“the watchdog process is configured to, for each operating system, periodically write the timer value into the firmware timer register,”
Claim 10: “the watchdog process is configured to, for each operating system, periodically write the timer value into the firmware timer register;”
“the GPU driver of each operating system is configured to periodically copy the timer value in the firmware timer register for that operating system into the OS return register for that operating system, and”
Claim 10: “the GPU driver is configured to periodically copy the timer value in the firmware timer register into the OS return register; and”
“the watchdog process is configured to, for each operating system, compare the OS return register to the firmware timer register so as to determine whether that operating system is online.”
Claim 10: “the watchdog process is configured to, for each operating system, compare the OS return register to the firmware timer register so as to determine whether that operating system is online.”
Claim 2
Present Application
‘499 Patent
“the graphics processing unit including, for each operating system”
Claim 1: “a graphics processing unit (GPU) including GPU firmware for controlling the execution of tasks at the graphics processing unit and, for each operating system
“a firmware state register modifiable by the GPU firmware and indicating whether the GPU firmware is online; and”
Claim 1: “an OS state register modifiable by the GPU driver of the respective operating system and indicating whether the GPU driver is online;”
Claim 3
Present Application
‘499 Patent
“the computer system comprising a memory management unit configured to mediate access to the registers of the GPU such that each operating system can access its respective registers but not those of other operating systems”
Claim 1: “a memory management unit configured to mediate access to the registers of the GPU such that each operating system can access its respective registers but not those of other operating systems.”
Claim 4
Present Application
‘499 Patent
“wherein each GPU driver is configured to, on loading at its operating system, modify its respective OS state register at the GPU to indicate that the GPU driver is online.”
Claim 3: “wherein each GPU driver is configured to, on loading at its operating system, modify its respective OS state register at the GPU to indicate that the GPU driver is online.”
Claim 5
Present Application
‘499 Patent
“wherein each GPU driver has write access to its respective OS state register and the GPU firmware has read but not write access to the OS state registers.”
Claim 6: “wherein each GPU driver has write access to its respective OS state register and the GPU firmware has read but not write access to the OS state registers.”
Claim 6
Present Application
‘499 Patent
“wherein the GPU firmware has write access to the firmware state registers and the GPU drivers have read but not write access to the firmware state registers.”
Claim 7: “wherein the GPU firmware has write access to the firmware state registers and the GPU drivers have read but not write access to the firmware state registers.”
Claim 7
Present Application
‘499 Patent
“wherein, if the watchdog process determines that an operating system is not online, the GPU firmware ignores any tasks scheduled for processing at the GPU for that operating system.”
Claim 11: “wherein, if the watchdog process determines that the operating system is not online, the GPU firmware ignores any tasks scheduled for processing at the GPU for that operating system.”
Claim 8
Present Application
‘499 Patent
“wherein the watchdog process is configured to perform its writing and comparing steps in respect of an operating system only while that operating system has tasks in a queue for processing at the GPU.”
Claim 12: “wherein the watchdog process is configured to perform its writing and comparing steps in respect of an operating system only while that operating system has tasks in a queue for processing at the GPU.”
Claim 9
Present Application
‘499 Patent
“wherein the computer system comprises a central processing unit (CPU) arranged to support a plurality of operating systems, the CPU including one or more processing cores at which the plurality of operating systems run.”
Claim 15: “further comprising a central processing unit (CPU) arranged to support the plurality of operating systems.”
Claim 10
Present Application
‘499 Patent
“wherein the watchdog process is configured to, for each operating system, periodically write the timer value into the firmware timer register according to a predefined period.”
Claim 10: “the watchdog process is configured to, for each operating system, periodically write the timer value into the firmware timer register.”
Claim 11
Present Application
‘499 Patent
“wherein the GPU driver of each operating system is configured to periodically copy the timer value in the firmware timer register for that operating system into the OS return register for that operating system according to the predefined period.”
Claim 10: “the watchdog process is configured to, for each operating system, periodically write the timer value into the firmware timer register.”
Claim 10: “the GPU driver is configured to periodically copy the timer value in the firmware timer register into the OS return register.”
Claim 12
Present Application
‘499 Patent
“wherein the watchdog process is configured to write the same timer value into the firmware timer register for each of the operating systems.”
Claim 10: “the watchdog process is configured to, for each operating system, periodically write the timer value into the firmware timer register.”
Claim 13
Present Application
‘499 Patent
“wherein the watchdog process is configured to write different timer values into the firmware timer register of each of the operating systems.”
Claim 10: “the watchdog process is configured to, for each operating system, periodically write the timer value into the firmware timer register.”
Claim 14
Present Application
‘499 Patent
“wherein the watchdog process is configured to write the timer value into the firmware timer register for an operating system at a frequency multiple of the periodicity at which the GPU driver of that operating system is configured to copy the timer value into the OS return register for that operating system.”
Claim 10: “the watchdog process is configured to, for each operating system, periodically write the timer value into the firmware timer register.”
Claim 10: “the GPU driver is configured to periodically copy the timer value in the firmware timer register into the OS return register.”
Claim 15
Present Application
‘499 Patent
“wherein the watchdog process is configured to compare the timer value in the OS return register for an operating system with the current value of the timer, to obtain an approximate time period since the GPU driver of that operating system last updated the OS return register for that operating system.”
Claim 10: “the GPU having access to a timer and further comprising a watchdog process and, for each operating system, a firmware timer register and a OS return register.”
Claim 10: “the watchdog process is configured to, for each operating system, compare the OS return register to the firmware timer register so as to determine whether that operating system is online.”
Claim 16
Present Application
‘499 Patent
“wherein the watchdog process is configured to conclude that an operating system is online if the timer value in the OS return register for that operating system matches the timer value in the firmware timer register for that operating system.”
Claim 10: “the GPU driver is configured to periodically copy the timer value in the firmware timer register into the OS return register.”
Claim 10: “the watchdog process is configured to, for each operating system, compare the OS return register to the firmware timer register so as to determine whether that operating system is online.”
Claim 17
Present Application
‘499 Patent
“wherein the watchdog process is configured to conclude that an operating system is offline if the timer value in the OS return register for that operating system does not match the timer value in the firmware timer register for that operating system.”
Claim 10: “the watchdog process is configured to, for each operating system, compare the OS return register to the firmware timer register so as to determine whether that operating system is online.”
Claim 11: “wherein, if the watchdog process determines that the operating system is not online, the GPU firmware ignores any tasks scheduled for processing at the GPU for that operating system.”
Claim 18
Present Application
‘499 Patent
“wherein, in response to concluding that an operating system is offline, the watchdog process is configured to cause the GPU firmware to offload any tasks being performed or scheduled to be performed for that operating system at the GPU.”
Claim 11: “wherein, if the watchdog process determines that the operating system is not online, the GPU firmware ignores any tasks scheduled for processing at the GPU for that operating system.”
Claim 19
Present claim 19 is rejected under non-statutory double patenting against claims 1, 10, and 18 (method embodiment) of the ‘499 patent, as indicated in the double patenting rejection of claim 1.
Claim 20
Present claim 20 is rejected under non-statutory double patenting against claims 1, 10, and 20 (medium embodiment) of the ‘499 patent, as indicated in the double patenting rejection of claim 1.
Allowable Subject Matter
Claims 1-20 allowable over prior art; but are subject to non-statutory double patenting rejections. Reasons for allowance held in abeyance until close of prosecution. Relevant art found in prior art search is cited in Form 892.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANK D MILLS whose telephone number is (571)270-3194. The examiner can normally be reached M-F 9-5:30 CT.
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/FRANK D MILLS/Primary Examiner, Art Unit 2194 September 16, 2026
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