DETAILED ACTION
This communication is responsive to Application #18765347 filed 07/08/2024. No Claim(s) amended; Claim(s) 1-21 canceled; Claim(s) 22-42 added. Claim(s) 22-42 is/are subject to examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22-42 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites the limitation “thread map register entries corresponding to a time delay which is greater than the first response latency or the second response latency”. It is unclear if the correspondence is (1) with a first time delay greater than the first response latency or a second time delay greater than the second response latency; (2) with second response latency or a time delay which is greater than the first response latency; or (3) with a time delay, wherein the time delay is greater that at least one of the first response latency or the second response latency. For the purpose of examination, the examiner will interpret the claim as (3) with a time delay, wherein the time delay is greater that at least one of the first response latency or the second response latency. Claims 23-35 are rejected as being dependent on claim 22.
Claim 22 recites the limitation “a number of thread map register entries corresponding to a time delay”. It is unclear if these entries are the same as, different from, or a subset of “a greater number of entries” earlier in the claim. For the purpose of examination, the examiner will interpret the entries in “a greater number of entries” as total number of thread_id values and “a number of thread map register entries” as a subset of the total number of thread_id values. Claims 23-35 are rejected as being dependent on claim 22.
Claim 23 recites the limitation "The s system" in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the examiner will interpret “The s system” as the same as the communication system of claim 22.
Claim 24 recites the limitation "The system" in line 1. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the examiner will interpret “The system” as the same as the communication system of claim 22.
Claim 25 recites the limitation “a media access controller for the first communications processor…a media access controller for the second communications processor…”. It is unclear whether the media access controllers for each respective communication processor are the same or different (“a first media access controller for the first communications processor…a media access controller for the second communication processor…”). For the purpose of examination, the examiner will interpret the media access controller as the same.
Claim 30 recites the limitation “the first communication protocol and second communication protocol”. It is unclear if second communication protocol is the same as “the second communication protocol” of claim 29. For the purpose of examination, the examiner will interpret “second communication protocol” as “the second communication protocol”. Claim 31 is rejected as being dependent on claim 30.
Claim 36 recites the limitation “a plurality of communications processors, each communications processor operative to…each communications processor of the plurality of communications processor”. It is unclear whether the first “each communications processor” is the same as the second “each communications processor of the plurality of communications processor” or different. For the purpose of examination, the examiner will interpret the claim to mean: “a plurality of communications processors, each communications processor of the plurality of communications processors operative to…each of the communications processor of the plurality of communications processors…”. Claims 37-39 are rejected as being dependent on claim 36.
Claim 36 recites the limitation "greater than the external interface response latency" in the last line. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the examiner will interpret the limitation to mean “greater than the response latency of the external interface”. Claims 37-39 are rejected as being dependent on claim 36.
Claim 37 recites the limitation “where at least one communications processor”. It is not clear if this at least one communications processor can include only the “plurality of communications processors” in claim 36; can include but is not limited to the “plurality of communications processors” in claim 36; or includes only communications processors outside of the “plurality of communications processors” in claim 36. For the purpose of limitations, the examiner will interpret the limitation as “where at least one communications processor of the plurality of communications processor”.
Claim 40 recites the limitation “a plurality of communications processors, each communications processor operative to…each communications processor of the plurality of communications processor”. It is unclear whether the first “each communications processor” is the same as the second “each communications processor of the plurality of communications processor” or different. For the purpose of examination, the examiner will interpret the claim to mean: “a plurality of communications processors, each communications processor of the plurality of communications processors operative to…each of the communications processor of the plurality of communications processors…”. Claims 41-42 are rejected as being dependent on claim 40.
Claim 40 recites the limitation "greater than the external interface response latency" in the last line. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the examiner will interpret the limitation to mean “greater than the response latency of the external interface”. Claims 41-42 are rejected as being dependent on claim 40.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22-25, 29-38, and 40-41 is/are rejected under 35 U.S.C. 103 as being unpatentable over TRAN (US 20070204137 A1) in view of POTASH (US 20220103990 A1) and DI BONA et al. (US 20110296111 A1), hereby referred to as BONA.
Claim 22:
TRAN teaches A communication system comprising: a multi-thread processor having stages forming a single execution pipeline and configured to execute a plurality of threads, each thread being executed according to a programmable thread map register identifying a particular thread to fetch an instruction on each successive instruction cycle, the programmable thread map register having a greater number of entries than a number of the plurality of threads (FIG 2 item 1105 the multithread microprocessor and para 73 (“…thread selector…includes an available thread identifier 1010 a register 1012 for identifying the previous dynamic thread that has been fetched…The thread selector 1013 used the last thread number from 1012 and the available thread identifier from 1010 to determine which thread to fetch…”) where the thread values can be in a programmable sequence; para 390 (“In multithreaded operations…veto selection…provide a round robin priority to thread issuance to the MAC unit…”) where the thread map register comprises a sequence of threads that each have an identifier);
a first communications processor operative to receive and transmit wireless packets compatible with a first communication protocol (TRAN: FIG 2 item 1430 the second communication processor using the second protocol, Bluetooth, item 1540 the first communication processor using the first protocol, WLAN);
a second communications processor operative to receive and transmit wireless packets compatible with a second communication protocol (TRAN: FIG 2 item 1430 the second communication processor using the second protocol, Bluetooth, item 1540 the first communication processor using the first protocol, WLAN);
However, TRAN does not explicitly disclose the programmable thread map register comprising a canonical sequence of programmable thread id values, the number of unique thread id values in the canonical sequence being less than a number of thread id values in the canonical sequence of thread id values in the programmable thread map register
POTASH, in the same field of endeavor, teaches the programmable thread map register comprising a canonical sequence of programmable thread id values, the number of unique thread id values in the canonical sequence being less than a number of thread id values in the canonical sequence of thread id values in the programmable thread map register (POTASH: FIG. 3A-3B and FIG. 5-6 the unique thread id values in the sequence less than a number of thread id values in the sequence,
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to have modified TRAN with POTASH, the combination hereby referred to as TRAN-POTASH, for the benefit of efficiency (POTASH: para 8) by adapting to varying thread workloads (POTASH: para 14) to preserve system integrity (POTASH: para 7).
However, TRAN-POTASH does not explicitly disclose a first thread of the plurality of threads configured to perform data operations on the first communication processor with an external interface, the external interface having a first response latency associated with the first communications processor; a second thread of the plurality of threads operative to perform data operations on the second communication processor with the external interface, the external interface having a second response latency associated with the second communications processor; and where a particular thread_id value for the first thread or the second thread is separated in the thread map register from other particular thread id values by a number of thread map register entries corresponding to a time delay which is greater than the first response latency or the second response latency
BONA, in the same field of endeavor, teaches threads configured to perform data operations on a communication processor with an external interface, the external interface having a response latency associated with the communications processor (BONA: para 157 (“When data is requested to be transmitted along a connection an outgoing packet is created, queued to be sent, and then held in case of a retransmission. A time-out with the clock thread is created to enable the retransmission to occur. When the data is acknowledged the time-out is cancelled along with the save packet being discarded…”) wherein the acknowledgment causes a response latency as there is a wait to see if retransmission is required) where a particular thread_id value for the first thread or the second thread is separated in the thread map register from other particular thread id values by a number of thread map register entries corresponding to a time delay which is greater than the first response latency or the second response latency (BONA: para 157 (“When data is requested to be transmitted along a connection an outgoing packet is created, queued to be sent, and then held in case of a retransmission. A time-out with the clock thread is created to enable the retransmission to occur.”) wherein when ack is not received within the latency response time, the time-out/time delay is not cancelled and therefore longer than the response latency to allow the retransmission to occur).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to have modified the two communication protocols of TRAN-POTASH with the latency response for retransmission in a communication protocol of BONA, the combination hereby referred to as TRAN-POTASH-BONA, for the benefit of handling retransmissions (BONA: para 141-142).
Claim 23:
TRAN-POTASH-BONA teaches the system of claim 22, where each thread_id is associated with a respective program counter, each said respective program counter identifying an address of an instruction to fetch (TRAN: para 119 (“N program counters (PCs) support the multi-threading of N respective threads…”) and Table 4 pg 22 (“Program Counter…holds the address of the instruction in thread…”)).
Claim 24:
TRAN-POTASH-BONA teaches the system of claim 22 where at least one of the first communication processor and the second communication processor each comprise an antenna, signal processing electronics, and a media access controller (MAC) coupled to the data interface for received packets and packets to transmit (TRAN: FIG. 2 item 1500 a communication processor with MAC, signal processing, and antenna).
Claim 25:
TRAN-POTASH-BONA teaches the system of claim 22 configured to execute at least one process thread servicing a media access controller for the first communications processor and also at least one process thread servicing a media access controller for the second communication processor (TRAN:FIG. 2 item 1540 (“WLAN RF”) and item 1430 (“Bluetooth”); and para 390 (“In multithreaded operations…veto selection…provide a round robin priority to thread issuance to the MAC unit…”)).
Claim 29:
TRAN-POTASH-BONA teaches the communication system of claim 22 where at least one of the first communication protocol or the second communication protocol is at least one of: a Wireless Local Area Network (WLAN) protocol, a Bluetooth protocol (TRAN: FIG. 2 item 1430 (“Bluetooth”) and item 1500 (“WLAN”); and para 87 (“…for use in various WLAN and UMA modem applications…”)).
Claim 30:
TRAN-POTASH-BONA teaches the communication system of claim 29 where the first communication protocol and second communication protocol are different protocols (TRAN: FIG. 2 item 1430 (“Bluetooth”) and item 1500 (“WLAN”); and para 87 (“…for use in various WLAN and UMA modem applications…”)).
Claim 31:
TRAN-POTASH-BONA teaches the communication system of claim 30 where the first communication protocol is a Wireless Local Area Network Protocol compatible with an 802.11 IEEE standard and the second communication protocol is a Bluetooth protocol (TRAN: FIG. 2 item 1430 (“Bluetooth”) and item 1500 (“WLAN”); and para 87 (“…for use in various WLAN and UMA modem applications…”)).
Claim 32:
TRAN-POTASH-BONA teaches the communication system of claim 22 where at least one of the first communication processor or second communication processor has a receive processor which comprises, in sequence, an antenna (TRAN: FIG. 2 multiple antennas), a low noise amplifier (TRAN: para 80 (“…coupled via…to receiving LNAs (low noise amplifiers)…”)), a mixer (TRAN: FIG. 2 item 1370 and para 80 (“…demodulator 1370 to produce the I/Q…”)), a low pass filter (TRAN: FIG. 2 item 1360 (“band-pass filters”)), and an analog to digital converter (TRAN: para 74 (“…(ABB) block 1210…includes…analog-to-digital conversion…”)) and baseband processor (TRAN: FIG. 2 item 1200 (“ABB/PM”) analog baseband chip) coupled to the media access controller (TRAN: FIG. 2 item 1510 (“MAC”)).
Claim 33:
TRAN-POTASH-BONA teaches the communication system of claim 22 where at least one of the first communications processor or the second communications processor includes a transmitter (TRAN: FIG. 2 item 1100-1500 the transmitter) coupled to the media access controller (TRAN: FIG. 2 item 1510 (“MAC”) the media access controller), the transmitter further comprising a baseband processor generating a baseband stream of symbols coupled to a mixer for conversion to an RF frequency (TRAN: FIG. 2 item 1200 the baseband processor and FIG. 2 item 1370 and para 80 (“…demodulator 1370 to produce the I/Q…”) the mixer), the mixer output coupled in sequence to an amplifier (TRAN: FIG. 2 item 1370 and para 80 (“…demodulator 1370 to produce the I/Q…”)) the mixer and para 80 (“…coupled via band-pass filters…to receiving LNAs (low noise amplifiers)…”)), transmit/receive switch (TRAN: para 80 (“Off-chip switchplexer 1350 couples wireless antenna and switch circuitry to both the transmit portion 1310, 1330 and the receive portion next described.”)), and an antenna (TRAN: FIG. 2 item 1540 antenna).
Claim 34:
TRAN-POTASH-BONA teaches the communication system of claim 22 where the first communications processor and the second communications processor are coupled to the multi-thread processor through a signal physical interface (TRAN: para 67 (“FIGS. 1 and 2 show a processor integrated circuit and a serial interface….”)) and para 71 (“…SPI (Serial Port Interface) are included in digital circuitry 1150.”)).
Claim 35:
TRAN-POTASH-BONA teaches the communication system of claim 22 where the external interface is at least one of Peripheral Component Interconnect (PCI), Serial Peripheral Interface (SPI), Secure Digital (SD) interface, or an interface providing an address and data to be read or written (TRAN: para 67 (“FIGS. 1 and 2 show a processor integrated circuit and a serial interface….”)) and para 71 (“…SPI (Serial Port Interface) are included in digital circuitry 1150.”)).
Claim 36:
TRAN teaches a communication system comprising: a multi-thread processor (TRAN: FIG. 2 item 11050) having stages forming a single execution pipeline and configured to execute a plurality of threads, each thread having a unique thread_id, each thread being executed according to a programmable thread map register identifying a particular thread to execute on each successive instruction cycle, the programmable thread map register having a greater number of entries than a number of the plurality of threads (FIG 2 item 1105 the multithread microprocessor and para 73 (“…thread selector…includes an available thread identifier 1010 a register 1012 for identifying the previous dynamic thread that has been fetched…The thread selector 1013 used the last thread number from 1012 and the available thread identifier from 1010 to determine which thread to fetch…”) where the thread values can be in a programmable sequence; para 390 (“In multithreaded operations…veto selection…provide a round robin priority to thread issuance to the MAC unit…”) where the thread map register comprises a sequence of threads that each have an identifier); a plurality of communications processors, each communications processor operative to receive and transmit wireless packets compatible with a respective communication protocol (TRAN: FIG 2 item 1430 the second communication processor using the second protocol, Bluetooth, item 1540 the first communication processor using the first protocol, WLAN).
However, TRAN does not explicitly disclose the programmable thread map register comprising a canonical sequence of the respective thread id values, the number of unique thread id values in the canonical sequence being less than a number of thread id values in the canonical sequence of programmable thread id values
POTASH, in the same field of endeavor, teaches the programmable thread map register comprising a canonical sequence of the respective thread id values, the number of unique thread id values in the canonical sequence being less than a number of thread id values in the canonical sequence of programmable thread id values (POTASH: FIG. 3A-3B and FIG. 5-6 the unique thread id values in the sequence less than a number of thread id values in the sequence).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to have modified TRAN with POTASH, the combination hereby referred to as TRAN-POTASH, for the benefit of efficiency (POTASH: para 8) by adapting to varying thread workloads (POTASH: para 14) to preserve system integrity (POTASH: para 7).
However, TRAN-POTASH does not explicitly disclose each communications processor of the plurality of communications processors having a respective thread of the plurality of threads configured to perform data operations on the respective communications processor with an external interface, the external interface having a response latency; where a particular thread id value for a respective thread is separated in the thread id register from other particular thread id values by a number of thread map register entries corresponding to a time delay which is greater than the external interface response latency.
BONA, in the same field of endeavor, teaches threads configured to perform data operations on the respective communications processor with an external interface, the external interface having a response latency (BONA: para 157 (“When data is requested to be transmitted along a connection an outgoing packet is created, queued to be sent, and then held in case of a retransmission. A time-out with the clock thread is created to enable the retransmission to occur. When the data is acknowledged the time-out is cancelled along with the save packet being discarded…”) wherein the acknowledgment causes a response latency as there is a wait to see if retransmission is required) where a particular thread id value for a respective thread is separated in the thread id register from other particular thread id values by a number of thread map register entries corresponding to a time delay which is greater than the external interface response latency (BONA: para 157 (“When data is requested to be transmitted along a connection an outgoing packet is created, queued to be sent, and then held in case of a retransmission. A time-out with the clock thread is created to enable the retransmission to occur.”) wherein when ack is not received within the latency response time, the time-out/time delay is not cancelled and therefore longer than the response latency to allow the retransmission to occur).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to have modified the two communication protocols of TRAN-POTASH with the latency response for retransmission in a communication protocol of BONA, the combination hereby referred to as TRAN-POTASH-BONA, for the benefit of handling retransmissions (BONA: para 141-142).
Claim 37:
TRAN-POTASH-BONA teaches the communication system of claim 36 where at least one communications processor is operative to transmit and receive wireless local area network (WLAN) packets, the communications processor having a media access controller for the transmission and reception of data using the data interface (TRAN: FIG. 2 item 1500 WLAN and item 1510 (“MAC”) the media access controller).
Claim 38:
TRAN-POTASH-BONA teaches the communication system of claim 36 where at least one communications processor is operative to transmit and receive Bluetooth Packets (TRAN: FIG 2 item 1430 Bluetooth).
Claim 40:
TRAN teaches a process for a communication system. For further limitations, see rejection for claim 36 above.
Claim 41:
TRAN-POTASH-BONA teaches the process of claim 40 where the plurality of process threads includes at least one process thread servicing a media access controller for a communications processor (TRAN: FIG. 2 item 1500 WLAN and item 1510 (“MAC”) the media access controller serviced by the multithreading processor).
Claim(s) 26-28, 39, and 42 is/are rejected under 35 U.S.C. 103 as being unpatentable over TRAN in view of POTASH and BONA, the combination hereby referred to as TRAN-POTASH-BONA, and in further view of KELSEY et al. (US 20030037228 A1), hereby referred to as KELSEY.
Claim 26:
TRAN-POTASH-BONA teaches the communication system of claim 22 but does not explicitly disclose where only thread_id values of threads associated with active communication interfaces are present in the thread map register.
KELSEY, in the same field of endeavor, teaches where only thread_id values of threads associated with active communication interfaces are present in the thread map register (KELSEY: para 60 (“Thread A is scheduled 50% of the time, thread B is scheduled 25% of the time…”) and para 62 (“There is no need for it to be scheduled when it is not active…”) wherein only active threads are present/scheduled).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to have modified TRAN-POTASH-BONA with KELSEY, hereby referred to as TRAN-POTASH-BONA-KELSEY, for the benefit of predictable allocation of thread (KESLEY: para 59).
Claim 27:
TRAN-POTASH-BONA-KELSEY teaches the communication system of claim 26 where the active communication interface are switched between an active state and an inactive state during mutually exclusive intervals (TRAN: para 119 (“…the symmetric multi-threading circuitry…rapidly switches to execute another thread…”) wherein threads for each communication interface is switched between) (KELSEY: para 60 (“Thread A is scheduled 50% of the time, thread B is scheduled 25% of the time…”) and para 62 (“There is no need for it to be scheduled when it is not active…”) wherein only active threads are present/scheduled).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to have modified TRAN-POTASH-BONA with KELSEY, hereby referred to as TRAN-POTASH-BONA-KELSEY, for the benefit of smaller memory buffers, faster response time, and reduced time delay (KESLEY: para 22).
Claim 28:
TRAN-POTASH-BONA teaches the system of claim 22, but does not explicitly disclose where the multi-thread processor also executes a thread map management process increasing the number of thread_id values associated with a particular communications processor when a greater number of packets is being transmitted or received by the particular communications processor than are being transmitted or received by a different communications processor.
KELSEY, in the same field of endeavor, teaches where the multi-thread processor also executes a thread map management process increasing the number of thread_id values associated with a particular communications processor when a greater number of packets is being transmitted or received by the particular communications processor than are being transmitted or received by a different communications processor (KELSEY: para 60 (“Thread A is scheduled 50% of the time, thread B is scheduled 25% of the time…”) and para 62 (“There is no need for it to be scheduled when it is not active…”) wherein different threads can be allocated more often).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to have modified TRAN-POTASH-BONA with KELSEY, hereby referred to as TRAN-POTASH-BONA-KELSEY, for the benefit of smaller memory buffers, faster response time, and reduced time delay (KESLEY: para 22).
Claim 39:
TRAN-POTASH-BONA teaches the communication system of claim 36, but does not explicitly disclose where at least one thread has associated thread_id values which are not in contiguous thread map register locations.
KELSEY, in the same field of endeavor, teaches where at least one thread has associated thread_id values which are not in contiguous thread map register locations (KELSEY: FIG. 7A-7C non-contiguous mapping).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to have modified TRAN-POTASH-BONA with KELSEY, hereby referred to as TRAN-POTASH-BONA-KELSEY, for the benefit of smaller memory buffers, faster response time, and reduced time delay (KESLEY: para 22).
Claim 42:
TRAN-POTASH-BONA teaches the process of claim 40 but does not explicitly disclose where at least one thread of the plurality of threads increases the number of thread_id values associated with a particular communications processor when a greater number of packets is being transmitted or received by the particular communications processor than are being transmitted or received by a different communications processor.
KELSEY, in the same field of endeavor, teaches where at least one thread of the plurality of threads increases the number of thread_id values associated with a particular communications processor when a greater number of packets is being transmitted or received by the particular communications processor than are being transmitted or received by a different communications processor (KELSEY: para 60 (“Thread A is scheduled 50% of the time, thread B is scheduled 25% of the time…”) and para 62 (“There is no need for it to be scheduled when it is not active…”) wherein different threads can be allocated more often).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to have modified TRAN-POTASH-BONA with KELSEY, hereby referred to as TRAN-POTASH-BONA-KELSEY, for the benefit of smaller memory buffers, faster response time, and reduced time delay (KESLEY: para 22).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
HASS et al. (US 20050033889 A1) para 74 teaches multi-threading and scheduling due to stall.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELIE T NGO whose telephone number is (571)272-0180. The examiner can normally be reached Mon - Thur: 8am - 5pm; 2nd Fri: 8am - 3pm.
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/A.T.N./Examiner, Art Unit 2416
/NOEL R BEHARRY/Supervisory Patent Examiner, Art Unit 2416
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