DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cottell (US 2014/0203843 A1 hereinafter Cottell), in view of Kempitiya (US 11,139,812 B2 hereinafter Kempitiya).
As to claim 1, Cottell discloses in Figs. 2, 3, a method for monitoring a semiconductor switch (20 as shown in Fig. 2) which has a control terminal (G as shown in Fig. 2), a current input terminal (C as shown in Fig. 2) and a current output terminal (E as shown in Fig. 2), the current input terminal being connected to a potential terminal (GD_V+ as shown in Fig. 2) via a reverse-connected diode (D1, D2 as shown in Fig. 2), a connection point of a capacitor (C1 as shown in Fig. 2) whose other connection point is connected to ground (V_E as shown in Fig. 2), a resistor component (R1, R3 as shown in Fig. 2) and a current source (pull-up current via R1 from GD_V+ as shown in Fig. 2), having the following steps: a) determining a DeSat voltage dropping across the capacitor at a first point in time and at a second point in time (para [0023]: "the output of the detector may be held below a level at which a desaturation routine in the optocoupler would be triggered until an output from the threshold setting element is detected."; para [0024]: "the threshold setting element being arranged to set a threshold voltage at the input at which the threshold setting element will provide an output at the output of the threshold setting element when the input voltage is exceeded" as shown in Figs. 2–3); b) determining a drain-source voltage dropping between the current input terminal and the current output terminal of the semiconductor switch at the first point in time from the DeSat voltage determined at the first point in time and the DeSat voltage determined at the second point in time (para [0022]; [0058]: "the detector being arranged to detect an output at the output of the threshold setting element and in response to provide a control signal at the output of the detector for the desaturation detection input to trigger a desaturation routine in the optocoupler." as shown in Fig. 2: Vce_trip_level calculated via V_GD_V+ − (V_BE_Q1 + i2(R7+R8+R2) + V_D1 + V_D2)).
Cottell does not disclose repeating steps a) and b) for a plurality of different first points in time and obtaining a plurality of drain-source voltages for the plurality of different first points in time; d) determining an operability of the semiconductor switch from the plurality of drain-source voltages for the plurality of different first timings.
However, Kempitiya discloses repeating steps a) and b) for a plurality of different first points in time and obtaining a plurality of drain-source voltages for the plurality of different first points in time ("The stored values are used to generate a lookup table 1504 including historical values of reconstructed current vs PWM value during normal operation … over several switching and/or fundamental cycles"; "repeated … during operation"; "When a new reconstructed current is generated during operation, it is compared with the historically expected value in the LUT to determine if a slow overload condition is present." as shown in Fig. 15: voltages sampled across L and integrated with capacitor C in op-amp for V_CE equivalents); d) determining an operability of the semiconductor switch from the plurality of drain-source voltages for the plurality of different first timings ("If a slow overload condition exists (for example if the new value is above an allowable threshold over the historical value) … the IGBT power device [is shut down] … due to IGBT or load degradation over several switching … cycles"; "The slow overload can be due to IGBT or load degradation over several switching and/or fundamental cycles (if, for example, the load is an electric machine)." as shown in Fig. 15).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify the system of Cottell and provide repeating steps a) and b) for a plurality of different first points in time and obtaining a plurality of drain-source voltages for the plurality of different first points in time; d) determining an operability of the semiconductor switch from the plurality of drain-source voltages for the plurality of different first timings, as taught by Kempitiya for tracking voltage/current trends over many cycles to detect gradual failure in automotive inverters.
As to claim 2, Cottell discloses The method according to claim 1 , wherein the DeSat voltage dropping across the capacitor is determined by means of a DeSat voltage measuring circuit. (para [0020]: "To limit the current drawn, a resistor R2 is provided in series with D1 and D2, with a typical value of around 100 Ω."; para [0022]: "a desaturation detection circuit for use between the desaturation detection input of an optocoupler and the output of a power switching device, the desaturation detection circuit comprising: a threshold setting element having an input and an output, the input for connection to the output of a power switching device via one or more diode(s)" as shown in Figs. 2–3).
As to claim 3, Cottell discloses The method according to claim 1 , wherein the current input terminal is connected to a DeSat terminal of a gate driver via the reverse-connected diode, the connection point of the capacitor and the resistor component, wherein the DeSat terminal of the gate driver is connected to the potential terminal via a current source of the gate driver. (para [0022]: "the input for connection to the output of a power switching device via one or more diode(s)"; para [0025]: "A first resistor network may be provided to couple the first switching element to the output of the power switching device via at least one diode and a second resistor network may be provided to couple the second switching element to the optocoupler" as shown in Figs. 2–3: diodes D1/D2, capacitor C1, resistors R1/R3, pull-up from GD_V+).
As to claim 4, Cottell discloses The method according to claim 3 , wherein the DeSat voltage dropping across the capacitor is determined within the gate driver. (para [0022]: "the detector being arranged to detect an output at the output of the threshold setting element and in response to provide a control signal at the output of the detector for the desaturation detection input to trigger a desaturation routine in the optocoupler." as shown in Fig. 2).
As to claim 5, the combination of Cottell and Kempitiya discloses The method according claim 1 , wherein the semiconductor switch is conductive at the first point in time and at the second point in time, and wherein the semiconductor switch is in particular non-conductive between the first point in time and the second point in time. (Kempitiya: "the integrator circuit 316 thereafter senses the voltage … during IGBT turn ON"; "The output of integrator circuit 316 is thus I CE (t), which is representative of the current flowing through IGBT 306." as shown in Fig. 3).
As to claim 6, the combination of Cottell and Kempitiya discloses The method according claim 1 , wherein the time between the first point in time and the second point in time is at most 10 ms or at most 25 ms or at most 50 ms or at most 100 ms. (Kempitiya: "over several switching and/or fundamental cycles"; "repeated … during operation" as shown in Fig. 15, where switching cycles in power electronics are typically in microseconds to milliseconds, making the time between points obvious within the claimed ranges for inverter operation).
As to claim 7, the combination of Cottell and Kempitiya discloses The method according to claim 1 , wherein the DeSat voltage determined at the first point in time is greater than the DeSat voltage determined at the second point in time. (Cottell, para [0024]: "the threshold setting element being arranged to set a threshold voltage at the input at which the threshold setting element will provide an output at the output of the threshold setting element when the input voltage is exceeded" as shown in Figs. 2–3, where voltage drops indicate desat conditions).
As to claim 8, the combination of Cottell and Kempitiya discloses The method according to claim 1 , wherein the second point in time corresponds to a point in time with the lowest possible current or a zero crossing of a load current curve. (Kempitiya: "When a new reconstructed current is generated during operation, it is compared with the historically expected value" as shown in Fig. 15, including low-current points in cycles).
As to claim 9, the combination of Cottell and Kempitiya discloses The method according to claim 1 , wherein the first point in time corresponds to a point in time with the highest possible current or a peak point or apex of a load current curve. (Kempitiya: "the integrator circuit 316 thereafter senses the voltage … during IGBT turn ON" for peak current sensing as shown in Fig. 3).
As to claim 10, Kempitiya discloses The method according to claim 1 , wherein determining the operability of the semiconductor switch from the plurality of drain-source voltages for the plurality of different first points in time comprises: comparing a drain-source voltage at a current first point in time with a drain-source voltage at an earlier first point in time, and determining an operability from the comparison result. ("When a new reconstructed current is generated during operation, it is compared with the historically expected value in the LUT to determine if a slow overload condition is present." as shown in Fig. 15).
As to claim 11, Kempitiya discloses The method according to claim 10 , wherein the comparison of the drain-source voltage at the current first point in time with the drain-source voltage at the earlier first point in time is carried out with the same load current within permissible tolerances and/or the same junction temperature within permissible tolerances. ("historical values of reconstructed current vs PWM value during normal operation" implying same conditions for comparison as shown in Fig. 15).
As to claim 12, Kempitiya discloses The method according to claim 10, further comprising: determining the operability of the semiconductor switch as insufficient when a difference between the drain-source voltage at the current first point in time with the drain-source voltage at the earlier first point in time exceeds a threshold value. ("If a slow overload condition exists (for example if the new value is above an allowable threshold over the historical value) … the IGBT power device [is shut down]" as shown in Fig. 15).
As to claim 13, Kempitiya discloses The method according to claim 1, further comprising: performing an action when the operability of the semiconductor switch is determined as insufficient. ("the IGBT power device [is shut down] … due to IGBT or load degradation" as shown in Fig. 15).
As to claim 14, Kempitiya discloses The method according to claim 1, further comprising: storing the plurality of drain-source voltages for the plurality of different first points in time in a memory device. ("The stored values are used to generate a lookup table 1504 including historical values" as shown in Fig. 15).
As to claim 15, the combination of Cottell and Kempitiya discloses The method according to claim 1 , wherein at least one of a high-side switch and a low-side switch of a half-bridge arrangement are monitored as semiconductor switch. (Cottell, para [0002]: "power switching device" in bridge configurations; Kempitiya: "IGBT power device" in inverters implying half-bridges as shown in Fig. 1).
As to claim 16, the combination of Cottell and Kempitiya discloses An inverter circuit for driving an electric machine, comprising at least one semiconductor switch and a control device, wherein the inverter circuit is adapted to perform a method according to claim 1 . (Kempitiya: "The slow overload can be due to IGBT or load degradation over several switching and/or fundamental cycles (if, for example, the load is an electric machine)." as shown in Fig. 15; Cottell para [0002]: inverter applications).
As to claim 17, Cottell discloses The inverter circuit according to claim 16 , having a gate driver with a DeSat terminal, the current input terminal of the semiconductor switch being connected to the DeSat terminal of the gate driver via the diode which is connected in the reverse direction, the connection point of the capacitor and the resistor component being connected to the DeSat terminal of the gate driver, the DeSat terminal of the gate driver being connected to the potential terminal via the current source. (para [0022]: "the input for connection to the output of a power switching device via one or more diode(s)"; para [0025]: "A first resistor network may be provided to couple the first switching element to the output of the power switching device via at least one diode" as shown in Figs. 2–3).
As to claim 18, the combination of Cottell and Kempitiya discloses An inverter circuit according to claim 16 , further comprising a DeSat voltage measuring circuit for detecting the DeSat voltage, which is electrically isolated and connected to the control device. (Cottell, para [0022]: "desaturation detection circuit ... optocoupler" implying isolation as shown in Fig. 2).
As to claim 19, the combination of Cottell and Kempitiya discloses An inverter circuit according to claim 16 , wherein the gate driver is connected to the control device via a digital data interface for transmitting the DeSat voltage. (Kempitiya: "the integrator circuit 316 thereafter senses the voltage" and comparison logic implying data transmission as shown in Fig. 3).
Conclusion
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/TUNG X NGUYEN/Primary Examiner, Art Unit 2858 3/14/2026