DETAILED ACTION
Claims 1-20 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Easton et al. (U.S. PGPub No. 2011/0173615) in view of Cho et al. (U.S. PGPub No. 2012/0131266).
Claim 1
Easton (2011/0173615) teaches:
A computing system comprising:
a host configured to distribute and allocate process data associated with a plurality of processes to a plurality of logic addresses, P. 0251 the program begins to execute, and selects the next QDIO buffer to be transferred to the adapter. The program fills in the storage block address list (SBAL) with the program absolute addresses of the storage blocks to be transferred
determine a valid bit corresponding to a logic address among a plurality of logic addresses, P. 0297 the contents of the program SBAL are copied to the host's SBAL; P. 0298 a pin is acquired for a program absolute storage block address in the host SBAL, and the pinned page indicator in the host's SBAL is set
the valid bit indicating whether a process among the plurality of the processes corresponding to the logic address is executing, and P. 0179 host pages are pinned for the duration of an FCP I/O operation
generate an update information including the valid bit and the logic address corresponding to the valid bit; and P. 0146-149 a storage block address list entry (SBALE) includes an absolute storage address of a storage block 526 and flags including a pinned page indicator
Easton does not explicitly teach sending an address and valid bit to a storage device.
Cho (2012/0131266) teaches:
generate an update information including the valid bit and the logic address corresponding to the valid bit; and P. 0077 and FIG. 5 the host 20 may store information about the attributes of the data, i.e., data attribute information in a reserved bit
a storage device configured to receive the update information from the host. P. 0078 the address and data attribute information may be transmitted together from the host 20 to the controller 120; FIG. 1 and P. 0042 data storage system 100 includes controller 120
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Easton with sending an address and valid bit to a storage device taught by Cho
The motivation being to analyze attribute information using the upper most bits of transmitted address bits (see Cho P. 0078)
The systems of Easton and Cho are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Easton with Cho to obtain the invention as recited in claims 1-8.
Claim 3
Easton (2011/0173615) teaches:
The computing system of claim 1, wherein the host is configured to generate the update information in response to the valid bit changing. P. 0298 a pin is acquired for a program absolute storage block address in the host SBAL, and the pinned page indicator in the host's SBAL is set
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Easton et al. (U.S. PGPub No. 2011/0173615) in view of Cho et al. (U.S. PGPub No. 2012/0131266) in view of Mills et al. (U.S. PGPub No. 2021/0240605).
Claim 2
The systems of Easton and Cho do not explicitly teach performing garbage collection based on the valid bit indicating a process is not executing.
Mills (2021/0240605) teaches:
The computing system of claim 1, wherein the storage device includes a plurality of non-volatile memories, FIG. 1 and P. 0025 storage media 1 118 may be a SSD and the storage device is configured to perform garbage collection on the plurality of non-volatile memories based on the update information. P. 0043 if the pin status 210 indicates that a conditional lock has just timed-out, module 214 can flag the data blocks 113, in that specific ones of the LBA range 121, as free to relocate; P. 0057 tiering data movement engine 120 can move the data blocks 113 associated with an LBA range 313 to a new physical address
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Easton and Cho with performing garbage collection based on the valid bit indicating a process is not executing taught by Mills
The motivation being to improve the performance of the host processor 102 without user intervention (See Mills P. 0037)
The systems of Easton, Cho and Mills are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Easton and Cho with Mills to obtain the invention as recited in claim 2.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Easton et al. (U.S. PGPub No. 2011/0173615) in view of Cho et al. (U.S. PGPub No. 2012/0131266) in view of Kanno et al. (U.S. PGPub No. 2018/0173430)
Claim 8
The systems of Easton and Cho do not explicitly teach allocating addresses to process data based on a input/output speed of the process data.
Kanno (2018/0173430) teaches:
The computing system of claim 1, wherein the host is configured to distribute and allocate the process data to the plurality of logic addresses based on at least one of a consistency or an input/output speed of the process data. P. 0100 host 2 is able to designate a bandwidth (i.e., bit rate) for communication with each virtual SSD (VSSD); P. 0094 VSSD creation unit 21 allocates a capacity to an VSSD based on a request from the host 2 that designates a user capacity (user capacity corresponds to a user accessible LBA space, see P. 0090); P. 0064 VSSD management command includes various parameters for providing a VSSD suitable for storage requirements of an individual user
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Easton and Cho with allocating addresses to process data based on a input/output speed of the process data taught by Kanno
The motivation being improvement of I/O performance of the host (See Kanno P. 0046)
The systems of Easton, Cho and Kanno are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Easton and Cho with Kanno to obtain the invention as recited in claim 8.
Claim(s) 9 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Easton et al. (U.S. PGPub No. 2011/0173615) in view of Mills et al. (U.S. PGPub No. 2021/0240605).
Claim 9
Easton (2011/0173615) teaches:
A method of a computing system comprising:
distributing and allocating process data associated with a plurality of processes to respective ones of a plurality of logic addresses, P. 0251 the program begins to execute, and selects the next QDIO buffer to be transferred to the adapter. The program fills in the storage block address list (SBAL) with the program absolute addresses of the storage blocks to be transferred
determining a valid bit corresponding to a logic address among a plurality of logic addresses, P. 0297 the contents of the program SBAL are copied to the host's SBAL; P. 0298 a pin is acquired for a program absolute storage block address in the host SBAL, and the pinned page indicator in the host's SBAL is set
the valid bit indicating whether a process among the plurality of processes corresponding to the logic address is executing, P. 0179 host pages are pinned for the duration of an FCP I/O operation
generating update information including the valid bit and the logic address corresponding to the valid bit, P. 0146-149 a storage block address list entry (SBALE) includes an absolute storage address of a storage block 526 and flags including a pinned page indicator
Easton does not explicitly teach mapping the logic address to an address in non-volatile memory, and performing garbage collection based on the valid bit indicating a process is not executing.
Mills (2021/0240605) teaches:
mapping a first logic address among the plurality of logic addresses of a first type to a storage address for a storage device including a non-volatile memory, and P. 0029 block storage virtualization module 132 maps virtual logical block addresses (LBAs) into physical block addresses; FIG. 1 and P. 0025 storage media 1 118 may be a SSD
performing garbage collection on the storage device at the storage address corresponding to the logic address in response to the valid bit indicating that the process is not executing based on the update information. P. 0043 if the pin status 210 indicates that a conditional lock has just timed-out, module 214 can flag the data blocks 113, in that specific ones of the LBA range 121, as free to relocate; P. 0057 tiering data movement engine 120 can move the data blocks 113 associated with an LBA range 313 to a new physical address
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Easton with mapping the logic address to an address in non-volatile memory, and performing garbage collection based on the valid bit indicating a process is not executing taught by Mills
The motivation being to improve the performance of the host processor 102 without user intervention (See Mills P. 0037)
The systems of Easton and Mills are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Easton with Mills to obtain the invention as recited in claims 9-14.
Claim 14
Easton (2011/0173615) teaches:
The method of the computing system of claim 9, wherein the generating of the update information includes generating the update information in response to the valid bit changing. P. 0297 the contents of the program SBAL are copied to the host's SBAL; P. 0298 a pin is acquired for a program absolute storage block address in the host SBAL, and the pinned page indicator in the host's SBAL is set
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Easton et al. (U.S. PGPub No. 2011/0173615) in view of Mills et al. (U.S. PGPub No. 2021/0240605) in view of Yang et al. (U.S. PGPub No. 2025/0217037).
Claim 10
The systems of Easton and Mills do not explicitly teach a CXL memory including a volatile memory.
Yang (2025/0217037) teaches:
The method of the computing system of claim 9, further comprising: mapping a second logic address of a second type among the plurality of logic addresses to a CXL memory address for a CXL memory including a volatile memory. P. 0075 and FIG. 1 a controller of each type of storage medium stores a first mapping relationship between a physical address and a virtual address; P. 0062 and FIG. 2 electronic device 200 is connected to a storage device 105 through a CXL bus, storage device 105 includes storage medium 31; P. 0054 types of storage media 31 include phase-change memory (PCM) 312, and a double data rate synchronous dynamic random-access memory (DDR) 313
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Easton and Mills with a CXL memory including a volatile memory taught by Yang
The motivation being CXL is a well-known bus standard, and volatile memory (see Yang P. 0061) and double data rate synchronous dynamic random-access memory is a well-known type of storage media (see Yang P. 0054)
The systems of Easton, Mills and Yang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Easton and Mills with Yang to obtain the invention as recited in claim 10-12.
Claim 11
Yang (2025/0217037) teaches:
The method of the computing system of claim 10, further comprising: mapping a third logic address among the plurality of logic addresses of a third type to the CXL memory address for a host memory including a volatile memory. FIG. 1 and P. 0054 types of storage media 31 include static random access high bandwidth memory (HBM) 311; P. 0075 and FIG. 1 a controller of each type of storage medium stores a first mapping relationship between a physical address and a virtual address
Claim 12
Yang (2025/0217037) teaches:
The method of the computing system of claim 11, wherein the generating of the update information includes generating the update information including the valid bit that corresponds to the logic address selected from the first logic address of the first type, a second logic address of the second type, or a third logic address of the third type. P. 0121 medium attribute identifier indicates the storage medium to which the storage unit belongs, and includes two storage media: a DDR and a PCM
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Easton et al. (U.S. PGPub No. 2011/0173615) in view of Mills et al. (U.S. PGPub No. 2021/0240605) in view of Kanno et al. (U.S. PGPub No. 2018/0173430)
Claim 13
The systems of Easton and Mills do not explicitly teach allocating addresses to process data based on a input/output speed of the process data.
Kanno (2018/0173430) teaches:
The method of the computing system of claim 9, wherein the distributing and assigning to the plurality of logic addresses includes distributing and assigning the process data to the plurality of logic addresses based on at least one of a consistency or an input/output speed of the process data. P. 0100 host 2 is able to designate a bandwidth (i.e., bit rate) for communication with each virtual SSD (VSSD); P. 0094 VSSD creation unit 21 allocates a capacity to an VSSD based on a request from the host 2 that designates a user capacity (user capacity corresponds to a user accessible LBA space, see P. 0090); P. 0064 VSSD management command includes various parameters for providing a VSSD suitable for storage requirements of an individual user
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Easton and Mills with allocating addresses to process data based on a input/output speed of the process data taught by Kanno
The motivation being improvement of I/O performance of the host (See Kanno P. 0046)
The systems of Easton, Mills and Kanno are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Easton and Mills with Kanno to obtain the invention as recited in claim 13.
Claim(s) 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. PGPub No. 2025/0217037) in view of Easton et al. (U.S. PGPub No. 2011/0173615) in view of Mills et al. (U.S. PGPub No. 2021/0240605).
Claim 15
Yang (2025/0217037) teaches:
A CXL device comprising: a CXL storage including a non-volatile memory corresponding to a first type of a first logic address among a plurality of logic addresses, P. 0062 and FIG. 2 electronic device 200 is connected to a storage device 105 through a CXL bus, storage device 105 includes storage medium 31; P. 0054 storage media 31 includes phase-change memory (PCM)
the CXL storage is configured to receive a valid bit corresponding to the first logic address among the plurality of logic addresses, the valid bit indicating whether a process among a plurality of processes corresponding to the first logic address of the first type […] P. 0121 medium attribute identifier indicates the storage medium to which the storage unit belongs, and includes two storage media: a DDR and a PCM
[…] a CXL memory including a volatile memory corresponding to a second type of a second logic address among the plurality of logic addresses. P. 0175 the source medium attribute identifier is a medium attribute identifier of the storage medium to which the source storage unit belongs; P. 0077 the medium attribute identifier indicates the second storage medium
Yang does not explicitly teach the valid bit indicating a process is not executing.
Easton (2011/0173615) teaches:
the valid bit indicating whether a process among a plurality of processes corresponding to the first logic address of the first type is executing P. 0251 the program begins to execute, and fills in the storage block address list (SBAL) with the program absolute addresses of the storage blocks to be transferred; . 0298 a pin is acquired for a program absolute storage block address in the host SBAL, and the pinned page indicator in the host's SBAL is set; P. 0179 host pages are pinned for the duration of an FCP I/O operation
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Yang with the valid bit indicating a process is not executing taught by Easton
The motivation being to indicate that the contents of a host page are pinned in a host page frame (see Easton P. 0304)
The systems of Yang and Easton do not explicitly teach performing garbage collection based on the valid bit
Mills (2021/0240605) teaches:
perform garbage collection for the non-volatile memory based on the valid bit; and P. 0043 if the pin status 210 indicates that a conditional lock has just timed-out, module 214 can flag the data blocks 113, in that specific ones of the LBA range 121, as free to relocate; P. 0057 tiering data movement engine 120 can move the data blocks 113 associated with an LBA range 313 to a new physical address
It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Yang and Easton with performing garbage collection based on the valid bit taught by Mills
The motivation being to improve the performance of the host processor 102 without user intervention (See Mills P. 0037)
The systems of Yang, Easton and Mills are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Yang and Easton with Mills to obtain the invention as recited in claims 15-20.
Claim 16
Yang (2025/0217037) teaches:
The CXL device of claim 15, further comprising: a CXL controller is configured to map the first logic address of the first type to a CXL storage address for the CXL storage, and map the second logic address of the second type to a CXL memory address for the CXL memory. P. 0075 and FIG. 1 a controller of each type of storage medium stores a first mapping relationship between a physical address and a virtual address; P. 0054 types of storage media 31 include phase-change memory (PCM) 312, and a double data rate synchronous dynamic random-access memory (DDR) 313
Claim 17
Yang (2025/0217037) teaches:
The CXL device of claim 16, wherein the CXL storage includes a flash translation layer (FTL) that maps the CXL storage address to a physical address of the non- volatile memory. P. 0075 a controller of each type of storage medium stores a first mapping relationship between a physical address and a virtual address; P. 0054 types of storage media 31 include phase-change memory (PCM) 312
Claim 18
Mills (2021/0240605) teaches:
The CXL device of claim 17, wherein the FTL performs the garbage collection at the CXL storage address of the CXL storage corresponding the valid bit indicating the process that is not executing. P. 0043 if the pin status 210 indicates that a conditional lock has just timed-out, module 214 can flag the data blocks 113, in that specific ones of the LBA range 121, as free to relocate; P. 0057 tiering data movement engine 120 can move the data blocks 113 associated with an LBA range 313 to a new physical address
Claim 19
Yang (2025/0217037) teaches:
The CXL device of claim 16, wherein the CXL controller is configured to receive the valid bit through a CXL interface. P. 0062 and FIG. 2 electronic device 200 is connected to a storage device 105 through a CXL bus, storage device 105 includes storage medium 31; P. 0121 medium attribute identifier indicates the storage medium to which the storage unit belongs, and includes two storage media: a DDR and a PCM; P. 0077a data migration request includes an address and a medium attribute identifier
Claim 20
Easton (2011/0173615) teaches:
The CXL device of claim 15, wherein the CXL storage is configured to receive the valid bit in response to the executing of the process changes. P. 0297 the contents of the program SBAL are copied to the host's SBAL; P. 0298 a pin is acquired for a program absolute storage block address in the host SBAL, and the pinned page indicator in the host's SBAL is set
Allowable Subject Matter
Claims 4-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 recites the limitation “a CXL device logically connected to the host through a CXL interface, wherein the CXL device includes the storage device, and wherein a CXL controller is configured to map a first type of a first logic address among the plurality of logic addresses to a storage address for the storage device”
Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0020, 00112 and FIG. 1]. Said limitations, in combination with the other recited limitations of claim 4, are not taught or suggested by a reasonable combination of the prior art of record. None of the references teach both a host device which determines a valid bit corresponding to an address associated with a currently executing process, and sends the address and valid bit to a storage device, where the address is mapped to a storage within a CXL device.
Claims 5-7 depend from claim 4, and are considered allowable for at least the same reasons as claim 4.
Response to Arguments
Applicant's arguments filed 1/27/2026 have been fully considered but they are not persuasive.
The applicant states “The cited portion of Mills describes that data blocks can be flagged as free to relocate when a pin status indicates that a conditional lock has just timed out. Mills further describes that the conditional lock may be a time-based lock. (Mills, 0028). Mills does not describe that the conditional lock is based on whether a process is executing and the description that the conditional lock is a time-based lock indicates that the conditional lock does not depend on whether an indication of whether a process is executing. Therefore, Mills also does not describe performing garbage collection based on a valid bit of the update information indicating whether the process is executing, as recited by independent claim 1.”
The examiner respectfully notes the rejection is based on a combination of Easton and Mills, and while Mill’s conditional lock does not teach the functionality of the claimed valid bit, Easton’s pinned page indicator does. Easton describes a pinned page indicator that pins host pages for a duration of an FCP I/O operation, this is analogous to a valid bit that indicates whether one of the processes is executing. The combination of Easton’s pinned page indicator and Mill’s conditional lock teaches the claim limitation in its current form.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nemiroff et al. (U.S. PGPub No. 2007/0143555) teaches lock and unlock sector commands from a currently executing host CPU sent to firmware via a Host Embedded Controller Interface (HECI)
Verduzco et al. (U.S. PGPub No. 2014/0282559) teaches a process profile to include memory addresses corresponding to processes of the application currently executing on the host device
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE WU whose telephone number is (571)272-0257. The examiner can normally be reached 1pm to 6pm, and 10pm to 1am Eastern time (10am to 3pm, and 7pm to 10pm Pacific time).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at (571) 270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEPHANIE WU/Primary Examiner, Art Unit 2133
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