DETAILED ACTION
Claim(s) 1, 6 are 11 is amended. Claims 1-11 are pending.
Priority: 6/12/2023
Assignee: R Bosch
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/4/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Cohen (20180232179) in view of Noeske et al (20050166032), and further in view of Lesartre(20170293573).
As per Claim 1, Cohen discloses a method for operating a memory module (Cohen, [0300 – In Fig. 1A, a SSD controller includes a host interface for interfacing with a host, an interface for interfacing with NVM such as flash memory, and circuitry for controlling the interfaces]), comprising the following steps:
providing, in a first step, a memory module (Cohen, [0305 – In Fig. 1A, SSD Controller 100 is communicatively coupled via one or more Device Interfaces 190 to NVM 199 including one or more storage devices, such as one or more Flash Device 192]), wherein the memory module includes a memory area with a plurality of memory cells having data (Cohen, [0286 - At least one flash memory comprises one or more of NAND flash technology storage cells, and NOR flash technology storage cells]);
and when there is an access (Cohen, [0309 – In Fig. 1A, host Interfaces 111 sends and receives commands and/or data via External Interfaces 110]), including a write access and/or read access, to the data of the memory cells of the memory module (Cohen, [0309 - The commands include a read command specifying an address/LBA and an amount of data to read, and a write command specifying an address/LBA and an amount of data to write]), checking whether the access is permissible (Cohen, [0304 - SSD controller implementing address space to NVM) address, span, and length mapping/converting, using various techniques for encoding location- and length-related information, such as within table entries of an address mapping function, e.g. Map 141 of Fig. 1A]; [0313 - Scheduling 193 is enabled to queue operations to instances of Flash Device 192, and to selectively send the operations to individual ones of Flash Device 192; Since the claim does not recite how access permissibility is determined, the citation is a valid interpretation]),
when the access is permissible, executing the access in a third step (Cohen, [0298 – The SSD controller executes commands of a host protocol sent from a host via a host interface of the SSD. Some of the commands direct the SSD to write and read the NVM with data sent from and to the host, respectively]).
Noeske discloses,
providing in a first step, a memory module (Noeske, [0002 – buffer memory]; [Fig. 2: Buffer 41]),
providing, in a second step, at least one address boundary register (Noeske, [Fig. 1: address generator 40]; [Fig. 1: write address register 11 is included in address generator 40]) with at least one address boundary (Noeske, [0002 - An address generator contains a modulo register in which the length of the buffer memory, that is, the number of its memory locations, is entered. Whenever the offset to the base address/boundary contained in the write register is incremented by the value contained in the modulo register, the offset modulo of the buffer length is taken]) which can be changed in value at least in one direction (Noeske, [0002 - A counter or increment/direction statement that functions to modify, i.e., to increment the register after each output of a write address, so as to advance the register to an address that follows the one just outputted—in an increasing sequence]),
wherein the providing of the at least one address boundary register in the second step includes that the address boundary can be set to a new value and it can be checked (Noeske, [0033 – Fig. 3: comparator 48]; [Fig. 1: modulo computing circuit 16 does a compare operation in Para-0023]) whether the new value has been changed in a permissible direction (Noeske, [0033 – In Fig. 3, occupancy output 32 of each address generator 40,40′,….is connected to an input of a comparator 48,48′….at the input of which a reference value is applied. When the count of the address generator 40 exceeds/direction the reference value, the comparator 48 supplies an inhibiting signal to the data source 47 that prevents this source from sending additional data on the write bus 43]; [0023 - When the content the increment value register 14 is positive, that is, the buffer memory is being written to and read in the direction of increasing addresses, the modulo computing circuit 16 compares the result of the addition with the content of the length register 17. If the result is smaller, it outputs it to the write address register, whose content is overwritten by the new value]);
and when there is an access, including a write access and/or read access (Noeske, [0002 – An address generator is employed to generate write addresses and read addresses for access to a buffer memory]), checking whether the access is permissible (Noeske, [0005 - An occupancy value contained within the occupancy registers is read and, employed to trigger countermeasures against any overflow or underflow, thereby determining if access is permissible]), and, when the access is permissible, executing the access in a third step (Noeske, [0022 – In Fig. 1, the content of increment value register 14 corresponds to the number of memory locations of the buffer memory that can be written to simultaneously during a single write or read access to the buffer memory]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address translator of Noeske into the NVM controller of Cohen, for the benefit of detecting and correcting read/write buffer overflow and underflow (Noeske, 0001).
Cohen in view of Noeske does not explicitly disclose the following, however Lesartre discloses:
wherein data stored in the memory cells includes at least one of sensor calibration data, security keys, or firmware objects, and control of the access is configured to selectively restrict read and/or write access to the data(Lesartre, [0025 -- The scope of the present disclosure is not limited to any particular type of validation key. Thus, the other portion of the NVM 108 is used to store sensitive information such as system firmware, a system boot sequence, or BIOS, as noted above. However, write access is restricted only with respect to the validation key, while unnecessary memory access overhead is avoided by not implementing restricted write access to each address in the portion of the NVM 108 storing such sensitive information.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Lesarte into the system of Cohen in view of Noeske for the benefit of a protected location which is in a write-protected state or not is determined which ensures that the write access to system firmware is efficiently restricted which enhances the system security(Lesartre, 0017).
As per Claim 2, the rejection of claim 1 is incorporated, and Cohen, Noeske disclose,
the at least one address boundary register (Noeske, [Fig. 1: address generator 40]) is a digital flip-flop component (Noeske, [0021 – In Fig. 1, one output of the modulo computing circuit 16 is connected to a data input of the write address register 11, thereby implying that since write address register 11 stores data, it is a storage register type of flip flop]),
and the check of whether the new value of the address boundary has been changed in the permissible direction is implemented based on a logic comparator element (Noeske, [0033 – Fig. 3: comparator 48]; [Fig. 1: modulo computing circuit 16 does a compare operation in Para-0023]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address translator of Noeske into the NVM controller of Cohen, for the benefit of detecting and correcting read/write buffer overflow and underflow (Noeske, 0001).
As per Claim 3, the rejection of claim 1 is incorporated, and Cohen, Noeske disclose,
the address boundary register (Noeske, [Fig. 1: 40]) is implemented in ascending order address boundaries (Noeske, [0002 - A counter or increment statement that functions to modify, i.e., to increment the register after each output of a read address or write address, so as to advance the register to an address that follows the one just outputted—in an increasing sequence]),
and the address boundary is set to a smallest possible value of the memory module at system start (Noeske, [0029 – In Fig. 1, the value in the occupancy register 30 when this register is initialized to zero, upon startup/system start of the buffer memory]),
the at least one address boundary in the ascending implementation of the address boundaries is set in an ascending direction of values when a new value of the address boundary is greater than a previous value of the address boundary (Noeske, [0002 - Advance the register to an address that follows the one just outputted, in an increasing sequence]),
and the access is carried out in the third step when an access address has a value that corresponds at least to the value of the address boundary and/or is above the value of the address boundary (Noeske, [0025 – In Fig. 1, if the modulo computing circuit 16 determines that the result outputted by adder 13 is greater than or equal to length of the buffer entered in the buffer length register 17, the circuit subtracts the content of the register from the result of the adder 13 and passes on the difference thus obtained to the write address register 11]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address translator of Noeske into the NVM controller of Cohen, for the benefit of detecting and correcting read/write buffer overflow and underflow (Noeske, 0001).
Cohen clarifies the smallest possible value w.r.t. the NVM memory module/persistent storage at system start as follows,
the address boundary is set to a smallest possible value of the memory module at system start (Cohen, [0205 - The reading of the data reads data from the NVM beginning at the starting address/smallest value]; [0354 - A writing and/or a striping order of data within an R-block is page, e.g. lowest to highest first, across all devices, then the next highest page across all devices, and so forth, continuing throughout the last page of the R-block]).
As per Claim 5, the rejection of claim 1 is incorporated, and Cohen, Noeske disclose,
- at least one first address boundary register (Noeske, (Noeske, [Fig. 3: 40]; [Fig. 1: write address register 11]) and one second address boundary register (Noeske, (Noeske, [Fig. 3: 40’]; [Fig. 1: read address register 21]) are implemented (Noeske, [Fig. 3: 40,40’]), and are be formed independently of one another (Noeske, [0013 – As per Fig. 1, the buffer memory is connected to a write bus to receive data from one source, and a read bus to output data to a sink, that have mutually independent clock signals]);
- and (i) the first address boundary register (Noeske, [Fig. 3: 40]) is implemented in ascending order of address boundaries (Noeske, [Fig. 1: increment value register 14]; [0002 - A counter or increment statement that functions to modify/increment the register after each output of a write address, so as to advance the register to an address that follows the one just outputted—in an increasing sequence]; [0020 - Increment value register 14 is written to with the values ±1, ±2, ±4, depending on whether the buffer memory is read 1, 2, or 4 bytes at a time in an increasing direction]) and the second address boundary register (Noeske, [Fig. 3: 40’]) is implemented in descending order of the address boundaries (Noeske, [Fig. 1: increment value register 24]; [0002 - A counter that functions to modify the register after each output of a read address, so as to advance the register to an address that follows the one just outputted—in a decreasing sequence]), and/or
- (ii) the first address boundary register is implemented for write accesses and the second address boundary register is implemented for read accesses (Noeske, [Fig. 3: 40,40’]; [0002 – As per Fig. 1, the address generator comprises one or more address registers, the content of which may be outputted as a read address/read access or write address/write access to an address bus of the system, to which bus the buffer memory to be controlled is connected]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address translator of Noeske into the NVM controller of Cohen, for the benefit of detecting and correcting read/write buffer overflow and underflow (Noeske, 0001).
Claim 4 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Cohen (20180232179) in view of Noeske et al (20050166032) and Swenson et al (7546480), and further in view of Lesartre(20170293573).
As per Claim 4, the rejection of claim 1 is incorporated, and Cohen, Noeske disclose,
the address boundary register (Noeske, [Fig. 1: address generator 40]) is implemented in descending order in address boundaries (Noeske, [0002 - Advance the register to an address that follows the one just outputted—in a decreasing sequence]) and the address boundary is set to a largest possible value of the memory module at system start (Noeske, [0010 - The second limit/largest must not be greater than the difference between the size of the buffer/module and the size of a block to be read]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address translator of Noeske into the NVM controller of Cohen, for the benefit of detecting and correcting read/write buffer overflow and underflow (Noeske, 0001).
Swenson further discloses,
the at least one address boundary in the descending implementation is set in a descending direction of the values when a new value of the address boundary is smaller than a previous value of the address boundary (Swenson, [Col. 2, lines 9-10 - In Fig. 2, the sender 202 transmits the block of data to the receiver, and decrements the counter 206 by the size of the block of data, thereby implying that that the address boundary is decremented]),
and the access is carried out in the third step when an access address has a value that corresponds at least to the value of the address boundary and/or is below the value of the address boundary (Swenson, [Col. 2, lines 5-10 - If the block of data is less than or equal to the contents of the counter 206, it is determined that the one or more buffers maintained at the receiver can accommodate the block of data. Hence, the sender 202 transmits the block of data to the receiver, and decrements the counter 206 by the size of the block of data]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the data flow control of Swenson into the NVM controller of Cohen, Noeske for the benefit of systems using high speed busses interconnect sources and destinations of data, and, more specifically, to alignment, re-timing, and buffer underflow/overflow enhancements for such systems (Swenson, Col. 1, lines 13-16).
Claims 6-8, 10 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Cohen (20180232179) in view of Noeske et al (20050166032) and Yamamura et al (20150089180), and further in view of Lesartre(20170293573).
As per Claim 6, Cohen discloses a memory controller (Cohen, [Fig. 1A: SSD controller 100]; [0304 – In Fig. 1A, the SSD controller is for managing non-volatile storage, such as implemented via NVM elements, e.g., flash memories. SSD Controller 100 is communicatively coupled via one or more External Interfaces 110 to a host]), comprising:
a processing unit (Cohen, [0308 - In Fig. 1A, SSD Controller 100 has one or more modules such as CPU 171]) operatively connected via a bus system (Cohen, [0307 – In Fig. 1A, device interfaces 190 are organized as one or more busses with one or more of Flash Device 192 per bus]) to a memory module (Cohen, [Fig. 1A: NVM 199]) which is configured as a non-volatile memory (Cohen, [0305 - SSD Controller 100 is coupled via one or more Device Interfaces 190 to NVM 199 including one or more storage devices, such as one or more of Flash Device 192]),
wherein the memory module (Cohen, [Fig. 1A: NVM 199]) includes a memory area with a plurality of memory cells having data (Cohen, [0286 – The flash memory comprises one or more of NAND flash technology storage cells, and NOR flash technology storage cells]);
an address logic module (Cohen, [Fig. 1A: Device Interface Logic 191]) operatively connected to the processing unit (Cohen, [Fig. 1A: CPU 171]) and the memory module via the bus system (Cohen, [0313 - Device Interface Logic 191 controls instances of Flash Device 192 via Device Interfaces 190. Device Interface Logic 191 is enabled to send data to/from the instances of Flash Device 192. Device Interface Logic 191 includes Scheduling 193 to selectively sequence control of the instances of Flash Device 192 via Device Interfaces 190]),
Noeske clarifies the address logic module as,
wherein the address logic module (Noeske, [Fig. 3]; [Fig. 1: address generator 40 is included in Fig. 3]) is configured to provide at least one address boundary register (Noeske, [Fig. 1: write address register 11 included in address generator 40]) with at least one address boundary (Noeske, [0002 - One counter or increment statement that functions to modify/increment the register after each output of a read address or write address, so as to advance the register to an address that follows the one just outputted—in an increasing sequence]);
wherein the address logic module (Noeske, [Fig. 3]) is configured to set the address boundary to a new value and to check whether the new value has been changed in a permissible direction (Noeske, [0033 – In Fig. 3, occupancy output 32 of each address generator 40,40′,….is connected to an input of a comparator 48,48′….at the input of which a reference value is applied. When the count of the address generator 40 exceeds/direction the reference value, the comparator 48 supplies an inhibiting signal to the data source 47 that prevents this source from sending additional data on the write bus 43]; [0023 - When the content of the increment value register 14 is positive, .i.e., the buffer memory is being written to and read in the direction of increasing addresses, the modulo computing circuit 16 compares the result of the addition with the content of the length register 17. If the result is smaller, it outputs it to the write address register, whose content is overwritten by the new value, thereby setting the address boundary to a new value]);
wherein the address logic module includes at least one further logic comparator element (Noeske, [Fig. 3: comparator 48]; [Fig. 1: modulo computing circuit 16 does a compare operation in Para-0023]),
wherein the at least one further logic comparator element is configured for an access, including write access and/or read access, to data of the memory cells, to check whether the access is permissible (Noeske, [0033 – Fig. 3: comparator 48]), and, when the access is permissible, to execute the access (Noeske, [Fig. 3]; [0022 - Whenever a data value is to be written to the buffer controlled by the address generator, a trigger pulse is applied to the trigger input 15. This trigger pulse causes the adder 13 to add the values outputted by the registers 11, 14, and supply them to the modulo computing circuit 16. The content of the increment value register 14 corresponds to the number of memory locations of the buffer memory that can be written to simultaneously during a single write or read access to the buffer memory]; [0033 – In Fig. 3, data sink 42 connected to the buffer 41 thus obtains time to finish processing the data accumulated in the buffer 41]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address translator of Noeske into the NVM controller of Cohen, for the benefit of detecting and correcting read/write buffer overflow and underflow (Noeske, 0001).
Yamamura discloses the software module as follows,
wherein the processing unit (Yamamura, [Fig. 4: CPU 10]) includes a software module (Yamamura, [Fig. 10: address range check unit 15]) which is configured to change a value of the at least one address boundary (Yamamura, [Fig. 10: start address, end address]) in at least one direction (Yamamura, [0094 - Configure the address range check unit 15]; [0040 – In Fig. 4, an address range check unit 15 that performs the address range check as to whether the access destination address of a memory access instruction, such as load/read and store/write instructions, is within the address range of the memory allocation area that has been allocated by the memory area allocation function]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address range check unit of Yamamura into the NVM system of Cohen, Noeske for the benefit of having the address range check unit provided in parallel with the TLB unit, which performs the address translation, and executes the address range check at a stage same as the pipeline stage of address translation thereby facilitating data storage in the NVM memory (Yamamura, 0040).
Cohen in view of Noeske and Yamamura does not explicitly disclose the following, however Lesartre discloses:
wherein data stored in the memory cells includes at least one of sensor calibration data, security keys, or firmware objects, and control of the access is configured to selectively restrict read and/or write access to the data(Lesartre, [0025 -- The scope of the present disclosure is not limited to any particular type of validation key. Thus, the other portion of the NVM 108 is used to store sensitive information such as system firmware, a system boot sequence, or BIOS, as noted above. However, write access is restricted only with respect to the validation key, while unnecessary memory access overhead is avoided by not implementing restricted write access to each address in the portion of the NVM 108 storing such sensitive information.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Lesarte into the system of Cohen in view of Noeske for the benefit of a protected location which is in a write-protected state or not is determined which ensures that the write access to system firmware is efficiently restricted which enhances the system security(Lesartre, 0017).
As per Claim 7, the rejection of claim 6 is incorporated, and Cohen, Noeske, Yamamura disclose,
the at least one address boundary register is a digital flip-flop component (Noeske, [Fig. 1: address generator 40]; [0021 – In Fig. 1, one output of the modulo computing circuit 16 is connected to a data input of the write address register 11, thereby implying that since write address register 11 stores data, it is a storage register type of flip flop]);
the digital flip-flop component is configured to check whether the new value of the address boundary has been changed in the permissible direction based on the logic comparator element (Noeske, [0023 – In Fig. 1, when the buffer memory is being written to and read in the direction of increasing/permissible direction addresses, the modulo computing circuit 16 compares the result of the addition with the content of the length register 17. If the result is smaller, it outputs it to the write address register, whose content is overwritten by the new value]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address translator of Noeske into the NVM controller of Cohen, Yamamura for the benefit of detecting and correcting read/write buffer overflow and underflow (Noeske, 0001).
As per Claim 8, the rejection of claim 6 is incorporated, and Cohen, Noeske, Yamamura, disclose,
the software module (Yamamura, [Fig. 10: address range check unit 15]) of the processing unit (Yamamura, [Fig. 4: CPU 10]) is configured to set (Yamamura, [0094 - Configure the address range check unit 15]) the at least one address boundary (Yamamura, [Fig. 10: start address, end address]) of the address boundary register in a direction of ascending value (Yamamura, [Fig. 17: lower limit check, upper limit check]; [0055 - Fig. 8 shows the address range table and address range register]; [0066 – In Fig. 10, address range check unit 15 has an address range register 15A, which is Fig. 8: 35, and an adder 151 that generates an end address by adding up the start address [59:0] and the size/range in register 15A, thereby implying an ascending order]);
the software module of the processing unit is configured to transmit the set value to the address logic module (Yamamura, [Fig. 9: effective address generator 12A/address logic module]; [0063 - The primary cache pipeline 50 has an address range register 15A and a range check circuit 15B that are referred to with respect to the virtual address VA generated by the effective address generator 12A]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address range check unit of Yamamura into the NVM system of Cohen, Noeske for the benefit of having the address range check unit provided in parallel with the TLB unit, which performs the address translation, and executes the address range check at a stage same as the pipeline stage of address translation thereby facilitating data storage in the NVM memory (Yamamura, 0040).
Noeske discloses,
the address logic module (Noeske, [Fig. 3]) is configured to set the address boundary to a smallest possible value of the memory module when the system starts (Noeske, [0029 – In Fig. 1, the value in the occupancy register 30 when this register is initialized to zero, upon startup/system start of the buffer memory]) and to check whether a new value of the address boundary is greater than a previous value of the address boundary, and when this is the case, to adopt the set value of the address boundary (Noeske, [0002 - Advance the register to an address that follows the one just outputted—in an increasing sequence]);
the address logic module (Noeske, [Fig. 3]) is configured to grant access to the processing unit when an access address corresponds in value to at least the value of the address boundary and/or is above the value of the address boundary (Noeske, [0025 - If the modulo computing circuit 16 determines that the result outputted by adder 13 is greater than or equal to length of the buffer entered in the buffer length register 17, the circuit subtracts the content of the register from the result of the adder 13 and passes on the difference thus obtained to the write address register 11]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address translator of Noeske into the NVM controller of Cohen, Yamamura for the benefit of detecting and correcting read/write buffer overflow and underflow (Noeske, 0001).
As per Claim 10, the rejection of claim 6 is incorporated, and Cohen, Noeske, Yamamura disclose,
the address logic module includes a switch element (Noeske, [Fig. 2: D/A convertor 42 can operate as a switch]; [Fig. 1: occupancy measurement section 3]);
the switch element is configured to switch from at least one first address boundary register to a second address boundary register (Noeske, [Fig. 3: 40,40’]; [Figs. 2-3: switching functionality]) and/or the switch element is configured to switch from at least one second address boundary register to a first address boundary register (Noeske, [0029 – In Fig. 1, occupancy measurement section 3 comprises an occupancy register 30 and an adder 31 that is connected to both trigger inputs 15, 25, to add the content of increment value register 14 to the occupancy register 30 when a trigger signal is received at input 15, or to subtract the content of increment value register 24 from this value when a trigger signal is received at the trigger input 25]);
the first address boundary register and the second address boundary register (Noeske, [Fig. 3: 40,40’]) are formed independently of one another (Noeske, [0013 - The buffer memory is connected to a write bus to receive data from one source, and a read bus to output data to a sink, that have mutually independent clock signals]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address translator of Noeske into the NVM controller of Cohen, Yamamura for the benefit of detecting and correcting read/write buffer overflow and underflow (Noeske, 0001).
Claim 9 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Cohen (20180232179) in view of Noeske et al (20050166032), Yamamura et al (20150089180) and Swenson et al (7546480), and further in view of Lesartre(20170293573).
As per Claim 9, the rejection of claim 6 is incorporated, and Cohen, Noeske, Yamamura disclose,
the software module of the processing unit is configured to set the at least one address boundary of the address boundary register in a direction of descending value (Yamamura, [Fig. 17: upper limit]; [Fig. 7: ID=1 to 4, which identifies the memory allocation areas MA1 to MA4, respectively, and the start addresses/boundaries VA1 to VA4 of the respective memory allocation areas]; [0040 - The address range check unit 15 is provided in parallel with the TLB unit 14, which performs the address translation:virtual address to physical address, and executes the address range check at a stage same as the pipeline stage of address translation]);
the software module of the processing unit is configured to transmit the set value to the address logic module (Yamamura, [Fig. 9: effective address generator 12A/address logic module]; [0063 - The primary cache pipeline 50 has an address range register 15A and a range check circuit 15B that are referred to with respect to the virtual address VA generated by the effective address generator 12A]);
Noeske further discloses,
the address logic module (Noeske, [Fig. 3]) is configured to set the address boundary to a largest possible value of the memory module when the system starts (Noeske, [0010 - The second limit must not be greater than the difference between the size of the buffer/module and the size of a block to be read]) and to check whether a new set value of the address boundary is smaller than a previous value of the at least one address boundary, and, when this is the case, to adopt the set value of the address boundary (Noeske, [0002 - A counter or increment statement that functions to modify/increment the register after each output of a read address or write address, so as to advance the register to an address that follows the one just outputted—in a decreasing sequence. The address generator also contains a modulo register in which the length of the buffer memory, .i.e. the number of its memory locations, is entered. Whenever the offset to the base address contained in the write register or read register is incremented by the value contained in the modulo register, the offset modulo of the buffer length is taken]);
Swenson further discloses,
the address logic module is configured to grant access to the processing unit when an access address corresponds in value to at least the value of the address boundary and/or is below the value of the address boundary (Swenson, [Col. 2, lines 5-10 - If the block of data is less than or equal to the contents of the counter 206, it is determined that the one or more buffers maintained at the receiver can accommodate the block of data. Hence, the sender 202 transmits the block of data to the receiver, and decrements the counter 206 by the size of the block of data]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the data flow control of Swenson into the NVM controller of Cohen, Noeske for the benefit of systems using high speed busses interconnect sources and destinations of data, and, more specifically, to alignment, re-timing, and buffer underflow/overflow enhancements for such systems (Swenson, Col. 1, lines 13-16).
Claim 11 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Lee (20090293615) in view of Cohen (20180232179), Noeske et al (20050166032) and Yamamura et al (20150089180), and further in view of Lesartre(20170293573).
As per Claim 11, Lee discloses a MEMS component (Lee, [0020 - Fig. 2 shows a sensor management system 10]), comprising:
a MEMS element including an inertial sensor element configured to generate sensor data indicative of motion(Lee, [0007 - A MEMS system includes an inertial sensor having sensor circuitry and management circuitry implemented with the sensor circuitry]; [0004 - In a MEMS accelerometer, the inertial mass is suspended in a plane above a substrate and movable with respect to the substrate]; [See 112(b)]);
an evaluation circuit (Lee, [0021 – As per Figs. 1-2, various parameters are set in sensor 4 by the management module 18, e.g., parameters are set based on whether activity or inactivity is detected, free fall is detected, a tap or double tap is detected by the detection module 14]) including a microprocessor system with a memory controller (Lee, [0019 - Fig. 1: central computer or microprocessor 6]; [0006 - The microprocessor or controller periodically or continuously monitors the acceleration data from the inertial sensor to determine the state of the device]), the inertial sensor element operatively connected to the evaluation circuit and configured to provide the sensor data to the memory controller(Lee, [Figs. 1-2]),
the memory controller (Lee, [Fig. 1: controller]) including:
a processing unit operatively connected via a bus system to a memory module (Lee, [0023 - Management module 18 monitors the amount of data in memory 16/memory module and instructs the device's microprocessor 6 when to read the data once a certain amount has been stored]) which is configured as a non-volatile memory (Lee, [0020 - The sensor management system 10 also includes memory 16 for storing or collecting the data values received from the external devices and the data values processed by the detection module 14]; [0010 - The memory stores the data values received by the inertial sensor in a stream buffer type of configuration; Since NVM can be configured to support stream buffer-like operations for applications requiring high-speed data capture and persistent storage of streaming data, it is valid to interpret memory 16 as NVM]),
Cohen clarifies the architecture as follows,
the memory controller (Cohen, [Fig. 1A, SSD Controller 100]) including:
a processing unit (Cohen, [0308 - In Fig. 1A, SSD Controller 100 has one or more modules such as CPU 171]) operatively connected via a bus system (Cohen, [0307 – In Fig. 1A, device interfaces 190 are organized as: one or more busses with one or more of Flash Device 192 per bus]) to a memory module which is configured as a non-volatile memory (Cohen, [0305 - SSD Controller 100 is coupled via one or more Device Interfaces 190 to NVM 199 including one or more storage devices, such as one or more of Flash Device 192]),
wherein the memory module includes a memory area with a plurality of memory cells having data (Cohen, [0286 – The flash memory comprises one or more of NAND flash technology storage cells, and NOR flash technology storage cells]);
an address logic module (Cohen [Fig. 1A: Device Interface Logic 191]) operatively connected to the processing unit and the memory module (Cohen, [Fig. 1A: NVM 199]) via the bus system (Cohen, [0313 - Device Interface Logic 191 controls instances of Flash Device 192 via Device Interfaces 190. Device Interface Logic 191 is enabled to send data to/from Flash Device 192]; [0307 - Device Interfaces 190 are organized as: one or more busses with one or more of Flash Device 192 per bus]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the NVM controller of Cohen into the MEMS sensor management system of Lee, for the benefit of using flash memory storage technology to provide improvements in performance, efficiency, and utility of use (Cohen, 0006).
Noeske clarifies the address logic module as,
wherein the address logic module (Noeske, [Fig. 3]; [Fig. 1: address generator 40, included in Fig. 3]) is configured to provide at least one address boundary register (Noeske, [Fig. 1: write address register 11 included in address generator 40]; [Noeske, [Fig. 3: 40,40’]) with at least one address boundary (Noeske, [0002 - One counter or increment statement that functions to modify/increment the register after each output of a read address or write address, so as to advance the register to an address that follows the one/lower boundary just outputted—in an increasing sequence]; [0027 - If the write address has reached the end of the buffer, it is returned by the modulo computing circuit 16 to the opposite end/lower boundary of the buffer, and the buffer is once again written to completely from one end to the other]),
wherein the address logic module (Noeske, [Fig. 3]) is configured to set the address boundary to a new value and to check whether the new value has been changed in a permissible direction (Noeske, [0033 – In Fig. 3, occupancy output 32 of each address generator 40,40′,….is connected to an input of a comparator 48,48′….at the input of which a reference value is applied. When the count of the address generator 40 exceeds/direction the reference value, the comparator 48 supplies an inhibiting signal to the data source 47 that prevents this source from sending additional data on the write bus 43]; [0023 - When the content of the increment value register 14 is positive, .i.e., the buffer memory is being written to and read in the direction of increasing addresses, the modulo computing circuit 16 compares the result of the addition with the content of the length register 17. If the result is smaller, it outputs it to the write address register, whose content is overwritten by the new value, thereby setting the address boundary to a new value]),
wherein the address logic module (Noeske, [Fig. 3]) includes at least one further logic comparator element (Noeske, [0033 – Fig. 3: comparator 48]; [Fig. 1: modulo computing circuit 16 does a compare operation in Para-0023]),
wherein the at least one further logic comparator element is configured for an access (Noeske, [0035 – In Fig. 3, comparator 48 may function to generate a control signal that prohibits the data source from using the packet mode when a limit is exceeded]), including write access and/or read access, to data of the memory cells, to check whether the access is permissible, and, when the access is permissible, to execute the access (Noeske, [0022 - Whenever a data value is to be written to the buffer controlled by the address generator, a trigger pulse is applied to the trigger input 15. This trigger pulse causes the adder 13 to add the values outputted by the registers 11, 14, and supply them to the modulo computing circuit 16. The content of the increment value register 14 corresponds to the number of memory locations of the buffer memory that can be written to simultaneously during a single write or read access to the buffer memory]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address translator of Noeske into the MEMS sensor management system of Lee, Cohen, Yamamura for the benefit of detecting and correcting read/write buffer overflow and underflow (Noeske, 0001).
Yamamura discloses,
wherein the processing unit (Yamamura, [Fig. 4: CPU 10]) includes a software module (Yamamura, [Fig. 10: address range check unit 15]) which is configured to change a value of the at least one address boundary (Yamamura, [Fig. 10: start address, end address]) in at least one direction (Yamamura, [0094 - Configure the address range check unit 15]; [0040 – In Fig. 4: an address range check unit 15 that performs the address range check as to whether the access destination address of a memory access instruction, such as load/read and store/write instructions, is within the address range of the memory allocation area that has been allocated by the memory area allocation function]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the address range check unit of Yamamura into the MEMS sensor management system of Lee, Cohen, for the benefit of having the address range check unit provided in parallel with the TLB unit, which performs the address translation, and executes the address range check at a stage same as the pipeline stage of address translation thereby facilitating data storage in the NVM memory (Yamamura, 0040).
Lee, Cohen in view of Noeske and Yamamura does not explicitly disclose the following, however Lesartre discloses:
wherein data stored in the memory cells includes at least one of sensor calibration data, security keys, or firmware objects, and control of the access is configured to selectively restrict read and/or write access to the data(Lesartre, [0025 -- The scope of the present disclosure is not limited to any particular type of validation key. Thus, the other portion of the NVM 108 is used to store sensitive information such as system firmware, a system boot sequence, or BIOS, as noted above. However, write access is restricted only with respect to the validation key, while unnecessary memory access overhead is avoided by not implementing restricted write access to each address in the portion of the NVM 108 storing such sensitive information.]).
Therefore it would have been obvious to a POSITA at the time of filing to incorporate the features of Lesarte into the system of Cohen in view of Noeske for the benefit of a protected location which is in a write-protected state or not is determined which ensures that the write access to system firmware is efficiently restricted which enhances the system security(Lesartre, 0017).
Response to arguments
Applicant’s arguments submitted 2/4/2026 with respect to claim(s) 1-11 have been considered but are moot because the new ground of rejection relies on a different combination of references.
Examiner Notes
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bulusu et al.(20200387325) where the processor writes a globally unique identifier (GUID) to the non-volatile region of the memory module. The GUID indicates a location of boundary between the first and second non-volatile storage partitions, and accesses the first non-volatile storage partition. The processor determines the location of the boundary and accesses the second non-volatile storage partition in response to determining the location of the boundary by executing instructions of the system firmware. The operating system is prevented from accessing the second non-volatile storage partition and the system firmware is prevented from accessing the first non-volatile storage partition(Bulusu, abstract).
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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