DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-12 and 14-21 are pending for examination.
This Office Action is Non-Final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, 10-11, 14-16, 18-19, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ludden et al. (US 20200201778 A1, hereinafter “Ludden”).
Regarding Claim 1, Ludden discloses a computer-implemented method (Fig. 2-5) comprising:
commencing a simulation in a simulation environment, the simulation executing a test case using a model of a processor core for functional verification of the processor core (Fig. 2 and [0039]: Simulation environment 202 reads the simulation model 210 and the test case 206, and executes the test cases against a simulated processor core to perform verification of asynchronous page fault detection), wherein the test case includes (i) a targeted command for performance ([0043]: non-irritator thread code 302 executes load instructions, each instruction spanning at least 2 slices. [0045]-[0046]: storage access == page table access for page table performance (page fault or not), targeted at the same page table entry (PTE). Load instructions (which accesses/fetches a PTE) are interpreted as targeted commands for page table performance), based on a trigger condition that occurs during the simulation ([0055]-[0056]: PTE fetch by a processor slice (i.e., by thread 302) triggers execution of L2 cache behavioral module 360 to randomly turn off valid bit of PTE being fetched. PTE fetch is a condition meant to trigger (i.e., is a trigger condition for) module 360 during the simulation to invalidate the PTE being fetched), for simulating interaction between the processor core and another processor core to change an architected state of the model from an initial state to a changed state ([0002]-[0003]: each processor core accesses shared memory. [0042]: shared memory 322 contains page table. [0046]; [0056]: PTE fetch triggers module 360 to change PTE valid bit from initially ON to OFF. Hence, simulates shared data interaction (by accessing the same PTE) between thread 302 of core 300 (Fig. 3) and module 360 that mimics the shared access by another core, without actually modeling another core, to change PTE from initial ON state to OFF state) and (ii) indications of a state change condition, to trigger the change in the architected state of the model ([0055]-[0056]: PTE fetch is an indication of a state change condition to trigger module 360 to change PTE valid bit), and a state restore condition ([0056]-[0058]: accessing PTE with turned off valid bit triggers page fault interrupt to be recorded, which then triggers page fault handler 370 to restore valid bit of PTE), and wherein the commencing the simulation commences the simulation using the test case with the included targeted command and the indications of the state change condition and the state restore condition ([0067]-[0069]: begins simulation with test code, including non-irritator thread code containing load/PTE fetch instructions (targeted command + state change) – see above. [0062]-[0063]: page fault handler 370 checks if an interrupt occurred because of an async page fault and determines if the interrupt is properly handled. Non-irritator thread code includes the page fault handler code, where completed test case is sent to simulation controller 212 for execution. Thus, the simulation begins and executes test case code, the test code including non-irritator thread code containing PTE load/fetch instructions (as targeted command + state change conditions) and page fault handler 370 code ([0071]-[0072]: determines if async page fault have been detected when module 360 turns off valid bit of PTE and properly handled by restoring the PTE valid bit back to ON));
monitoring progression of the simulation, with the architected state of the model in the initial state, for a trigger condition for simulated interaction ([0055]-[0056]: monitor PTE fetch issuance to trigger random turn off of PTE valid bit, which simulates sharing the valid bit data modification between thread 302 and module 360 (see above). [0046]: PTE valid bit initially ON);
based on recognizing the trigger condition for simulated interaction at a point in the test case, changing the architected state of the model from the initial state to the changed state, wherein the changing directs the progression of the simulation, at the point in the test case, to simulate the interaction between the processor and another executing entity ([0056]: issuance of PTE fetch by processor slice triggers module 360 to change valid bit of PTE from ON to OFF. Changing the valid bit simulates data sharing/access between processor slice ([0043]: of thread 302) and module 360 by accessing the same PTE); and
based on a determination to end the simulated interaction, continuing progression of the simulation from the point in the test case ([0072]: return execution to original instruction only if async fault ([0071]: caused by valid bit flip by module 360, which simulates data sharing between thread 302 – see above) is properly handled. Hence, first determines whether async fault was properly handled (ends simulated interaction of faulty data sharing between module 360 and thread 302) before continuing execution from the original instruction).
Regarding Claim 2, Ludden discloses the method of claim 1, as referenced above, wherein the trigger condition comprises the state change condition ([0055]-[0056]: PTE fetch is a trigger and state change condition – trigger module 360 to change PTE valid bit from ON to OFF), wherein the architected state remains in the changed state for the simulated interaction ([0056]: module 360 turns OFF PTE valid bit, processor slice ([0043]-[0046]: of non-irritator thread 302) receives PTE, and records a page fault interrupt. Hence, faults because the PTE valid bit remained OFF when the processor slice receives the PTE), and wherein the method further comprises:
monitoring the progression of the simulation for the state restore condition ([0058]: whenever a page fault is observed (via page fault interrupt), it is handled by page fault handler 370 to restore the valid bit of the PTE. [0071]: detection of async page fault when module 360 randomly turns off valid bit of the PTE requested by a processor slice. Monitors turned off valid bit + recorded page fault interrupt as the handling condition, where the handler restores the valid bit); and
based on recognizing the state restore condition, restoring the architected state to the initial state ([0058]: when page fault interrupt is generated, page fault handler 370 is invoked to restore the valid bit. [0072]: turns PTE valid bit back ON).
Regarding Claim 3, Ludden discloses the method of claim 2, as referenced above, wherein the changed state emulates a page fault exception ([0056]: module 360 turns PTE valid bit OFF, causing a page fault interrupt by the processor slice), wherein changing the architected state to the changed state comprises altering at least one bit value of the model, the altering invalidating a page table entry and driving the page fault exception based on execution of an instruction of the test case ([0056]: turns valid bit OFF, causing processor slice receiving the PTE to record a page fault interrupt based on execution of a PTE fetch (also see [0071]: “async page fault generated during execution of test code when module 360 randomly turns off valid bit when it returns to the core a PTE requested by the processor core slice… observed by only one processor slice executing an instruction of non-irritator thread code, and remaining slices executing the same instruction do not observe that page fault”).
Regarding Claim 4, Ludden discloses the method of claim 3, as referenced above, wherein the restoring the architected state to the initial state comprises restoring the at least one bit value, the restoring the at least one bit value restoring the page table entry ([0058]; [0072]: turn valid bit of PTE back ON), and wherein the determination to end the simulated interaction comprises a determination that the page table entry is restored ([0072]: determine if async page fault ([0071]; [0043]-[0046]: part of simulated interaction as interaction between processor slice of thread 302 + module 360 caused the async page fault) was properly handled and recorded…. Async fault properly handled (and thus ends the async fault) if properly returns execution to original instruction and/or turns valid bit of PTE back on).
Regarding Claim 5, Ludden discloses the method of claim 4, as referenced above, wherein the method further comprises:
identifying the point in the test case, the point being a point at which to emulate a page invalidation ([0056]: issuance of PTE fetch), wherein the targeted command changes the architected state to emulate the page invalidation by altering the at least one bit value ([0056]: PTE fetch causes module 360 to change PTE valid bit to OFF, i.e., invalidate the PTE).
Regarding Claim 7, Ludden discloses the method of claim 2, as referenced above, wherein the changed architecture state emulates a changed instruction stream of the test case ([0056]-[0058]: turning off the valid bit of the PTE generates a page fault interrupt and invokes a page fault handler module 370. [0059]: Interrupts (e.g., page faults) switches context to an interrupt handler, which contains instructions for dealing with the particular condition that caused the interrupt), wherein changing the architected state to the changed state comprises replacing an instruction of the test case, at the point in the test case, with a changed instruction that directs the progression of the simulation to a subroutine ([0059]: As a result of the interrupt, the processor transfers control to a special routine known as an interrupt handler. Examiner interprets “replacing an instruction of the test case” as replacing the original instruction order of the test case to now include instructions in the interrupt handler).
Regarding Claim 10, Ludden discloses the method of claim 1, as referenced above, wherein the changed state emulates sharing of data by the other processor core, wherein changing the architected state to the changed state comprises storing a value to the model ([0056]; [0082]: store 0 in PTE valid bit to invalidate PTE), wherein the storing emulates an indication that the data has been shared by the other processor core and directs the progression of the simulation to proceed as if the data were shared by the other processor core ([0056]: changed valid bit state emulates sharing of data/common access to data by module 360 (see [0042]; [0003]; and above: serves as another processor core for accessing shared page table memory), wherein module 360 changes/stores the PTE valid bit to OFF such that the processor slice receiving the PTE records a page fault interrupt ([0071]: observes page fault / invalid PTE; invalid PTE due to data modification by module 360 in shared page table)).
Regarding Claim 11, Ludden discloses the method of claim 10, as referenced above, wherein the determination to end the simulated interaction comprises a determination that the value has been restored ([0060]: Execution of the AVP ([0038] which stores the test) is only returned after the page fault handler 370 turns the valid bit back ON in the PTE. In other words, ending the page fault and returning back to the test case depends on whether the valid bit was turned back ON/restored to its initial value).
Regarding Claim 14, Ludden discloses the method of claim 1, as referenced above wherein the simulated interaction is one simulated interaction of a plurality of simulated interactions ([0067]: a test case in a simulated environment is executed to detect asynchronous page faults (pl.) during storage access in the simulated processor), wherein the method further comprises generating the test case (Fig. 1 and [0029]: test case generator 123 for generating test cases), the generating comprising including in the test case a plurality of targeted commands in a selected order to change the architected state and drive the plurality of simulated interactions in the selected order ([0046]: Load instructions may be configured to use the same PTE. Examiner interprets “in a selected order to change the architected state and drive the plurality of simulated interactions in the selected order” as invalidating PTEs and reporting a page fault (see [0056]) in the order in which the load instructions appear), the selected order resulting in serial performance of the plurality of simulated interactions as part of the simulation ([0046] and [0056]: execution of the load instructions may simulate page faults).
Regarding Claim 15, the method of Claim 1 performs the same steps as the system of Claim 15, and Claim 15 is rejected using the same art and rationale set forth above in the rejection of Claim 1 by the teachings of Ludden.
Ludden further discloses a computer system (Fig. 1: computer system 100) comprising:
at least one computing device (Fig. 1: processor 110);
a set of one or more computer readable storage media (Fig. 1: main memory 120); and
program instructions, collectively stored in the set of one or more computer readable storage media, for causing the at least one computing device to perform computer operations ([0032]: Main memory 120 stores programs and data that processor 110 may access, including program instructions that make up OS 121 and test case generator 123).
Regarding Claim 16, Ludden teaches the system of Claim 15 above. The method of Claim 2 performs the same steps as the system of Claim 16, and Claim 16 is rejected using the same art and rationale set forth above in the rejection of Claim 2 by the teachings of Ludden.
Regarding Claim 18, the method of Claim 1 performs the same steps as the product of Claim 18, and Claim 18 is rejected using the same art and rationale set forth above in the rejection of Claim 1 by the teachings of Ludden.
Ludden further discloses a computer program product (Fig. 1) comprising:
a set of one or more computer readable storage media (Fig. 1: main memory 120); and
program instructions, collectively stored in the set of one or more computer readable storage media, for causing at least one computing device to perform computer operations ([0032]: Main memory 120 stores programs and data that processor 110 may access, including program instructions that make up OS 121 and test case generator 123).
Regarding Claim 19, Ludden teaches the product of Claim 18 above. The method of Claim 2 performs the same steps as the product of Claim 19, and Claim 19 is rejected using the same art and rationale set forth above in the rejection of Claim 2 by the teachings of Ludden.
Regarding Claim 21, Ludden discloses the method of claim 1, as referenced above, wherein the another processor core is not modeled as part of the simulation ([0003]: background recites a shared memory environment where data can be changed by each processor core. Fig. 3; [0042]: simulation environment 202 includes shared memory 322 with a page table which threads 302-306 of simulated core 300 have access to ([0043][0046]: thread 302 actually accesses it to use a PTE in said page table via PTE load). [0055]-[0056]: L2 cache behavioral module 360 is a software module called by core 300 that randomly turns off the valid bit of the PTE being accessed by the PTE fetch request. Thus, software module 360 simulates another core to mimic shared PTE access without actually modeling the full core).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ludden in view of UCSD (NPL: “Project 3: Demand Paging”).
Regarding Claim 6, Ludden discloses the method of claim 5, as referenced above, further comprising including in the test case a program interrupt handler to return execution of the instruction of the test case, based on the page table entry being invalidated ([0056]-[0058]: test case includes page fault handler 370 that, in response to turning off a valid bit of a PTE, restores the valid bit and returns execution of the test back to the instruction which observed the page fault).
Ludden does not disclose:
…a program interrupt handler to iteratively retry execution of the instruction of the test case…
However, UCSD teaches:
…a program interrupt handler to iteratively retry execution of the instruction of the test case… (Page 4, para. 2: “Once you have paged in the faulted page, mark the TranslationEntry as valid. Then let the machine restart execution of the user program at the faulting instruction: return from the exception, but do not increment the PC… so that the machine will re-execute the faulting instruction.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Ludden and UCSD by implementing the PC (program counter) taught by UCSD. One of ordinary skill in the art would be motivated to make this modification as a simple substitution of one known element (Ludden: [0056]-[0058]: page fault handler returns execution to fault instruction) for another (UCSD: Page 4 page fault handler returns execution to fault instruction and re-executes fault instruction) to obtain predictable results (page fault handler returns execution to fault instruction).
Regarding Claim 17, Ludden teaches the system of Claim 16 above. The method of Claim 6 performs the same steps as the system of Claim 17, and Claim 17 is rejected using the same art and rationale set forth above in the rejection of Claim 6 by the teachings of Ludden in view of UCSD (Examiner’s Note: Claim 17 recites the same steps as the combination of Claims 1-6. The dependency of Claim 6 includes all limitations recited in Claims 1-5 in addition to the limitation recited in Claim 6).
Regarding Claim 20, Ludden teaches the product of Claim 19 above. The method of Claim 6 performs the same steps as the product of Claim 20, and Claim 20 is rejected using the same art and rationale set forth above in the rejection of Claim 6 by the teachings of Ludden in view of UCSD (Examiner’s Note: Claim 20 recites the same steps as the combination of Claims 1-6. The dependency of Claim 6 includes all limitations recited in Claims 1-5 in addition to the limitation recited in Claim 6).
Claim 8-9 is rejected under 35 U.S.C. 103 as being unpatentable over Ludden in view of Tanenbaum et al. (NPL: "Modern Operating Systems”).
Regarding Claim 8, Ludden discloses the method of claim 7, as referenced above, wherein the restoring the architected state to the initial state comprises restoring the instruction of the test case ([0058]: Along with restoring the valid bit, the page fault handler returns/restores execution of the test back to the instruction), and
Ludden does not disclose:
wherein the determination to end the simulated interaction comprises a determination that the instruction of the test case is restored.
However, Tanenbaum teaches:
wherein the determination to end the simulated interaction comprises a determination that the instruction of the test case is restored (Pages 234-235, Section 3.6.2 Page Fault Handling: in step 8, execution from the OS page fault handler ends and returns back to the routine that called it only when the program counter is reset to point to the faulting instruction)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Ludden and Tanenbaum by resetting the program counter at the end of the page fault handler in the simulation. One of ordinary skill in the art would be motivated to make this modification in order to return to user space and continue execution, as if no fault had occurred (Tanenbaum: Page 235, step 10).
Regarding Claim 9, Ludden in view of Tanenbaum teaches the method of claim 8, as referenced above, wherein the method further comprises:
identifying the point in the test case, the point being a point at which to emulate a modification to the instruction stream of the test case, wherein the targeted command changes the architected state to emulate the modification to the instruction stream to call the subroutine (Ludden: [0055]: module 360 receives test code, executes it to receive info regarding storage access sequences (identifies the info), and operates to randomly turn off the valid bit of PTEs being fetched. [0056]: issuance of PTE fetch causes module 360 to change PTE valid bit, causing handler 370 to be invoked when the processor slice receives the PTE and records a page fault. Thus, module 360 identifies PTE fetches (targeted commands) in the test code to change the PTE valid bit to OFF, causing the instruction stream to change to from the test case to handler 370 restoration subroutine).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ludden in view of Bair et al. (NPL: "Functional verification of the z990 superscalar, multibook microprocessor complex", hereinafter “Bair”).
Regarding Claim 12, Ludden discloses the method of claim 1, as referenced above.
Ludden does not disclose:
wherein the changing the architected state performs the change under a quiesce sequence issued by the simulation environment based on inclusion of a targeted command in the test case.
However, Bair discloses:
wherein the changing the architected state performs the change under a quiesce sequence issued by the simulation environment based on inclusion of a targeted command in the test case (Page 358, Processor element verification - Quiesce: a change to a translation table entry by an “invalidate page table entry” instruction/command is performed while the processor is quiesced. Page 351, right column, para. 2: processor is quiesced during testing, hence quiescing is included in test cases).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine Ludden and Bair by including the quiesce sequence in the test case executed by the simulation environment taught by Ludden. One of ordinary skill in the art would be motivated to make this modification in order to allow the processor to complete the operation and ensure that the architecture was adhered to while optimizing overall system performance (Bair: Page 358, Quiesce).
Response to Arguments
Applicant’s arguments with respect to claims 1-12 and 14-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Upon further consideration and in light of the amended limitations, Claims 1-5, 7, 10-11, 14-16, 18-19, and 21 are rejected under 35 USC 102 over Ludden. As cited above, Ludden discloses a test case including a state change (non-irritator thread code contains PTE fetch) and restore condition (recorded page fault as a result of bit flip by module 360, included in page fault handler code of non-irritator thread code of test case code), wherein the simulation begins the test case with the non-irritator thread code ([0068]), as referenced above.
Additionally, previously allowable subject matter Claims 5-6, 17, and 20 are rejected in light of an updated prior art search (see above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CATHERINE MARIE NGUYEN whose telephone number is (571)272-6160. The examiner can normally be reached M-F 7:30 AM - 4:30 PM ET.
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/C.M.N./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114