Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to the amendments filed on September 23, 2024.
Priority
Priority is granted to Korean patent application number 10-2024-0025909 filed February 22, 2024.
Drawings
The amendments to the drawings submitted on September 23, 2025 have been considered and accepted.
Specification
The amendments to the specification submitted on September 23, 2025 have been considered and accepted.
Allowable Subject Matter
Independent claims 1, 10, and 15 contain allowable subject matter, as indicated in the previous Office action.
The following is an examiner’s statement of reasons for allowance:
The prior art does not teach or suggest the claimed circuit layout and operation. A summary of the prior art and how it differs from the claimed invention can be found below.
Cha et al. (US 2013/0315007) discloses memory comprising a first and second bank where a compression unit is connected to each bank. The compression units compare and compress data read from the banks in the first test mode and in the second test mode, the compressed data is output from both compression units to the output unit where the compressed data is combined under the direction of control signals and outputted based on the control signals. See figures 2, 3-4, 6 and paragraphs 23-42 and 50-54. However, Cha does not disclose at least two planes including a plurality of memory bank groups; at least one merge circuit configured to receive a plurality of compressed data corresponding to a plurality of memory banks included in one memory bank group, among the plurality of memory bank groups; wherein each memory bank, among the at least two memory banks coupled to a corresponding compressing circuit, is included in different memory bank groups, among the plurality of memory bank groups.
Seyyedy et al. (US 2006/0090108) discloses reading test data and comparing the test data. The read data is compressed creating two compressed data signals equal to the read data. Then the compressed data signals are output together as a single output. Latches are used to in compressing the read data and outputting it. See figures 2-3, 5 and paragraphs 25-29, 31-21. However, Seyyedy does not disclose the claimed layout including memory planes and memory bank groups, and the operations corresponding to those components.
Kim (US 2014/0133235) discloses a memory bank comprising a plurality of planes, where two planes share a row decoder. See figure 4 and paragraph 42. However, Kim’s memory bank includes multiple planes, whereas in the claims, the at least two planes each include a plurality of memory banks. Furthermore, Kim does not disclose the claimed compressing and merging circuitry, their operations, and the memory bank groups.
Kondo (US 2021/0117335) discloses a memory chip that includes a plurality of planes, where each includes a memory cell array and peripheral circuits, paragraph 139. However, Kondo does not disclose circuitry connecting the planes. Nor does Kondo disclose the claimed compressing and merging circuitry, their operations, and the memory bank groups.
Yang (US 2013/0201769) discloses a memory cell area that includes one or more planes where each plane has one or more banks. However, Yang does not disclose circuitry connecting the planes. Nor does Yang disclose the claimed compressing and merging circuitry, their operations, and the memory bank groups.
Foreign patent document KR 20110002678 A discloses memory bank groups with compression circuitry, for example including two memory banks connected to a compression circuit in Fig. 3. However, it does not disclose memory planes and the circuit layout elements that relate to the memory planes. It also does not disclose connecting two memory banks from different memory bank groups to the same compression circuit.
With regards to independent claims 1 and 10, the prior art does not teach or suggest, “at least two planes including a plurality of memory bank groups, wherein each of the plurality of memory bank groups includes a plurality of memory banks... at least one merge circuit configured to receive a plurality of compressed data… from at least two compressing circuits, among the plurality of compressing circuits, and configured to merge the plurality of compressed data to output merged data corresponding to the one memory bank group; and an output buffer circuit configured to receive a plurality of merged data corresponding to the plurality of memory bank groups from the at least one merge circuit” (the plurality of memory bank groups are distributed across the at least two planes, meaning the claim includes a merge circuit merging compressed data from memory bank groups located in multiple planes and an output buffer to receive such data. However, the prior art does not teach the circuit layout of memory bank groups, compression, merging, and output circuitry operating with a combination of planes in this way) and “wherein each memory bank, among the at least two memory banks coupled to a corresponding compressing circuit, is included in different memory bank groups, among the plurality of memory bank groups” in the context of each respective claim.
With regards to independent claim 15, the prior art does not teach or suggest, “a plurality of planes including a plurality of banks; a first compressing circuit coupled to a first memory bank and a second memory bank … a second compressing circuit coupled to a third memory bank and a fourth memory bank, among the plurality of memory banks … a first merge circuit configured to generate first merged data by merging the first compressed data and third compressed data; a second merge circuit configured to generate second merged data by merging the second compressed data and fourth compressed data; and an output buffer circuit configured to output the first merged data and the second merged data to an external device, among the plurality of memory banks” in the context of the claim. Although claim 15 does not positively recite memory bank groups as in claims 1 and 10, the recitation of the first through fourth memory banks and the way they are coupled to the other circuitry effectively amounts to grouping memory banks, and is likewise not taught by the prior art.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A terminal disclaimer may be effective to overcome a provisional nonstatutory double patenting rejection over a pending application (37 CFR 1.321(b) and (c)). A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional, the reply must be complete. MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/PatentForms. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/TerminalDisclaimer.
Please note that MPEP § 804 states: “A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Replies with an omission should be treated as provided in MPEP § 714.03.”
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claims 1-19 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, 5, and 6 of copending Application No. 20250077425 A1, hereinafter also known as ‘425, in view of claim 1 of copending application No. 20250054526 A1, hereinafter also known as ‘526.
Although the claims are not identical, they are not patentably distinct from each other. A comparison of claims is shown below.
Claim No.
US 18/765,774
Claim No.
US 20250077425 A1 or US 20250054526 A1
Examiner Comments
1
A memory device, comprising:
‘425 1
A memory device comprising:
at least two planes
‘425 1
a plurality of memory planes
including a plurality of memory bank groups,
‘425 1
a plurality of memory planes, each including a plurality of memory banks; each including a plurality of memory banks … the merge group comprises at least some memory banks included in a same plane group
The plane groups and merge groups of '425 teach this claim limitation since those are groupings of memory banks that are located on a plurality (at least two) memory planes.
wherein each of the plurality of memory bank groups includes a plurality of memory banks;
‘425 1
a plurality of memory planes, each including a plurality of memory banks; each including a plurality of memory banks … the merge group comprises at least some memory banks included in a same plane group
The plane groups and merge groups of '425 teach this claim limitation since those are groupings of (a plurality of) memory banks that are located on a plurality (at least two) memory planes.
a plurality of compressing circuits,
‘425 1
a plurality of compressing circuits
each coupled to at least two memory banks, among the plurality of memory banks,
‘425 1
each compressing circuit is connected to a corresponding memory bank of the plurality of memory banks
coupling the compressing circuits to at least two memory banks instead of one is obvious because it would allow for additional storage capacity (increasing the number of banks would increase the storage capacity).
the at least two memory banks being included in the same plane, among the at least two planes,
‘526 1
a plurality of memory planes each including a plurality of memory banks …
a plurality of compressing circuits respectively connected to the plurality of memory banks, the plurality of compressing circuits configured to output compressed data by respectively compressing data read from the plurality of memory banks in a compression read operation
The plurality of memory banks would refer to an arbitrary one plurality of the pluralities of memory banks found on the memory planes, i.e. the plurality of memory banks are coplanar.
A plurality of compressing circuits connected to the plurality of memory banks would include the possibility of a plurality of compressing circuits coupled to at least two memory banks (and as explained above, the memory banks would be coplanar as required by the claim limitation).
It would have been obvious to a person of ordinary skill in the art before the effectively filed date of the claimed invention to incorporate the concept of the at least two memory banks being included in the same plane of ‘526 because it would simplify the wiring of the device by only having to connect each compressing circuit to a single plane.
wherein each of the plurality of compressing circuits is configured to compress a plurality of data read from the at least two memory banks
‘526 1
The same rationale provided for the previous claim limitation also applies to this claim limitation.
to output compressed data respectively corresponding to the at least two memory banks;
‘526 1
The same rationale provided for the previous two claim limitations also applies to this claim limitation.
at least one merge circuit configured to
‘425 1
a plurality of merge circuits
A plurality is at least one
receive a plurality of compressed data corresponding to a plurality of memory banks included in one memory bank group, among the plurality of memory bank groups,
‘425 1
each merge circuit receiving compressed data … corresponding to a merge group of a plurality of merge groups, each merge circuit outputting, … merged data obtained by merging compressed data corresponding to memory banks grouped in the merge group
As explained above, a merge group is a grouping of memory banks.
from at least two compressing circuits, among the plurality of compressing circuits, [receive the compressed data from]
‘425 1
a plurality of compressing circuits, wherein each compressing circuit is connected to a corresponding memory bank; each merge circuit outputting … merged data obtained by merging compressed data corresponding to memory banks grouped in the merge group
since each compressing circuit is only connected to a single memory bank in ‘425, for each merge circuit to merge and output compressed data corresponding to a plurality of memory banks, there must be multiple compressing circuits, each compressing circuit connecting a memory bank to the merge circuit
and configured to merge the plurality of compressed data to output merged data corresponding to the one memory bank group;
‘425 1
The same rationale provided for the previous claim limitation also applies to this claim limitation.
and an output buffer circuit configured to
‘425 1
an output buffer circuit
receive a plurality of merged data corresponding to the plurality of memory bank groups from the at least one merge circuit
‘425 1
"a plurality of merge circuits … outputting … merged data obtained by merging compressed data corresponding to memory banks grouped in the merge group" also "a plurality of merge groups"
the output data would be getting output to/received by the output buffer circuit. The memory banks are grouped in a merge group. The plurality of merge circuits each outputting merged for their merge group of memory banks would amount to the claimed limitation (the plurality of merged data corresponding to the plurality of memory bank groups from the at least one merge circuit being output to the output buffer)
and configured to output the plurality of merged data to an external device,
‘425 1
an output buffer ... outputting the merged data
data is plural; a person having ordinary skill in the art would understand that a memory device outputting data would be outputting the data such that it could/would be received by an external device
wherein each memory bank, among the at least two memory banks coupled to a corresponding compressing circuit, is included in different memory bank groups, among the plurality of memory bank groups.
‘425 1
The entirety of ‘425 claim 1
The memory bank groups are merely a logical grouping and since '425 A1 claim 1 has nearly the same structure as described by claim 1 of the instant application, a person having ordinary skill in the art could draw the memory bank groups' boundaries onto the existing structure provided by '425 A1 to achieve this claim limitation. It would advantage the memory device to do so because it would provide parallelization to the memory bank groups (for example, it would connect multiple compressing circuits to the same memory bank group, allowing multiple memory banks in the same group to have their data read and compressed simultaneously).
2
The memory device of claim 1, wherein the plurality of compressing circuits are configured to simultaneously compress the plurality of data read from the at least two memory banks
N/A
Applicant admitted prior art under paragraph 5 of the specification of the instant application "However, in a predetermined operation mode, such asa compression read operation, data that is read from each of theplurality of memory areas included in one or a plurality of memorydevices may be compressed and output, and the plurality ofmemory areas included in the one memory device or the pluralityof memory devices may use a predetermined number of data linesby grouping the data lines in predetermined numbers. Therefore,the plurality of memory areas may be used at the same time. "
3
The memory device of claim 1, wherein the plurality of compressing circuits are configured to merge the plurality of data read from the at least two memory banks and compress the plurality of merged data.
‘425 1
The entirety of ‘425 claim 1
It would have been obvious to merge the data and then compress it because that would enhance efficiency by allowing both data streams to be compressed at once (because they would be merged together into a single stream prior to compression)
4
The memory device of claim 1, wherein the at least one merge circuit includes a plurality of merge circuits, and wherein the plurality of compressing circuits are configured to transfer the compressed data respectively corresponding to the at least two memory banks to different merge circuits, among the plurality of merge circuits.
'526 1
a plurality of first merge circuits configured to receive the compressed data and output control signals corresponding to at least a portion of the memory banks
The quoted claim limitation of ‘526 in its broadest reasonable interpretation would include the circuit layout of receiving compressed data corresponding to one of the two memory banks would from the compressing units. For example, each of the plurality of first merge circuits would be receiving the data corresponding to a portion of the memory banks, which would include one of the at least two memory banks of the instant claim. When two of the plurality of first merge circuits each receive data from a portion of the memory banks including one of the at least two memory banks, then the claimed limitation is achieved.
5
The memory device of claim 1, wherein the at least two memory banks are not physically adjacent to each other.
‘425 1
wherein the merge group comprises at least some memory banks included in a same plane group
This limitation of ‘425 teaches grouping memory banks that are on different planes, where the banks would not be physically adjacent. Therefore grouping at least two banks on the same plane that are not physically adjacent would also have been obvious.
6
The memory device of claim 1, wherein the at least two memory banks have the same column address sequence.
N/A
This would be obvious over ‘425 and ‘526 as it would improve memory locality optimization. Since the data from the at least two memory banks gets merged and compressed together, it would be logical to have them share memory addresses or otherwise have similar memory addresses since their operations are shared. For example, a computer program reading data from a sequence of memory addresses would only be activating a single compressing circuit rather than multiple (if the address sequence was not shared, the data would likely end split up amongst distant banks) improving efficiency.
7
The memory device of claim 1, wherein the at least two planes share a peripheral circuit driving a memory cell array included in the at least two planes to perform an operation of the memory device.
‘425 1
a plurality of memory planes, each including a plurality of memory banks; one or more plane groups, each plane group comprising at least two memory planes sharing at least one peripheral circuit; a plurality of compressing circuits, wherein each compressing circuit is connected to a corresponding memory bank of the plurality of memory banks and outputs compressed data by compressing data read from the corresponding memory bank of the plurality of memory banks in a compression read operation;
8
The memory device of claim 1, wherein each of the plurality of memory bank groups includes physically adjacent memory banks.
‘425 3
wherein the merge group is configured with memory banks physically adjacent to each other.
The merge group is a grouping of memory banks and this claim limitation from '425 teaches the concept of grouping the memory banks based on adjacency
9
The memory device of claim 1, wherein each of the plurality of memory bank groups includes four or more memory banks.
‘425 5
in the merge group, four or more memory banks are grouped.
This teaches creating groups of four or more memory banks
10
A method of operating a memory device including a plurality of planes, each including a plurality of memory banks, the method comprising: grouping the plurality of memory banks into a plurality of memory bank groups; reading a plurality of data from a plurality of memory banks included in the plurality of memory bank groups; compressing the plurality of data, wherein a plurality of data read from at least two memory banks, among the plurality of memory banks, included in one of the plurality of planes are simultaneously compressed; merging a plurality of compressed data corresponding to a plurality of memory banks included in one memory bank group, among the plurality of memory bank groups; and outputting a plurality of merged data corresponding to the plurality of memory bank groups to an external device, wherein each memory bank, among the at least two memory banks, is included in different memory bank groups, among the plurality of memory bank groups.
The claim is rejected under the same rationale as claims 1 and 2 above.
11
The method of claim 10, wherein the grouping of the plurality of memory banks comprises grouping a plurality of memory banks included in at least two planes, among the plurality of planes, into one memory bank group.
The claim is rejected under the same rationale as claim 1 above
12
The method of claim 10, wherein the compressing of the plurality of data comprises: merging the plurality of data read from the at least two memory banks; and compressing the plurality of merged data.
The claim is rejected under the same rationale as claim 3 above
13
The method of claim 10, further comprising, after the compressing of the plurality of data, transferring compressed data corresponding to the at least two memory banks to different merge circuits.
The claim is rejected under the same rationale as claim 4 above
14
The method of claim 10, wherein the outputting of the plurality of merged data comprises sequentially outputting the plurality of merged data according to a predetermined order.
‘425 6
wherein each of the merge circuits includes:
one or more multiplexing circuits receiving normal data and compressing data from the memory banks, the one or more multiplexing circuits selecting data to be output, based on whether the compression read operation is enabled; and
a latch circuit latching data output from at least some of the multiplexing circuits, the latch circuit outputting the latched data, based on the output control signal.
A multiplexer is a device that controls the sequencing of electrical signals, so given that the merge circuits of ‘425 contain multiplexing circuitry, a person having ordinary skill in the art would recognize that the merge circuits are capable of sequentially outputting the plurality of merged data according to a predetermined order. The predetermined order would be the actual circuit layout and/or algorithms implemented in the multiplexing circuitry by the hardware designer.
15
A memory device, comprising: a plurality of planes including a plurality of banks; a first compressing circuit coupled to a first memory bank and a second memory bank, among the plurality of memory banks, wherein the first compressing circuit is configured to compress first data read from the first memory bank and second data read from the second memory bank to output first compressed data and second compressed data corresponding to the first memory bank and the second memory bank, respectively; a second compressing circuit coupled to a third memory bank and a fourth memory bank, among the plurality of memory banks, wherein the second compressing circuit is configured to compress third data read from the third memory bank and fourth data read from the fourth memory bank to output third compressed data and fourth compressed data corresponding to the third memory bank and the fourth memory bank, respectively; a first merge circuit configured to generate first merged data by merging the first compressed data and third compressed data; a second merge circuit configured to generate second merged data by merging the second compressed data and fourth compressed data;
‘425 and ‘526 teach pluralities of the claimed circuit components (as explained in the rejections to claims 1-14 above), which would include the first through fourth versions of circuit components recited in claim 15
and an output buffer circuit configured to output the first merged data and the second merged data to an external device according to a predetermined number.
This claim limitation is applicant admitted prior art. See specification paragraphs 3-5
16
The memory device of claim 15, wherein the compressing circuit is configured to simultaneously compress the first data and the second data.
The claim is rejected under the same rationale as claim 2 above
17
The memory device of claim 15, wherein the compressing circuit is configured to compress the first data and the second data by merging the first and second data.
The claim is rejected under the same rationale as claim 3 above
18
The memory device of claim 15, wherein the first memory bank and the second memory bank are not physically adjacent to each other.
The claim is rejected under the same rationale as claim 5 above
19
The memory device of claim 15, wherein the first memory bank and the second memory bank have the same column address sequence.
The claim is rejected under the same rationale as claim 6 above
Response to Arguments
The examiner thanks the applicant for their remarks of September 23, 2025. The remarks have been accepted and fully considered. However, the arguments are not persuasive.
On page 16 of their remarks, applicant recites:
“The Office Action asserts that, in order to increase memory capacity, it would have been obvious to increase the number of memory banks and connect multiple memory banks to a single compressing circuit. Applicant respectfully disagrees. The presently claimed invention specifically identifies in the background section that as the number of memory areas increases, the size of the output data also increases, leading to an increase in the number of compressing circuits and undesirably increasing the overall size of the device.
This problem exists in devices such as those of the '425 and '526 patents, where compressing circuits are in a one-to-one correspondence with memory banks. The patent application '425 addresses merge failure by setting merge groups, while the patent application '526 addresses unstable clock alignment with a two-step merge method. Neither reference considers the problem of device size increase due to scaling the number of compressing circuits.”
The background section of the instant application also specifically identifies a method of time division to access memory areas. Time multiplexing is a well-known technique among persons having ordinary skill in the art, and among other possible techniques, could be used to increase the number of memory areas without “undesirably increasing the overall size of the device”. The examiner also notes that regardless of any potential disadvantages, it still would have been obvious to add new memory areas, as described in the nonstatutory double patenting rejection above, for the advantage of increasing the total amount of memory available. A given course of action often has simultaneous advantages and disadvantages.
“By contrast, the presently claimed invention solves this problem by allowing one compressing circuit to be coupled to multiple memory banks, each belonging to different bank groups. This configuration results in a different data receiving and operating structure compared to the prior art and effectively suppresses the increase in the number of compressing circuits and the corresponding device size. This cannot be achieved by simply re-drawing logical boundaries on the bank structure of the prior art.”
The Office action’s nonstatutory double patenting rejection does not solely rely open simply re-drawing logical boundaries on the bank structure of the prior art. It would have been obvious to a person having ordinary skill in the art motivated to increase the memory capacity of the device to introduce not just a re-drawing of logical boundaries, but also minor changes in the connections between device components alongside the addition of new memory areas. See the double patenting analysis for claim 1 above.
Accordingly, the Office Action's characterization overlooks the substantial structural and functional distinctions recited in claim 1. The claimed configuration is not taught or suggested by the patent application '425 or the patent application '526. Under MPEP § 804.03, the doctrine of double patenting is intended to prevent the unjustified extension of patent term. Since the present claims recite different structural configurations and address distinct problems and effects, the double patenting rejection is improper and should therefore be withdrawn.”
The examiner disagrees that substantial structural and functional distinctions recited in claim 1, as understood in its broadest reasonable interpretation, have been overlooked or that the claimed configuration is not taught or suggested by patent applications ‘425 or ‘526 (see above). For maximum clarity, the examiner also notes that the rejection is based on the combination of patent applications ‘425 and ‘526, not solely one application or the other.
The examiner additionally notes that “A double patenting rejection also serves public policy interests by preventing the possibility of multiple suits against an accused infringer by different assignees of patents claiming patentably indistinct variations of the same invention” [MPEP § 804].
Therefore the argument that the double patenting rejection is improper is not persuasive.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.J.O./
Examiner, Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138