DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/10/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4-5, 21-23 and 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandrasekaran et al. (US 10361698) in view of Roberts et al. (US 20150318851).
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With respect to claim 1, Chandrasekaran discloses, in Fig. 2A, power electronics device (Fig, 2A) comprising: a voltage-driven transistor (224); a galvanically isolated gate driver (Fig. 2A lest 224) configured to receive a power signal (signal induced onto 208), a turn-on signal (signal induced onto 216), and a turn-off signal (signal induced onto 214) for the voltage-driven transistor over galvanic isolation implemented using a transformer (transformer of 201); and an energy storage device (210) electrically connected to a gate of the voltage-driven power transistor (via the drain to source conduction path of Q1) and configured to store energy from the power signal received by the galvanically isolated gate driver (stores Vs1 across 208) and use the stored energy to stabilize a gate voltage of the voltage-driven power transistor during an on-state of the voltage-driven power transistor (provides the stabilized voltage of Von to turn on 224, see Fig. 2B), wherein the galvanically isolated gate driver comprises: a first coil (Ns1) configured to receive the power signal over the galvanic isolation (power signal induced on 208); a second coil (NS3) configured to receive the turn-on signal over the galvanic isolation (signal inducted onto 216 that controls the turn on of Q1/224, see Fig. 2B); and a third coil (Ns4) configured to receive the turn-off signal over the galvanic isolation (signal induced onto 214, that controls the turn off of Q4/224, see Fig. 2B) but Chandrasekaran fails to disclose that the transformer is a "coreless transformer".
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However, it is old and well-known to use coreless transformers for galvanic isolation in driving circuits, since, as disclosed in paragraph 0074 of Roberts et al., such coreless transformers a superior in terms of jitter, aging and delay and allow for power to be drawn from input transitions by the power source. Furthermore, coreless transformers do not require additional core elements and thus simplify construction. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use cordless transformers in Chandrasekaran et al. as taught by Roberts et al. for the purpose galvanic isolation as coreless transformers are superior in terms of jitter, aging and delay and allow for power to be drawn from input transitions by the power source.
With respect to claim 2, the combination above produces the power electronics device of claim 1, wherein the galvanically isolated gate driver (Fig. 2A lest 224) comprises: a voltage clamp device (Q4) electrically connected to the gate of the voltage-driven power transistor (via Rg).
With respect to claim 4, the combination above produces a rectification circuit (230) configured to rectify the power signal received at the first coil (Ns1) and energize the energy storage device (210) with the rectified power signal; a first switch device ( Q1) electrically connected between the energy storage device (210) and the gate of the voltage-driven power transistor (224) a failsafe pulldown device (Q2 and 232) electrically connected to the gate of the voltage-driven power transistor wherein the first switch device (Q1) is configured to connect the energy storage device (210) to the gate of the votlage-driven power transistor (224) when the turn on signal at the second coil (Ns3) is active, wherein the failsafe pulldown device is configured to pulldown the gate of the voltage-driven power transistor when the turn-off signal received at the third coil (Ns4) is active.
With respect to claim 5, the combination above produces the power electronics device of claim 4, wherein the galvanically isolated gate drive further comprises: a diode (diode 220 across Q1) having an anode connected to the second coil (Ns3) and a cathode connected to a gate of the first switch device (Q1).
With respect to claim 21, Chandrasekaran discloses, in Fig. 2A, power electronics device (Fig, 2A) comprising: a voltage-driven transistor (224); a galvanically isolated gate driver (Fig. 2A lest 224) configured to receive a power signal (signal induced onto 208), a turn-on signal (signal induced onto 216), and a turn-off signal (signal induced onto 214) for the voltage-driven transistor over galvanic isolation implemented using a transformer (transformer of 201); and an energy storage device (210) electrically connected to a gate of the voltage-driven power transistor (via the drain to source conduction path of Q1) and configured to store energy from the power signal received by the galvanically isolated gate driver (stores Vs1 across 208) and use the stored energy to stabilize a gate voltage of the voltage-driven power transistor during an on-state of the voltage-driven power transistor (provides the stabilized voltage of Von to turn on 224, see Fig. 2B), wherein the galvanically isolated gate driver comprises: a center tapped first coil (Ns1, NS2) configured to receive the power signal and the turn-off signal over the galvanic isolation (power signal induced on 208 off 206) and a second coil (NS3) configured to receive the turn-on signal over the galvanic isolation (signal inducted onto 216 that controls the turn on of Q1/224, see Fig. 2B) but Chandrasekaran fails to disclose that the transformer is a "coreless transformer".
However, it is old and well-known to use coreless transformers for galvanic isolation in driving circuits, since, as disclosed in paragraph 0074 of Roberts et al., such coreless transformers a superior in terms of jitter, aging and delay and allow for power to be drawn from input transitions by the power source. Furthermore, coreless transformers do not require additional core elements and thus simplify construction. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use cordless transformers in Chandrasekaran et al. as taught by Roberts et al. for the purpose galvanic isolation as coreless transformers are superior in terms of jitter, aging and delay and allow for power to be drawn from input transitions by the power source.
With respect to claim 22, the combination above produces the power electronics device of claim 21, wherein the galvanically isolated gate driver further comprises: a rectification circuit (230) configured to rectify the power signal received at the first coil (Ns1, Ns2) and energize the energy storage device (210) with the rectified power signal; a first switch device (Q1) electrically connected between the energy storage device (210) and the gate of the voltage-driven power transistor (Qout via Rg); and a failssafe pulldown device (Q2 and 232) electrically connected t the gate of the voltage-driven power transistor (via Rg), wherein the first switch device (Q1) is configured to connect the energy storage device (210) to the gate of the voltage-driven power transistor (Qout) when the turn-on signal received at the second coil (Ns3) is active, wherein the failsafe pulldown device is configured to pulldown the gate of the voltage driven power transistor (Qout) when the turn-off signal received at the first coil (Ns1, Ns2) is active.
With respect to claim 23, the combination above produces the power electronics device of claim 22, wherein the galvanically isolated driver further comprises: a diode (220) having an anode connected to the second coil (Ns3) and a cathode connected to a gate of the first switch device (Q1).
With respect to claim 27, the combination above produces the power electronics device of claim 22, wherein the center tap of the first coil is electrically (via Ns1 and diode 22) connected to a drain of the first switch device (Q1) through one or more diodes (diode 22).
With respect to claim 28, the combination above produces the power electronics device of claim 21, wherein the galvanically isolated gate driver further comprises: a voltage clamp device (Q2) electrically connected to the gate of the voltage-driven power transistor (via Rg).
Allowable Subject Matter
Claim 6-8, 24-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 6, the prior art of record fails to suggest or disclose wherein the failssafe pulldown device comprises a normally-on pulldown device electrically connected between gate and source of the voltage-driven power transistor, and one or more diodes electrically connected in series between a source and a gate of the normally-on pulldown device as disclosed.
With respect to claim 24, the prior art of record fails to suggest or disclose wherein the failssafe pulldown device comprises a normally-on pulldown device electrically connected to the gate of the voltage-driven power transistor, and one or more diodes electrically connected in series between a source and a gate of the normally-on pulldown device as disclosed.
Claims 29-33 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 29, the prior art of record fails to suggest or disclose a first switch device electrically connected between the energy storage device and a source of the voltage-driven power transistor; and a failsafe pulldown device electrically connected to the gate of the voltage-driven power transistor, wherein a first end and a second end of the center-tapped coil are electrically connected to the gate of the voltage-driven power transistor through the rectification circuit, wherein the second end of the center-tapped coil is electrically connected to a gate of the first switch device through one or more diodes, wherein the center tap of the center-tapped coil is electrically connected to a source of the first switch device, wherein the failsafe pulldown device is configured to pulldown the gate of the voltage- driven power transistor when the turn-off signal received at the center-tapped coil is active.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F(10:00-7:00).
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/KHAREEM E ALMO/Examiner, Art Unit 2836
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