Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 1-20 are presented for examination.
Title
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1-8 and 11-17 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-2, 4-7, 10-12, 14-17 and 20 of U.S. Patent No. 10062438. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are anticipated and the same scope of invention by claims 1-2, 4-7, and 10 of the reference such as a memory system comprising: a nonvolatile semiconductor memory device comprising: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string,
Claims 11-17 of the examined application are anticipated and the same scope of invention by claims 11-12, 14-17 and 20 of the reference such as a method of controlling a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string,
Claims 1, 9, 11 and 18 with the limitation the “source line being disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
Claims 10 and 19 with the limitation the “second word line, the third word line and the fourth word line are disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
6. Claims 1-8 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 7-13 of U.S. Patent No. 10490282. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-6 and 8 of the examined application are anticipated and the same scope of invention by claims 8-13 of the reference such as a memory system comprising: a nonvolatile semiconductor memory device comprising: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string, writing data in the second memory cell of the first string after the writing in the first memory cell of the first string, the second write process includes writing data in the first memory cell of the second string and writing data in the second memory cell of the second string after the writing in the first memory cell of the second string, the third write process includes writing data in the third memory cell of the first string and writing data in the fourth memory cell of the first string after the writing in the third memory cell of the first string, and the fourth write process includes writing data in the third memory cell of the second string and writing data in the fourth memory cell of the second string after the writing in the third memory cell of the second string.
Claims 11-17 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 7-13 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method of controlling a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string,
Claims 1, 9, 11 and 18 with the limitation the “source line being disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
Claims 7 and 17 are obvious to a claim 7 of the reference.
Claims 10 and 19 with the limitation the “second word line, the third word line and the fourth word line are disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
7. Claims 1-8 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 8-14 of U.S. Patent No. 10878913. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are apparatus claims but they encompass the same scope of invention as to that of method claims 8-14 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a memory system comprising: a nonvolatile semiconductor memory device comprising: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string, includes writing data in the third memory cell of the first string and writing data in the fourth memory cell of the first string after the writing in the third memory cell of the first string, and the fourth write process includes writing data in the third memory cell of the second string and writing data in the fourth memory cell of the second string after the writing in the third memory cell of the second string.
Claims 11-17 of the examined application are anticipated and the same scope of invention by claims 8-14 of the reference such as a method of controlling a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string, writing in the first memory cell of the first string, the second write process includes writing data in the first memory cell of the second string and writing data in the second memory cell of the second string after the writing in the first memory cell of the second string, the third write process includes writing data in the third memory cell of the first string and writing data in the fourth memory cell of the first string after the writing in the third memory cell of the first string, and the fourth write process includes writing data in the third memory cell of the second string and writing data in the fourth memory cell of the second string after the writing in the third memory cell of the second string.
Claims 1, 9, 11 and 18 with the limitation the “source line being disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
Claims 10 and 19 with the limitation the “second word line, the third word line and the fourth word line are disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
8. Claims 1-8 and 11-17 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 11100999. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are anticipated and the same scope of invention by claims 1-8 of the reference such as a memory system comprising: a nonvolatile semiconductor memory device comprising: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string,
Claims 11-17 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 9-15 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a 11. A method of controlling a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string, writing data in the third memory cell of the second string and writing data in the fourth memory cell of the second string after the writing in the third memory cell of the second string.
Claims 1, 9, 11 and 18 with the limitation the “source line being disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
Claims 10 and 19 with the limitation the “second word line, the third word line and the fourth word line are disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
9. Claims 1-8 and 11-17 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-2 and 4-8 of U.S. Patent No. 11631463. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are anticipated and the same scope of invention by claims 1-2 and 4-8 of the reference such as a memory system comprising: a nonvolatile semiconductor memory device comprising: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string,
Claims 11-17 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1-2 and 4-8 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method of controlling a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string,
Claims 1, 9, 11 and 18 with the limitation the “source line being disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
Claims 10 and 19 with the limitation the “second word line, the third word line and the fourth word line are disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
10. Claims 1-8 and 11-17 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-2 and 4-8 of U.S. Patent No. 12073885. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-8 of the examined application are anticipated and the same scope of invention by claims 1-2 and 4-8 of the reference such as a memory system comprising: a nonvolatile semiconductor memory device comprising: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string, process, to perform a second write process after the first write process, to perform a third write process after the second write process, and to perform a fourth write process after the third write process, wherein the first write process includes writing data in the first memory cell of the first string and writing data in the second memory cell of the first string after the writing in the first memory cell of the first string, the second write process includes writing data in the first memory cell of the second string and writing data in the second memory cell of the second string after the writing in the first memory cell of the second string, the third write process includes writing data in the third memory cell of the first string and writing data in the fourth memory cell of the first string after the writing in the third memory cell of the first string, and the fourth write process includes writing data in the third memory cell of the second string and writing data in the fourth memory cell of the second string after the writing in the third memory cell of the second string.
Claims 11-17 of the examined application are method claims but they encompass the same scope of invention as to that of apparatus claims 1-2 and 4-8 of the reference. For example, all claims of the examined application are anticipated and the same scope of invention by all claims of the reference such as a method of controlling a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including: a substrate; first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell; a bit line electrically connected to the first and the second strings; a first select gate line electrically connected to a gate of the select transistor of the first string; a second select gate line electrically connected to a gate of the select transistor of the second string; a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string; a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string, a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string; and a source line electrically connected to the first string,
Claims 1, 9, 11 and 18 with the limitation the “source line being disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
Claims 10 and 19 with the limitation the “second word line, the third word line and the fourth word line are disposed between the bit line and the substrate” is obvious to Fig. 19, a paragraph 124 of the reference 20110194357.
11. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
12. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827