DETAILED ACTION
Statement of claims
The present application includes:
Claims 1-20 are pending in the application. Claims 1-20 are being considered on the merits.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/13/2024 . The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2020/0320031, Wu hereinafter) in view of Haramaty et al. (US 2016/0021016, Haramaty hereinafter).
As to claim 1, Wu teaches a first integrated circuit device (e.g., see FIG. 5, “510”)comprising:
one or more processing units (“CPU 525”, FIG. 5) to generate data packets to be sent to a second integrated circuit device (e.g., para 8, “a request or packet to be generated ” for “two (or more) dies that are interconnected using an example MCPL 520”, “an MCPL can be applied to any interconnect or link connecting a die (e.g., 510) and other components, including connecting two or more dies (e.g., 510, 515), connecting a die (or chip) to another component off-die, connecting a die to another device or die off-package (e.g., 505), connecting die to a BGA package, implementation of a Patch on Interposer (POINT) in para 62) ; and
an interconnect communication unit (e.g., “510”, FIG. 5) to send the data packets to the second integrated circuit device via a chip-to-chip interconnect (e.g., para 62 and 63, “multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520”, “ dies and other components within a multichip package 505 can themselves include interconnect or other communication fabrics (e.g., 535, 550) providing the infrastructure for communication between components (e.g., 525-530 and 540-545) within the device (e.g., 510, 515 respectively). The various components and interconnects (e.g., 535, 550) may potentially support or use multiple different protocols” for “ for the data signals to have both an upstream and downstream data transfer” , “send and receive data between the devices” in para 67, see FIG. 6) , and manage the data packets sent to the second integrated circuit device via the chip-to-chip interconnect using a layered communication architecture supporting a credit-based data flow control (e.g., para [0058] transaction layer 205, link layer 210, and physical layer 220 a”, “ PCIe protocol stack, a layered protocol stack “ (1) a first layer to assemble packets, i.e. a transaction layer; a second layer to sequence packets, i.e. a link layer; and a third layer to transmit the packets, i.e. a physical layer. As a specific example, a common standard interface (CSI) layered protocol is utilized.”.
para 44, “The translation layer 205 typically manages credit-base flow control for TLPs. “, [0045] In addition PCIe utilizes credit-based flow control.“) ,wherein the chip-to-chip interconnect comprises a direct chip-to-chip connection between the first integrated circuit device as a first chip and the second integrated circuit device as a second chip to provide a direct communication between the first integrated circuit device and the second integrated circuit device (e.g., see FIG. 5, para [0062] FIG. 5 is a simplified block diagram 500 illustrating an example multi-chip package 505 that includes two or more chips, or dies, (e.g., 510, 515) communicatively connected using an example multi-chip package link (MCPL) 520. While FIG. 5 illustrates an example of two (or more) dies that are interconnected using an example MCPL 520. Thus, wherein the chip-to-chip interconnect comprises a direct chip-to-chip connection between the first integrated circuit device as a first chip and the second integrated circuit device as a second chip to provide a direct communication between the first integrated circuit device and the second integrated circuit).
However, Wu does not teach the credit-based data flow control updates a total-blocks-sent counter that counts a total number of blocks sent to the second integrated circuit device based on a block size of each sent data packet.
Haramaty teaches credit-based data flow control updates a total-blocks-sent counter that counts a total number of blocks sent to the second integrated circuit device based on a block size of each sent data packet (e.g. see FIG. 1, [0032] In the example of FIG. 1, nodes 24 and 28 exchange flow-control information (e.g., credit count information) that is represented internally using 18-bit resolution, via control packets in which flow-control information occupies 12-bit resolution fields. The 18-bit and 12-bit representations correspond to 64 B and 4 KB block size respectively. The 18-bit resolution flow-control information is converted to 12-bit resolution for sending over the network and back to 18-bit resolution at the destination.
para [0035] When sending node 28 receives a 12-bit resolution credit count via a respective flow-control packet from receiving node 24, transmitter controller 40 converts the 12-bit resolution credit count to 18-bit resolution using an up converter 56, and updates credit counter 48 accordingly. Up converter 56 can be implemented by multiplying its input by 64”).
And [0026] In some embodiments, the receiving node calculates the credit count with respect to the received blocks count. Each of the sending and receiving nodes holds an updated 18-bit resolution count of the number of 64 B blocks delivered since link initialization. To compensate for possible packet loss, the sending node occasionally informs the receiving end of the cumulative number of delivered blocks” ).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Wu with those of Haramaty because both references are directed to related systems addressing similar technical problems within the same field and seek to improve system performance, reliability, and efficiency.
Wu et al. disclose A first integrated circuit device comprising: one or more processing units to generate data packets to be sent to a second integrated circuit device; and an interconnect communication unit to send the data packets to the second integrated circuit device via a chip-to-chip interconnect, and manage the data packets sent to the second integrated circuit device via the chip-to-chip interconnect using a layered communication architecture supporting a credit-based data flow control while Haramaty et al. teaches the credit-based data flow control that updates a total-blocks-sent counter that counts a total number of blocks sent to the second integrated circuit device based on a block size of each sent data packet.
Incorporating the teachings of Haramaty et al. into the system of Wu et al. would have been a predictable and logical modification, yielding improved operational robustness and efficiency without requiring undue experimentation.
Such a combination would merely involve the substitution or integration of known elements performing their established functions, as taught by Haramaty et al., into the system of Wu et al., consistent with design incentives and market demands for improved performance and scalability. Moreover, Haramaty et al. explicitly recognize benefits to allow “ the sending and receiving nodes remain synchronized even when some of the data packets are lost while being sent over link 32.” (see Haramaty, para 39) . —that would naturally be desirable in the system of Wu et al.
Accordingly, to one of ordinary skill in the art would have had a reasonable expectation of success in combining Wu et al. with Haramaty et al., and the combination represents no more than the predictable use of prior art elements according to their known functions.
As to claim 2, Wu does not teach wherein the interconnect communication unit comprises a send buffer to store the data packets sent to the second integrated circuit device via the chip-to-chip interconnect, and wherein the interconnect communication unit is to remove one of the data packets stored in the send buffer upon receiving an acknowledgement of the data packet from the second integrated circuit device. However, Haramaty teaches wherein the interconnect communication unit comprises a send buffer (e.g., TX_Buffer”, FIG. 1) to store the data packets sent to the second integrated circuit device via the chip-to-chip interconnect (e.g., see FIG. 1, para [0042] The configuration of computing system 20 in FIG. 1, and in particular the configurations of nodes 24 and 28, is an example configuration, which is chosen purely for the sake of conceptual clarity. In alternative embodiments, any other suitable system configuration or node can also be used. FIG. 1 shows a single port of each of the sending and receiving nodes. Real-life nodes, however, typically comprise multiple ports, and the circuitry shown in the figure is typically duplicated per port (or at least for each port that is designated to communicate over a long-haul link).), and wherein the interconnect communication unit is to remove one of the data packets stored in the send buffer upon receiving an acknowledgement of the data packet from the second integrated circuit device (e..g., para [0052] At a synchronization step 116, when receiving node 24 receives from sending node 28 a 12-bit resolution sent blocks count N_ACC.sub.—4 KB (derived from sent blocks counter 44), up converter 74 converts this count to an 18-bit representation by multiplying N_ACC.sub.—4 KB by 64, and the receiver controller stores the 18-bit result in received blocks counter 66. The method then loops back to step 104 to convert the credit count N_CREDITS.sub.—64 B from step 112 to a 12-bit representation for publishing the credit count to the sending node.
Thus, wherein the “synchronization step 116” coupled with the “ receiving node 24 receives from sending node 28 a 12-bit resolution sent blocks count N_ACC.sub.—4 KB (derived from sent blocks counter 44)” and “ buffer 60 is assumed empty and receiver controller 62 clears received blocks counter 66, and initializes the 18-bit resolution credit count to the size of buffer 60 in units of 64 B. For example, for a 128 KB buffer the initial 18-bit resolution credit count equals 2048” in para 46, therefore to remove one of the data packets stored in the send buffer upon receiving an acknowledgement of the data packet from the second integrated circuit device ).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu by adopting the teachings of Haramaty to allow “ the sending and receiving nodes remain synchronized even when some of the data packets are lost while being sent over link 32.” (see Haramaty, para 39).
As to claim 3, Wu does not teach wherein the interconnect communication unit is to send an updated count of the total-blocks-sent counter to the second integrated circuit device. However, Haramaty teaches herein the interconnect communication unit is to send an updated count of the total-blocks-sent counter to the second integrated circuit device (e.g., para 26, “Each of the sending and receiving nodes holds an updated 18-bit resolution count of the number of 64 B blocks delivered since link initialization. To compensate for possible packet loss, the sending node occasionally informs the receiving end of the cumulative number of delivered blocks.” ).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu by adopting the teachings of Haramaty to allow “ the sending and receiving nodes remain synchronized even when some of the data packets are lost while being sent over link 32.” (see Haramaty, para 39)
As to claim 4, Wu does not teach wherein the interconnect communication unit is to: receive a credit-limit value of the second integrated circuit device, and determine whether to send another data packet to the second integrated circuit device based on whether a sum of the updated count of the total-blocks-sent counter and a block size of the other data packet is less than or equal to the credit-limit value of the second integrated circuit device . However, Haramaty teaches wherein the interconnect communication unit is to: receive a credit-limit value of the second integrated circuit device, and determine whether to send another data packet to the second integrated circuit device based on whether a sum of the updated count of the total-blocks-sent counter and a block size of the other data packet is less than or equal to the credit-limit value of the second integrated circuit device (e.g., para 0026] In some embodiments, the receiving node calculates the credit count with respect to the received blocks count. Each of the sending and receiving nodes holds an updated 18-bit resolution count of the number of 64 B blocks delivered since link initialization. To compensate for possible packet loss, the sending node occasionally informs the receiving end of the cumulative number of delivered blocks.) .
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu by adopting the teachings of Haramaty to allow “ the sending and receiving nodes remain synchronized even when some of the data packets are lost while being sent over link 32.” (see Haramaty, para 39)
As to claim 5, Wu does not teach wherein the interconnect communication unit further comprises: a receive buffer to store data packets received from the second integrated circuit device via the chip-to-chip interconnect, and an absolute-blocks-received counter that counts a total number of blocks received from the second integrated circuit device based on block sizes of the received data packets. However, Haramaty teaches wherein the interconnect communication unit further comprises: a receive buffer to store data packets received from the second integrated circuit device via the chip-to-chip interconnect, and an absolute-blocks-received counter that counts a total number of blocks received from the second integrated circuit device based on block sizes of the received data packets (e.g., para 33, “Transmitter controller 40 comprises a sent blocks counter 44 that counts the total number of 64 B blocks sent to the network since link initialization.” for “the receiving end could publish its available buffering space to the sending end using credits of the buffering block size. In the example of a receive buffer comprising 64 B blocks, the 12-bit fields constraint limits the maximal credit count to 2.sup.11=2048, and therefore also limits the buffer size to 2048*64 B=128 KB and the respective link length to 1.05 Km. “ in para [0022]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu by adopting the teachings of Haramaty to allow “ the sending and receiving nodes remain synchronized even when some of the data packets are lost while being sent over link 32.” (see Haramaty, para 39)
As to claim 6, Wu does not teach wherein the interconnect communication unit is to: calculate a credit limit of the first integrated circuit device by adding a count of the absolute-blocks-received counter and available space of the receive buffer, and send the calculated credit limit of the first integrated circuit device to the second integrated circuit device, wherein the second integrated circuit device is to determine whether to send another data packet to the first integrated circuit device based on the calculated credit limit of the first integrated circuit device . However, Haramaty teaches wherein the interconnect communication unit is to: calculate a credit limit of the first integrated circuit device by adding a count of the absolute-blocks-received counter and available space of the receive buffer, and send the calculated credit limit of the first integrated circuit device to the second integrated circuit device, wherein the second integrated circuit device is to determine whether to send another data packet to the first integrated circuit device based on the calculated credit limit of the first integrated circuit device (e.g., para 6, “a module, and a system for calculating a credit limit for an interface of a second device, that is capable of receiving multiple packets simultaneously from a first device. Generally, the multiple packets are simultaneously received at an interface on the second device, each packet being one of a plurality of packet types, and a flow control credit limit to be transmitted to the first device is adjusted based on the combination of packet types of the simultaneously received packets”) .
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Wu by adopting the teachings of Haramaty to allow “ the sending and receiving nodes remain synchronized even when some of the data packets are lost while being sent over link 32.” (see Haramaty, para 39)
As to claim 7, Wu teaches wherein the interconnect communication unit comprises circuitry logic configured to support a physical layer network communication protocol, including an Ethernet communication protocol, to send the data packets to the second integrated circuit device via the chip-to-chip interconnect (e.g., para 70, “ protocols can also be supported including Ethernet protocol, Infiniband protocols, and other PCIe fabric based protocols. The combination of the Logical PHY and physical PHY can also be used as a die-to-die interconnect to connect a SerDes PHY (PCIe, Ethernet, Infiniband or other high speed SerDes) on one Die to its upper layers that are implemented on the other die, “).
As to claim 8, Wu teaches wherein the interconnect communication unit further comprises additional circuitry logic configured to support communication protocols beyond the physical layer network communication protocol (e.g., para 78, “data in sequential time period windows (e.g., n+1 (720) and n+2 (725)) can be from different transactions to which different protocols are to apply, and stream signals (e.g., 735, 740) can be encoded accordingly to identify the different protocols applying to the sequential bytes of data on the data lanes (e.g., DATA[0-49]),).
As to claim 9, Wu teaches wherein the layered communication architecture of the interconnect communication unit comprises an application layer configured to manage work requests from a software application and access data in a high-bandwidth memory (e.g., para 144, “the invention is associated with a processor bus 2210 (e.g. other known high performance computing interconnect), a high bandwidth memory path 2218 to memory 2220, “) , and a message-dispatch-and-reassembly layer configured to manage segmentation and reassembly of the accessed data into the data packets for dispatching based on the work requests presented from the application layer (e.g., para 144, “a point-to-point link to graphics accelerator 2212 (e.g. a Peripheral Component Interconnect express (PCIe) compliant fabric), a controller hub interconnect 2222, an I/O or other interconnect (e.g. USB, PCI, PCIe)”, wherein “PCI Express implements split transactions (transactions with request and response separated by time), allowing the link to carry other traffic while the target device gathers data for the response.) is well known , therefore a message-dispatch-and-reassembly layer configured to manage segmentation and reassembly of the accessed data into the data packets for dispatching based on the work requests presented from the application layer) .
As to claim 10, Wu teaches wherein the layered communication architecture of the interconnect communication unit further supports a retransmission data flow control that communicates with the second integrated circuit device when a data packet sent from the second integrated circuit device was received with error and causes the second integrated circuit device to retransmit the data packet received with error (e.g., para [0104] In yet another example, illustrated in FIG. 14C, an example bit mapping of link-to-link packets (e.g., LLP packets) sent over an example MCPL is shown. LLPs can be 4 bytes each and each LLP (e.g., LLP0, LLP1, LLP2, etc.) can be sent four consecutive times, in accordance with fault tolerance and error detection within an example implementation. For instance, failure to receive four consecutive identical LLPs can indicate an error. Additionally, as with other data types, failure to receive a VALID in a proceeding time window, or symbol, can also indicate an error. In some instances, LLPs can have fixed slots. Additionally, in this example, unused, or “spare,” bits in the byte time period, can result in logical Os being transmitted over two of the fifty lanes (e.g., DATA[48-49]), among other examples).
As to claim 11, see rejection of claims 1 above . Wu teaches further a method comprising: configuring a first integrated circuit device comprising one or more processing units to generate data packets and an interconnect communication unit to send the data packets to a second integrated circuit device; establishing a chip-to-chip interconnect between the first integrated circuit device and the second integrated circuit device ( e.g., see FIG. 1) .
As to claim 12-16, see rejection of claims 2-7 above.
As to claim 17, see rejection of claims 1-4 above. Wu teaches further a first integrated circuit device comprising: one or more processing units to generate data packets; and an interconnect communication unit comprising: circuitry logic configured to support a physical layer network communication protocol to send the data packets to a second integrated circuit device via a chip-to-chip interconnect, wherein the chip-to-chip interconnect comprises a direct chip-to-chip connection between the first integrated circuit device as a first chip and the second integrated circuit device as a second chip (see FIG. 1).
As to claims 18-20, see rejection of claims 4-6 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gregg et al. (US 20080165690). Discloses An Infiniband flow control scheme disables credit based flow control so that transmission distances can be extended. An Infiniband credit based flow control suffers from round trip time lag that slows transmission rates. Disabling Infiniband credit based flow control enables back to back packet transmission because credit counts are ignored. Nonetheless, packets can be lost due to overruns in a receive buffer, therefore, packet drop detection mechanisms are employed so that the Infiniband receiver can send requests to the Infiniband transmitter to temporarily slow its Infiniband transmission rate.
Ganga et al. (US 20170272370) discloses a method for enabling class-based credit flow control for a network node in communication with a link partner using an Ethernet communications protocol. The method includes receiving a control frame from the link partner. The control frame includes at least one field for specifying credit for at least one traffic class and the credit is based on available space in a receive buffer associated with the at least one traffic class. The method further includes sending data packets to the link partner based on the credit, the data packets associated with the at least one traffic class.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDOU K SEYE whose telephone number is (571)270-1062. The examiner can normally be reached M-F 9-5:30.
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/ABDOU K SEYE/Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198
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