DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is sent in response to Applicant’s Communication received 7/8/2024 for application number 18/766,265. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and claims.
Claims 1 – 20 are presented for examination.
Drawings
Examiner contends that the drawings filed 7/8/2024 are acceptable for examination proceedings.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5-9, 11, and 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mudulodu PGPUB 2019/0243991, and further in view of Wang et al. (hereinafter as Wang) PGPUB 2019/0064910.
As per claim 1, Mudulodu teaches a method, comprising:
providing a device that supports at least two power states: a sleep state and an awake state [FIG. 2 and 0044 and 0057: (second node may transition to sleep mode; thus the second node supports at least a sleep state and a wake state)];
monitoring for power state information via a hardware interface and via a communication interface [FIG. 2: (1st comm link (communication interface 214) and 2nd comm link (hardware interface 216))], wherein the hardware interface allows communication between a physical layer (PHY) transceiver implemented at the device [FIG. 2: (second communication transceiver 212 (PHY transceiver) of second node)] and a PHY controller implemented at another device [FIG. 2: (second communication transceiver 206 (PHY controller) of first node)], and
wherein the communication interface allows communication between the device and the another device [0039, 0048, 0053: (wakeup code is transmitted from the first node 202 to the second node 208 using communication link 214)]; and
coordinating a change in power state of the device at least partially based on reception of power state information via the hardware interface and the communication interface [0036, 0049, and 0063: (if the received wakeup code on link 214 matches a template code derived from the protocol established on link 216, then the second node may wake up (change in power state)].
Mudulodu does not explicitly teach that the device is a system basis chip, that the another device is a microcontroller, and that hardware interface and the communication interface allows communication between the system basis chip and the microcontroller. In other words, Mudulodu does not explicitly teach the second node is a system basis chip and that the first node is a microcontroller.
Wang teaches a circuit that may be placed in the wake or sleep mode (PMIC) that is connected to another circuitry (embedded system 110) over a system interface. Wang is thus similar to Mudulodu because they both teach a device that may be placed in to a wake or sleep mode based on communication with another device. Wang further teaches a system basis chip [FIG. 4: (PMIC 402), 0028, 0035, 0037, 0040, 0045, and claim 5: (PMIC is an integrated circuit, and thus can be considered a system basis chip since it also is an integrated circuit that performs power management)], that the another device is a microcontroller [FIG. 4, FIG. 5, 0015, 0023, 0028, 0035, 0037, 0040, 0045, and claim 5: (embedded system 110 is scalable processor or system on chip; thus it is a microcontroller)], and that hardware interface and the communication interface allows communication between the system basis chip and the microcontroller [FIG. 4 and FIG. 5: (a system interface 410 is between the embedded system and the PMIC)].
The combination of Mudulodu and Wang leads to the first node in Wang being the embedded system and the second node in Wang being the PMIC/system basis chip that may be placed into a low power mode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Wang’s teachings of a processing component managing power state of an power managing IC/SBC over a connection in Mudulodu. Wang teaches an area in which Mudulodu’s teachings may be applied. One of ordinary skill in the art would have been motivated to specify the first node is the processing component and the second node is an SBC in Mudulodu because it allows Mudulodu’s teachings to be applied in situations such as communication between a processor and SBC so that the SBC may be reliably turned off or on to reduce power usage of the SBC/PMIIC.
As per claim 2, Mudulodu and Wang teach the method of claim 1, wherein monitoring for power state information includes monitoring for: power management commands and status information about power states [Mudulodu 0039, 0053, and 0054: (information for establishing a protocol and for sending a wakeup code) or Wang 0037: (system state or sleep or wake signals are communicated)].
As per claim 5, Mudulodu and Wang teach the method of claim 1, comprising: receiving a first power management command, wherein the first power management command is received via the hardware interface [Mudulodu 0042: (communicate protocol selection over link 216)]; receiving a second power management command, wherein the second power management command is received via the communication interface [Mudulodu 0039, 0048, 0053: (wakeup code is transmitted from the first node 202 to the second node 208 using communication link 214)]; and coordinating the change in power state of the system basis chip at least partially based on reception of both the first power management command and the second power management command [0036, 0049, and 0063: (if the received wakeup code on link 214 matches a template code derived from the protocol established using link 216, then the second node may wake up (change in power state)].
As per claim 6, Mudulodu and Wang teach the method of claim 5, comprising: decoding the first power management command from signals received via the hardware interface [Mudulodu 0042 and 0049: (protocol for wakeup code evaluated to determine a template wakeup code that will be accepted)]; and decoding the second power management command from signals received via the communication interface [Mudulodu 0048 and 0049: (wakeup code is received and analyzed/compared to template code)].
As per claim 7, Mudulodu and Wang teach the method of claim 5, wherein the power state of the system basis chip does not change responsive to only one of the first power management command or the second power management command [Mudulodu 0049: (if there is no match, sleep is continued and thus no power state change)].
As per claim 8, Mudulodu and Wang teach The method of claim 5, wherein both the first power management command and the second power management command respectively comprise: a wake command or a sleep command [Mudulodu 0049: (wakeup code (wakeup command))].
As per claim 9, Mudulodu and Wang teach the method of claim 1, wherein the communication interface is separate and distinct from the hardware interface [Mudulodu FIG. 2: (1st comm link is distinct from 2nd comm link)].
As per claim 11, Mudulodu and Wang teach the method of claim 1, comprising: staging a change in power state of the system basis chip from a first state to a second state through multiple intermediate states, wherein one of the first state or the second state is an awake state and the other one of the first state or the second state is a sleep state [Wang FIG. 2 and 0024: (transition between an active state_1 to intermediate state_2 to intermediate state_3 to safe state 210 to off state 212)].
As per claim 13, Mudulodu and Wang teach the method of claim 1, wherein the hardware interface for communication between the PHY transceiver and a PHY controller is integrated in the microcontroller [Mudulodu FIG. 2: (transceiver is integrated into first node and so is the link from it to the second node) and Wang FIG. 4, FIG. 5, 0015, 0023, 0028, 0035, 0037, 0040, 0045, and claim 5: (embedded system 110 is the equivalent of the first node in Mudulodu and it is connected to link to PMIC/SBC)].
As per claim 14, Mudulodu teaches an apparatus, comprising:
a first driver to implement functions of a PHY transceiver at a device [0040-0041: (communication transceiver 212 at second node 208)];
a second driver to implement functions of the device, the second driver different than the first driver [0048 and 0062: (wakeup receiver 210 implements wakeup functions of the second node; receiver 210 is different than the transceiver 212)]; and
a logic circuit [FIG. 2 first node 202] to coordinate a change in power state of the device with a change in power state at the PHY transceiver via commands issued to the first driver and the second driver [FIG. 2, 0036, 0049, and 0063: (if the received wakeup code on link 214 matches a template code derived from the protocol established through link 216, then the second node may wake up (change in power state)].
Mudulodu does not explicitly teach the device is a system basis chip.
Wang teaches a circuit that may be placed in the wake or sleep mode (PMIC) that is connected to another circuitry (embedded system 110) over a system interface. Wang is thus similar to Mudulodu because they both teach a device that may be placed in to a wake or sleep mode based on communication with another device. Wang further teaches a system basis chip [FIG. 4: (PMIC 402), 0028, 0035, 0037, 0040, 0045, and claim 5: (PMIC is an integrated circuit, and thus can be considered a system basis chip since it also is an integrated circuit that performs power management)], that the another device is a logic circuit [FIG. 4, FIG. 5, 0015, 0023, 0028, 0035, 0037, 0040, 0045, and claim 5: (embedded system 110 is scalable processor or system on chip; thus it is a logic circuit)].
The combination of Mudulodu and Wang leads to the first node in Wang being the embedded system and the second node in Wang being the PMIC/system basis chip that may be placed into a low power mode.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Wang’s teachings of a processing component managing power state of an power managing IC/SBC over a connection in Mudulodu. Wang teaches an area in which Mudulodu’s teachings may be applied. One of ordinary skill in the art would have been motivated to specify the first node is the processing component and the second node is an SBC in Mudulodu because it allows Mudulodu’s teachings to be applied in situations such as communication between a processor and SBC so that the SBC may be reliably turned off or on to reduce power usage of the SBC/PMIIC.
As per claim 15, Mudulodu and Wang teach the apparatus of claim 14, wherein the system basis chip supports at least two power states: a sleep state and an awake state [Mudulodu FIG. 2 and 0044 and 0057: (second node may transition to sleep mode; thus the second node supports at least a sleep state and a wake state)];.
As per claim 16, Mudulodu and Wang teach the apparatus of claim 14, wherein the logic circuit to: monitor for power state information via a hardware interface and via a communication interface [FIG. 2: (1st comm link (communication interface 214) and 2nd comm link (hardware interface 216))], wherein the hardware interface allows communication between the PHY transceiver implemented at the system basis chip [Mudulodu FIG. 2: (second communication transceiver 212 (PHY transceiver) of second node)] and a PHY controller implemented at a microcontroller [Mudulodu FIG. 2: (second communication transceiver 206 (PHY controller) of first node) and Wang FIG. 4, FIG. 5, 0015, 0023, 0028, 0035, 0037, 0040, 0045, and claim 5: (embedded system 110 is scalable processor or system on chip; thus it is a microcontroller)], and wherein the communication interface allows communication between the system basis chip and the microcontroller [0039, 0048, 0053: (wakeup code is transmitted from the first node 202 to the second node 208 using communication link 214)]; and coordinate the change in the power state of the system basis chip with the change in power state of the PHY transceiver at least partially based on reception of power state information via both the hardware interface and the communication interface [0036, 0049, and 0063: (if the received wakeup code on link 214 matches a template code derived from the protocol established on link 216, then the second node may wake up (change in power state)].
Claim 17 is similar in scope to claim 2 as addressed above and is thus rejected under the same rationale.
As per claim 18, Mudulodu and Wang teach the apparatus of claim 16, wherein the logic circuit comprises: a finite-state-machine (FSM) to initiate a change in power state of the system basis chip at least partially based on power state information received via the hardware interface and the communication interface indicating a coordinated change in power state for the PHY transceiver [Mudulodu FIG. 1: (process shown is a state machine that determines whether to change power state at step 112) or Wang FIG. 2].
As per claim 19, Mudulodu and Wang teach the apparatus of claim 16, wherein the logic circuit comprises: a finite-state-machine (FSM) to stage a change in power state of the system basis chip from a first state to a second state through multiple intermediate states, wherein one of the first state or the second state is an awake state and the other one of the first state or the second state is a sleep state [Wang FIG. 2 and 0024: (state machine and transition between an active state_1 to intermediate state_2 to intermediate state_3 to safe state 210 to off state 212)].
Claim 20 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mudulodu PGPUB 2019/0243991 in view of Wang et al. (hereinafter as Wang) PGPUB 2019/0064910, and further in view of Devarajan et al. (hereinafter as Devarajan) PGPUB 2021/0325951.
As per claim 3, Mudulodu and Wang teach the method of claim 1.
Mudulodu and Wang do not explicitly teach wherein coordinating the change in power state of the system basis chip comprises: coordinating the change in power state of the system basis chip with a change in power state of the PHY transceiver.
Devarajan teaches a system basis chip that receives a wake signal, and that the SBC being connected to an MCU over multiple connections. Devarajan is thus similar to Mudulodu and Wang. Devarajan further teaches wherein coordinating the change in power state of the system basis chip comprises: coordinating the change in power state of the system basis chip with a change in power state of the PHY transceiver [FIG. 1 – FIG. 2, 0016-0018, 0020, and 0022-0024: (SBC 120 includes a transceiver CAN SBC 160/260, and SBC 120 and CAN SBC 160/260 can receive wake signals to transition away from a sleep state; SBC 120 can control CAN SBC 160 transceiver to operate in a sleep mode; thus there is a coordination in change of power state of SBC 120 with a change in power state of CAN SBC 160/transceiver)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Devarajan’s teachings of the SBC chip coordinating its power change with the power change of the transceiver in Mudulodu and Wang. One of ordinary skill in the art would have been motivated to coordinate the power state change of the transceiver of the second node with the power state change of the second node in Mudulodu because it ensures that only the necessary components (wakeup receiver) are powered while other components are powered down to further save power.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mudulodu PGPUB 2019/0243991 in view of Wang et al. (hereinafter as Wang) PGPUB 2019/0064910, and further in view of de Haas et al. (hereinafter as de Haas)1 PGPUB 2023/0179225.
As per claim 10, Mudulodu and Wang teach the method of claim 1.
Mudulodu and Wang do not explicitly teach wherein the PHY transceiver and the PHY controller together form a 10SPE PHY having a split-PHY architecture.
de Haas teaches a device 101 being coupled to another device 106 using multiple links including a transceiver with PHY part. de Haas is thus similar to Mudulodu and Wang. de Haas further teaches wherein the PHY transceiver and the PHY controller together form a 10SPE PHY having a split-PHY architecture [0109: (transceiver part may include an Ethernet 10BASE-T1S transceiver for connecting with PHY of 106)].
The combination of Mudulodu and Wang with de Haas leads to the transceiver link being 10SPE PHY.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use de Haas’ teachings of 10BASE-T1S/10SPE PHY in Mudulodu and Wang. One of ordinary skill in the art would have been motivated to use such ethernet protocol in Mudulodu and Wang because it allows for faster communication, thus improving operation of the devices.
Allowable Subject Matter
Claims 4 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims (e.g. claims 3 or 11 respectively).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR §1.111(c).
Daoura et al. (PGPUB 2024/0362994) teaches a chip 4500 that is connected to microprocessor through multiple connections, one of which is through a modem [FIG. 45].
Jiang et al. (PGPUB 2024/0154186) shows a system basis chip U2 being connected two ways to microcontroller U4 [FIG. 2].
Hoffer et al. (PGPUB 2021/0028632) teaches an SBC 26 or 86 that receives a signal from a first microcontroller 24 and a second microcontroller 84 to generate a combined signal 63 [FIG. 2].
Jiang (PGPUB 2020/0252868) teaches a transceiver 100 of a SBC being connected to a microcontroller 160 over multiple connections, and providing a wake signal to the microcontroller 160.
Dahlen et al. (PGPUB 2008/0162964) teaches on a link layer, an AND gate that receives as input a signal transmitted over a PHY later and a status signal from a processor.
Atwell et al. (USPAT 6,646,941) teaches an AND gate that receives as input a signal provided as a result of a 1st control signal over link 128 and a 2nd control signal provided over like 126.
Potlapalli et al. (PGPUB 2024/0297588) teaches activating and deactivating the PMIC.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY CHAN whose telephone number is (571)270-5134. The examiner can normally be reached Monday - Friday 10-7 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 5712703779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY CHAN/Primary Examiner, Art Unit 2175
1 Cited in IDS on 4/14/2025.
Prosecution Insights