DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicants’ submission filed on 06/01/26 has been entered.
Claims 1, 2, 6, 7, 11, and 12 (is/are) amended. Thus, claims 1-20 are pending in the present application. Claims 1-20 are pending. IDS filed 09/21/26 have been considered. PTO-1449 are attached.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 706.02(1)(1) - 706.02(1)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-1I.jsp
Claims 1-20 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,586,495.
For example, claim 1 of the present application recites “An apparatus comprising: an error correction code (ECC) circuit configured to: receive an enable signal; and perform an ECC operation on first data based at least in part on fuse data from one or more fuses to provide corrected first data-; and wherein the ECC circuit is configured to based at least in part on the enable signal, provide one of the first data or the corrected first data at an output based at least in part on the enable signal and provide second data at a second output. Whereas claim 1 of US PN: 11,586,495 recites "An apparatus comprising: an error correcting code (ECC) circuit configured to receive an enable signal and to receive first fuse data and second fuse data via the fuse bus, wherein the ECC logic circuit is configured to perform an ECC operation on the first fuse data based on a portion of the second fuse data to provide corrected first fuse data, wherein the ECC logic circuit is configured to provide one of the first fuse data or the corrected first fuse data at an output based on the enable signal; and a latch circuit comprising a plurality of latches configured to selectively replace a group of defective memory cells based on the one of the first fuse data or the corrected first fuse data".
The examiner would like to point out that claim 1 of the present application is substantially the same of claim 1 of U.S. Patent No. 11,586,495. One is just an embodiment of the other and the claims are obvious variations of each other and not patentably distinct.
Rationale:
The instant application is a broader version of claim 1 of U.S. Patent No. 11,586,495, and several limitations in patented claim 1 have removed from the instant application of claim 1. Thus, claim 1 of the instant application may be considered as defining a broader genus version of the species defined in claim 1 of U.S. Patent No. 11,586,495. Therefore, the claims are obvious variations of each other and not patentably distinct. Further, it has been held that the omission of an element and its function is an obvious expedient if the remaining elements perform the same functions as before. See In re Karlson, 136 USPQ 184 (CCPA 1963). Also note Ex parte Rainu, 168 USPQ 375 (BdPatApp&Int 1970); omission of a reference element whose function is not needed would be obvious to one skilled in the art.
Other parallel independent of the instant application have corresponding issues with the independent claims of Patent No. 11,586,495 are also rejected under non-statutory obviousness-type double patenting for the same rationales discussed above.
Dependent claims 2-5 and 12-10 and are deemed obvious over dependent claims 1,9, and 12-15 of the '495 application for the same rationales discussed above.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 8, and 11 recites the limitation “based at least in part on the enable signal, provide one of the first data or the corrected first data at an output and provide second data at a second output” No support for the limitation appears in the specification. The specification Paragraph [0028] only discloses “in operation, the ECC circuit 210 may operate in one of at least two different modes. In an example, the mode of operation of the ECC circuit 210 may be controlled by the value of the ECC enable signal. The ECC enable signal may be additional fuse data from a fuse array or may be another configuration parameter or setting from the semiconductor device. In a first mode of operation, the ECC logic 211 may be disabled or unused, and ECC circuit 210 may provide the FuseData<14:8> (via the multiplexers 212 and the multiplexers 213) to the fuse latch circuit 220(1) and the FuseData<7:1> (via the multiplexers 214) to the fuse latch circuit 220(2). When operating in the first mode (e.g., with the ECC logic 211 disabled or unused), the ECC circuit 210 and the fuse latch circuits 220(1)-(2) may operate with full redundancy for high yield applications, such as for semiconductor devices that are early in a process lifecycle”. No portion of the specification specifically discloses or “based at least in part on the enable signal, provide one of the first data or the corrected first data at an output and provide second data at a second output” as recited in the claims.
Dependent claims depend from the base claims and inherently include limitations therein and therefore are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), second paragraph as well. Corrections are requested.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites the limitation “perform an ECC operation on first data based at least in part on fuse data from one or more fuses to provide corrected first data; and based at least in part on the enable signal, provide one of the first data or the corrected first data at an output and provide second data at a second output”.
The specification also not make mention of “provide one of the first data or the corrected first data at an output and provide second data at a second output” anywhere in the disclosure. It is not exactly clear what these terms are referring to in the claim language. Interconnections between the first data or corrected first data and second data and further the outputs are confusing and for the most part not detailed or mentioned in the claim. It is difficult to translate the claim and follow what processes are taking place. Therefore, the claim lacks clarity.
Independent claims 6 and 11 are rejected for similar reasons. Respective dependent claim
are rejected at least based on dependency.
Dependent claims depend from the base claims and inherently include limitations therein and therefore are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph as well. Corrections are requested.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction
of the statutory basis for the rejection will not be considered a new ground of rejection if
the prior art relied upon, and the rationale supporting the rejection, would be the same
under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102 of this title, if the
differences between the claimed invention and the prior art are such that the claimed
invention as a whole would have been obvious before the effective filing date of the
claimed invention to a person having ordinary skill in the art to which the claimed
invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over
Nagai et al. (US 2005/0076274) in view of Minzoni (US 2018/0336959).
As per claims 1 and 11:
Nagai teaches substantially teaches or discloses an apparatus and a method comprising:
an error correction code (ECC) circuit configured to receive an enable signal; and perform an ECC operation on first data based at least in part on fuse data from one or more fuses to provide corrected first data; and based at least in part on the enable signal, provide one of the first data or the corrected first data at an output and provide second data at a second output (see paragraphs [0054], [0092-0093], [0103], and [0176-0178]). Although Nagai did not explicitly use the phrase "enable signal, the decoder ECC circuit of Nagai is allowed to function and respond to inputs such as enabling logic gates and further the circuit start or stop its operations, ensuring that it can respond to commands and control the behavior of the system. However, Nagai does not explicitly teach wherein the ECC circuit is configured to provide one of the first data or the corrected first data at an output based at least in part on the enable signal. Minzoni in an analogous art teaches wherein the ECC circuit is configured to provide one of the first data or the corrected first data at an output based at least in part on the enable signal (fig. 5, para. 72, when error correction is performed, the data (first data) and parity bits (second data) are read from the memory array; para. 74, the decoding enables signal enables the ECC error correction function, and data errors can be detected and corrected, para. 73, the decoding signal disables the ECC correction function, the ECC error correction function cannot be used).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Nagai's Patent Application Publication with the teachings of Minzoni by including providing one of the first data or the corrected first data based at least in part on the enable signal. This modification would have been obvious to one of ordinary skills in the art, before the effective filing date of the claimed invention because one of ordinary skill in the art would have recognized that it would provide predictable result of providing the opportunity to provide corrected data based on the error correction enable
signal.
As per claim 2: Nagai in combination with Minzoni teaches the limitations with respect
to claim 1. Furthermore, Nagai teaches a latch circuit comprising a plurality of latches
configured to selectively replace a group of defective memory cells based on the one of the first-
data or the corrected first data (see fig. 8, para. 103, the decoded and corrected data is latched by
latch circuits; para. 100, fuse elements store data for a remedy of a defection cell).
As per claim 3: Nagai in combination with Minzoni teaches the limitations with respect
to claim 1. Furthermore, Minzoni teaches that the ECC circuit includes ECC logic configured to
perform the ECC operation on the first data based on an ECC encoded in the fuse data (fig. 5,
para. 72, when error correction is performed, the data (first data) and parity bits (second data) are
read from the memory array, para. 74, the decoding enable signal enables the ECC error
correction function, and data errors can be detected and corrected).
As per claim 4: Nagai in combination with Minzoni teaches the limitations with respect
to claim 1. Furthermore, Nagai teaches a fuse array, wherein the first data is first fuse data, and
wherein the first fuse data and the fuse data are from the fuse array (para. 106, the data read from
the fuse elements).
As per claim 5: Nagai in combination with Minzoni teaches the limitations with respect
to claim 1. Furthermore, Minzoni teaches that the ECC circuit includes ECC logic configured to
perform the ECC operation on the first data based on an ECC encoded in the fuse data (fig. 5,
para. 72, when error correction is performed, the data (first data) and parity bits (second data) are
read from the memory array; para. 74, the decoding enable signal enables the ECC error
correction function, and data errors can be detected and corrected).
As per claim 17: Nagai in combination with Minzoni teaches the limitations with respect
to claim 11. Furthermore, Nagai teaches providing the first data as the corrected first data based
at least in part on the fuse data (fig. 8, para. 106, the data read from the fuse elements is decoded
by the error correction circuit through the transfer path) and (para. 107, the correct data can be
latched by utilizing the error correction function of the error correction circuit)
As per claim 18: Nagai in combination with Minzoni teaches the limitations with respect
to claim 11. Furthermore, Minzoni teaches the fuse data that is encoded with ECC data corresponding to expected data of the first data for the ECC operation (fig. 5, para. 72, when error correction is performed, the data (first data) and parity bits (second data) are read from the memory array; para. 74, the decoding enable signal enables the ECC error correction function, and data errors can be detected and corrected).
As per claim 19: Nagai in combination with Minzoni teaches the limitations with respect
to claim 11. Further, Nagai teaches enabling a respective replacement row or column of memory
cells based on the enable signal (see fig. 8, para. 103, the decoded and corrected data is latched
by latch circuits; para. 100, fuse elements store data for a remedy of a defection cell).
Furthermore, Minzoni teaches that the ECC circuit includes ECC logic configured to perform the
ECC operation on the first data based on an ECC encoded in the fuse data (fig. 5, para. 72, when
error correction is performed, the data (first data) and parity bits (second data) are read from the
memory array; para. 74, the decoding enable signal enables the ECC error correction function,
and data errors can be detected and corrected).
As per claim 20: Nagai in combination with Minzoni teaches the limitations with respect
to claim 11. Further, Nagai teaches disabling a respective defective row or column of memory
cells based on the enable signal (see fig. 8, para. 103, the decoded and corrected data is latched
by latch circuits; para. 100, fuse elements store data for a remedy of a defection cell).
Furthermore, Minzoni teaches that the ECC circuit includes ECC logic configured to perform the
ECC operation on the first data based on an ECC encoded in the fuse data (fig. 5, para. 72, when
error correction is performed, the data (first data) and parity bits (second data) are read from the
memory array; para. 74, the decoding enable signal enables the ECC error correction function,
and data errors can be detected and corrected).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nagai et al. "herein as Nagai" (US 2005/0076274) in view of Minzoni (US 2018/0336959) and further in view of Rahul et al. (US PN: 8,972,835).
As per claim 6:
Nagai teaches substantially teaches or discloses an apparatus comprising: an error correction code (ECC) circuit configured to receive an enable signal and based at least in part on the enable signal, provide one of the first data or the corrected first data at an output and provide second data at a second output (see paragraphs [0054], [0092-0093], [0103], and [0176-0178]). Although Nagai did not explicitly use the phrase "enable signal, the decoder ECC circuit of Nagai is allowed to function and respond to inputs such as enabling logic gates and further the circuit start or stop its operations, ensuring that it can respond to commands and control the behavior the system. However, Nagai does not explicitly teach wherein the ECC circuit is configured to provide one of the first data or the corrected first data at an output based at least in part on the enable signal. Minzoni in an analogous art teaches wherein the ECC circuit is configured to provide one of the first data or the corrected first data at an output based at least in part on the enable signal (fig. 5, para. 72, when error correction is performed, the data (first data) and parity bits (second data) are read from the memory array; para. 74, the decoding enables signal enables the ECC error correction function, and data errors can be detected and corrected, para. 73, the decoding signal disables the ECC correction function, the ECC error correction function cannot be used).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to modify Nagai's Patent Application Publication
with the teachings of Minzoni by including providing one of the first data or the corrected first
data at an output based at least in part on the enable signal. This modification would have been
obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention
because one of ordinary skill in the art would have recognized that it would provide predictable
result of providing the opportunity to provide.
However, Nagai and Minzoni do not explicitly teach wherein the ECC circuit includes
one or more multiplexers configured to provide the first data in response to the enable signal
having a first value and providing the corrected first data in response to the enable signal having
a second value, wherein the first value is indicative of a first stage of processing, and wherein the second value is indicative of a second stage of processing after the first stage of processing.
Rahul et al. in analogous art teaches that the ECC circuit includes one or more
multiplexers configured to provide the first data in response to the enable signal having a first
value and to provide the corrected first data in response to the enable signal having a second
value, (col. 18, lines 18-25, data out signal 2428 and parity out signal 2427 are provided to
decoder and corrector 2403, and data out signal 2428 and parity out signal 2427 are provided to
respective multiplexers to bypass decoder and corrector 2403. A bypass mode is used when
enable ECC read signal 2429 is logic low; however, when enable ECC read signal 2429 is logic
high, data, parity, and syndrome bits, output from decoder and corrector 2403, are used (for error
correction).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to modify Nagai's system in view of Minzoni with
the teachings of Rahul et al. by including the ECC circuit include one or more multiplexers
configured to provide the first data in response to the enable signal having a first value and to
provide the corrected first data in response to the enable signal having a second value. This
modification would have been obvious to one of ordinary skill in the art, before the effective
filing date of the claimed invention because one of ordinary skill in the art would have
recognized that it would provide predictable result of providing the opportunity to provide
corrected data based on the error correction enable signal.
Allowable subject matter
Claims 7-10 and 12-16 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten independent from including all of the limitation of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jeong (U.S. PN: 8553486) teaches that the ECC decoder 50 is configured to receive the first fuse data FD1 through FDn and the ECC data associated with the first data ECC1 through ECCm, and generate second fuse data CFD1 through CFDn, as essentially an ECC corrected version of the first fuse data FD1 trough FDn using the ECC data ECC1 through ECCm. During a power-up operation for the semiconductor memory device, the ECC decoder 50 may thus be used to generate error-free second fuse data CFD1 through CFDn by correcting any errors present in the stored first fuse data FD1 through FDn (see col. 4, lines 9-23).
Nakaigawa (U.S. PN: 8,255,178) in FIG. 5 shows a block diagram of a semiconductor memory device disclosed by Sato. As shown in FIG. 5, the semiconductor memory device disclosed by Sato includes a ROM circuit 301, a defective address storage circuit 302, a fuse data holding circuit 303, a relief determination circuit 304, an ECC circuit 305, a data holding circuit 306, an address matching circuit 107, a switching holding circuit 308, and a switching circuit 309. The ROM circuit 301 includes a memory data 301a that holds necessary memory data, and a parity data area 301b that stores parity data for correcting an error of the memory data. The defective address storage circuit 302 stores a defective address which is an address of memory data determined as an error among memory data stored in the memory data area 301a. The fuse data holding circuit 303 holds fuse data output from the defective address storage circuit 302. The relief determination circuit 304 determines whether memory data determined as defective data is present or not, that is, whether it is necessary to relieve the data, based on the fuse data output from the fuse data holding circuit 303. The ECC circuit 305 corrects the memory data, which is determined as an error, based on parity data, and generates relief data corresponding to the defective address (see col. 2, lines 6-29).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESAW T ABRAHAM whose telephone number is (571)272-3812. The examiner can normally be reached on 8AM-4:30PM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112
