DETAILED ACTION
This action is responsive to the Applicant's amendments filed on 02/06/2026. Claims 1-20 remain pending in the application. No claims have been amended.
Response to Amendment
Specification objections is withdrawn in light of amendments/remarks.
Rejections under double patenting is maintained (see previous Non-final action filed on 11/10/2025).
Response to Arguments
Applicant's arguments filed 02/06/2026 have been fully considered but they are not
persuasive. Applicant's arguments are summarized below:
Nagai and/or Minzoni fail to teach, disclose, or suggest each and every limitation of independent claim 1 and thus do not support an obviousness rejection of independent claim 1.
Nagai, Minzoni, and/or Rahul fail to teach, disclose, or suggest each and every limitation of independent claim 6 and thus do not support an obviousness rejection of independent claim 6.
The Examiner respectfully disagrees.
With regard to claims independent claims 1 and 11, Nagai in paragraph [0054] teaches a decoder, or both an encoder and a decoder used to suppress generation of erroneous data are connected to the transfer path from the fuse circuit to an internal circuit requiring fuse data (e.g., an option setting circuit which determines operation characteristics of any other internal circuit). Further, Nagai in paragraph [0178] describes the decoder/error correction circuit 11A outputs an error detection signal SYN when an n-bit error exists. Upon receiving the error detection signal SYN, a latch data refresh control circuit 17 outputs a selection signal SEL, and controls a selection circuit 16 so as to select an output signal from the decoder error correction circuit 11A. Although, Nagai did not explicitly use the phrase “enable signal, the decoder ECC circuit of Nagai is allowed to function and respond to inputs such as enabling logic gates and further the circuit start or stop its operations, ensuring that it can respond to commands and control the behavior the system. However, Minzoni, in analogous art, in paragraph [0066] explicitly teaches N-bit data is sent from the first sense amplifier to the second sense amplifier and then sent to the ECC encoder via the data latch, and the encoding enable signal enables the ECC encoder to produce M-bit ECC parity bits for the data, which parity bits will be written into the ECC array and further in paragraphs [0072]-[0074] teaches if the value of the flag bit is in initial state, such as ‘0’, then the decoding enable signal disenables the ECC error correction function, meaning that the ECC error correction function cannot be used. If the value of the flag bit is not in initial state, such as ‘1’, then the decoding enable signal enables the ECC error correction function, and data errors can be detected and corrected as the ECC error correction function is normal. Therefore, contrary to Applicant's arguments, the clams are likewise remains rejected and the rejections of the claims 1 and 11 under 35 U.S.C. 103 are maintained.
With regard to claim 6, the combination of Nagai and Minzoni do not explicitly teach the ECC circuit includes one or more multiplexers to provide the data in response to the enable signal. However, Rahul in clearly describes that data out signal 2428 and parity out signal 2427 are provided to decoder and corrector 2403, and data out signal 2428 and parity out signal 2427 are provided to respective multiplexers to bypass decoder and corrector 2403. Thus, the combination is deemed still proper and the rejection of the claim 6 under 35 U.S.C. 103 is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102 of this title, if the
differences between the claimed invention and the prior art are such that the claimed
invention as a whole would have been obvious before the effective filing date of the
claimed invention to a person having ordinary skill in the art to which the claimed
invention pertains. Patentability shall not be negated by the manner in which the
invention was made.
Claims 1-5, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nagai et al. "herein as Nagai" (US 2005/0076274) in view of Minzoni (US 2018/0336959).
As per claims 1 and 11:
Nagai teaches substantially teaches or discloses an apparatus and a method comprising:
an error correction code (ECC) circuit configured to receive an enable signal and perform an ECC operation on first data based at least in part on fuse data from one or more fuses to provide corrected first data (see paragraphs [0054], [0092-0093], [0103], and [0176-0178]). Although, Nagai did not explicitly use the phrase “enable signal, the decoder ECC circuit of Nagai is allowed to function and respond to inputs such as enabling logic gates and further the circuit start or stop its operations, ensuring that it can respond to commands and control the behavior the system. However, Nagai does not explicitly teach wherein the ECC circuit is configured to provide one of the first data or the corrected first data at an output based at least in part on the enable signal. Minzoni in an analogous art teaches wherein the ECC circuit is configured to provide one of the first data or the corrected first data at an output based at least in part on the enable signal (fig. 5, para. 72, when error correction is performed, the data (first data) and parity bits (second data) are read from the memory array; para. 74, the decoding enable signal enables the ECC error correction function, and data errors can be detected and corrected; para. 73, the decoding signal disables the ECC correction function, the ECC error correction function cannot be used).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to modify Nagai's Patent Application Publication with the teachings of Minzoni by including that provide one of the first data or the corrected first data at an output based at least in part on the enable signal. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention because one of ordinary skill in the art would have recognized that it would provide predictable result of providing the opportunity to provide corrected data based on the error correction enable
signal.
As per claim 2: Nagai in combination with Minzoni teaches the limitations with respect
to claim 1. Furthermore, Nagai teaches a latch circuit comprising a plurality of latches
configured to selectively replace a group of defective memory cells based on the one of the first- data or the corrected first data (see fig. 8, para. 103, the decoded and corrected data is latched by latch circuits; para. 100, fuse elements store data for a remedy of a defection cell).
As per claim 3: Nagai in combination with Minzoni teaches the limitations with respect
to claim 1. Furthermore, Minzoni teaches that the ECC circuit includes ECC logic configured to perform the ECC operation on the first data based on an ECC encoded in the fuse data (fig. 5, para. 72, when error correction is performed, the data (first data) and parity bits (second data) are read from the memory array; para. 74, the decoding enable signal enables the ECC error correction function, and data errors can be detected and corrected).
As per claim 4: Nagai in combination with Minzoni teaches the limitations with respect
to claim 1. Furthermore, Nagai teaches a fuse array, wherein the first data is first fuse data, and wherein the first fuse data and the fuse data are from the fuse array (para. 106, the data read from the fuse elements).
As per claim 5: Nagai in combination with Minzoni teaches the limitations with respect to claim 1. Furthermore, Minzoni teaches that the ECC circuit includes ECC logic configured to perform the ECC operation on the first data based on an ECC encoded in the fuse data (fig. 5, para. 72, when error correction is performed, the data (first data) and parity bits (second data) are read from the memory array; para. 74, the decoding enable signal enables the ECC error correction function, and data errors can be detected and corrected).
As per claim 17: Nagai in combination with Minzoni teaches the limitations with respect
to claim 11. Furthermore, Nagai teaches providing the first data as the corrected first data based at least in part on the fuse data (fig. 8, para. 106, the data read from the fuse elements is decoded by the error correction circuit through the transfer path) and (para. 107, the correct data can be latched by utilizing the error correction function of the error correction circuit)
As per claim 18: Nagai in combination with Minzoni teaches the limitations with respect
to claim 11. Furthermore, Minzoni teaches the fuse data is encoded with ECC data corresponding to expected data of the first data for the ECC operation (fig. 5, para. 72, when error correction is performed, the data (first data) and parity bits (second data) are read from the memory array; para. 74, the decoding enable signal enables the ECC error correction function, and data errors can be detected and corrected).
As per claim 19: Nagai in combination with Minzoni teaches the limitations with respect
to claim 11. Further, Nagai teaches enabling a respective replacement row or column of memory cells based on the enable signal (see fig. 8, para. 103, the decoded and corrected data is latched by latch circuits; para. 100, fuse elements store data for a remedy of a defection cell). Furthermore, Minzoni teaches that the ECC circuit includes ECC logic configured to perform the ECC operation on the first data based on an ECC encoded in the fuse data (fig. 5, para. 72, when error correction is performed, the data (first data) and parity bits (second data) are read from the memory array; para. 74, the decoding enable signal enables the ECC error correction function, and data errors can be detected and corrected).
As per claim 20: Nagai in combination with Minzoni teaches the limitations with respect
to claim 11. Further, Nagai teaches disabling a respective defective row or column of memory cells based on the enable signal (see fig. 8, para. 103, the decoded and corrected data is latched by latch circuits; para. 100, fuse elements store data for a remedy of a defection cell). Furthermore, Minzoni teaches that the ECC circuit includes ECC logic configured to perform the ECC operation on the first data based on an ECC encoded in the fuse data (fig. 5, para. 72, when error correction is performed, the data (first data) and parity bits (second data) are read from the memory array; para. 74, the decoding enable signal enables the ECC error correction function, and data errors can be detected and corrected).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nagai et al. "herein as Nagai" (US 2005/0076274) in view of Minzoni (US 2018/0336959) and further in view of Rahul et al. (US PN: 8,972,835).
As per claim 6:
Nagai teaches substantially teaches or discloses an apparatus comprising: an error
correction code (ECC) circuit configured to receive an enable signal and perform an ECC
operation on first data based at least in part on fuse data from one or more fuses to provide
corrected first data (see paragraphs [0054], [0092-0093], [0103], and [0176-0178]). Although, Nagai did not explicitly use the phrase “enable signal, the decoder ECC circuit of Nagai is allowed to function and respond to inputs such as enabling logic gates and further the circuit start or stop its operations, ensuring that it can respond to commands and control the behavior the system. However, Nagai does not explicitly teach wherein the ECC circuit is configured to
provide one of the first data or the corrected first data at an output based at least in part on the enable signal. Minzoni in an analogous art teaches wherein the ECC circuit is configured to provide one of the first data or the corrected first data at an output based at least in part on the enable signal (fig. 5, para. 72, when error correction is performed, the data (first data) and parity bits (second data) are read from the memory array; para. 74, the decoding enable signal enables the ECC error correction function, and data errors can be detected and corrected; para. 73, the decoding signal disables the ECC correction function, the ECC error correction function cannot be used).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to modify Nagai's Patent Application Publication with the teachings of Minzoni by including that provide one of the first data or the corrected first data at an output based at least in part on the enable signal. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention because one of ordinary skill in the art would have recognized that it would provide predictable result of providing the opportunity to provide.
However, Nagai and Minzoni do not explicitly teach wherein the ECC circuit includes
one or more multiplexers configured to provide the first data in response to the enable signal having a first value and to provide the corrected first data in response to the enable signal having a second value, wherein the first value is indicative of a first stage of processing, and wherein the second value is indicative of a second stage of processing after the first stage of processing.
Rahul et al. in an analogous art teach that the ECC circuit includes one or more
multiplexers configured to provide the first data in response to the enable signal having a first value and to provide the corrected first data in response to the enable signal having a second value, (col. 18, lines 18-25, data out signal 2428 and parity out signal 2427 are provided to decoder and corrector 2403, and data out signal 2428 and parity out signal 2427 are provided to respective multiplexers to bypass decoder and corrector 2403. A bypass mode is used when enable ECC read signal 2429 is logic low; however, when enable ECC read signal 2429 is logic high, data, parity, and syndrome bits, output from decoder and corrector 2403, are used (for error correction).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to modify Nagai's system in view of Minzoni with the teachings of Rahul et al. by including the ECC circuit includes one or more multiplexers configured to provide the first data in response to the enable signal having a first value and to provide the corrected first data in response to the enable signal having a second value. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention because one of ordinary skill in the art would have recognized that it would provide predictable result of providing the opportunity to provide corrected data based on the error correction enable signal.
Allowable subject matter
Claims 7-10 and 12-16 are objected to as being dependent upon a rejected base claim
but would be allowable if rewritten independent from including all of the limitation of the
base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESAW T ABRAHAM whose telephone number is (571)272-3812. The examiner can normally be reached on 8AM-4:30PM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phonenumber for the organization where this application or proceeding is assigned is(703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112