DETAILED ACTION
This communication is in response to the Request for Continued Examination (RCE) and Amendment filed on February 05, 2026 in which claims 1-2, 4-13 and 19-25 are pending in the application. Claims 1, 10 and 19 are in independent form. Claims 3, 14-18 have been cancelled.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 5, 2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
This Non-Final Office Action is in response to the applicant’s remarks and arguments filed on February 05, 2026.
Claims 3 was canceled and claims 14-18 were previously canceled. Claims 1, 10 and 19 were amended. Claims 21-25 were previously added.
Claims 1-2, 4-13 and 19-25 remain pending in the application. Claims 1-2, 4-13 and 19-25 are being considered on the merits.
Response to Arguments
The applicant’s remarks and/or arguments, filed on February 5, 2026 have been fully considered with the following result(s).
The examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification. See MPEP 2111 [R-1] Interpretation of Claims-Broadest Reasonable Interpretation. The applicant always has the opportunity to amend the claims during prosecution, and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Prater, 162 USPQ 541,550-51 (CCPA 1969).
Regarding claims 1, 10 and 19, Applicant argues that the proposed combination of Vrudhula and Garofalo does not disclose thehighlighted claim features of claim 1 as amended.
A. Vrudhula fails to disclose the whole solution disclosed by the above claim
features as recited claim 1 as amended.
Regarding the rejection of claim(s) 1-2, 4-6, 10-11 and 15-25 under 35 USC 103, Applicant's arguments and remarks filed on February 5, 2026, have been fully considered and they are found persuasive. Therefore, the previous claim(s) rejection under 35 U.S.C 103 has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of a newly found prior art Dasalukunte (US 20210150328 A1):
Dasalukunte discloses the array of computing-in-memory cells perform, based on an analog circuit, a computation on received data to obtain first analog data [Para [0019]-[0021], Fig. 1, 2A-2D: Each supertile/tile has analog CIM cells performing computations];
wherein the peripheral analog circuit comprises an analog-to-digital converter, coupled to the array of computing-in-memory cells and configured to convert the first analog data into first digital data [Para [0019]-[0024]: Analog router (ADC), [0021]: Each tile has analog and digital; [0023]: ADC in analog router];
an interface module, configured to communicatively couple the first chip and the second chip, and configured to transfer data between the first chip and the second chip by using an analog signal, the analog signal comprising the first analog data [Para [0019]-[0025], [0028]-[0033]: Analog router transmits analog signals between tiles/supertile; bus connects supertiles].
As such, the combination of references discloses the claimed invention. For further details, please see claims rejections under 35 USC 103 below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-6, 10-11, and 19-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vrudhula et al. (US PGPub 2023/0385624 A1) and Dasalukunte (US 20210150328 A1).
As per claim 1, Vrudhula discloses a computing-in-memory system, comprising:
a first chip, comprising an array of computing-in-memory cells, wherein the array of computing-in-memory cells is configured to perform a computation on received data [Fig. 8C, element 810, NPEs; Para 0112];
a second chip, comprising a peripheral analog circuit and a digital circuit [Fig. 8C; element 815, DA and Simpli-V; Para 0112];
Vrudhula discloses a Logic Layer comprising Simply-V that performs floating operations and DA to act as a digital-to-analog converter [Fig. 8C].
However, the reference does not specifically teach “the array of computing-in-memory cells perform, based on an analog circuit, a computation on received data to obtain first analog data; wherein the peripheral analog circuit comprises an analog-to-digital converter, coupled to the array of computing-in-memory cells and configured to convert the first analog data into first digital data; an interface module configured to communicatively couple the first chip and the second chip, and configured to transfer data between the first chip and the second chip by using an analog signal, the analog signal comprising the first analog data.
Dasalukunte discloses the array of computing-in-memory cells perform, based on an analog circuit, a computation on received data to obtain first analog data [Para [0019]-[0021], Fig. 1, 2A-2D: Each supertile/tile has analog CIM cells performing computations];
wherein the peripheral analog circuit comprises an analog-to-digital converter, coupled to the array of computing-in-memory cells and configured to convert the first analog data into first digital data [Para [0019]-[0024]: Analog router (ADC), [0021]: Each tile has analog and digital; [0023]: ADC in analog router];
an interface module, configured to communicatively couple the first chip and the second chip, and configured to transfer data between the first chip and the second chip by using an analog signal, the analog signal comprising the first analog data [Para [0019]-[0025], [0028]-[0033]: Analog router transmits analog signals between tiles/supertile; bus connects supertiles].
Both Vrudhula and Dasalukunte are in the same field of endeavor and they are both in the in-memory computing art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Vrudhula with the teachings of Dasalukunte in order to overcome the well-known memory bottleneck affecting traditional AI digital accelerators.
Modification would improve system performance by reducing the amount of time and/or energy required to perform analog-to-digital conversions and digital-to-analog conversions and improves the time and amount of resources required to train neural networks and/or perform inference operations using the neural networks as taught by Dasalukunte (Para 0013).
As per claim 2, Vrudhula discloses the computing-in-memory system according to claim 1, wherein the interface module comprises a through-silicon via (TSV) structure [Fig. 8C, TSV 850; Para 0112].
As per claim 4, Vrudhula discloses the computing-in-memory system according to claim 1, wherein the peripheral analog circuit comprises at least two modules [Figs 8A-8C; Para 0070-0071], and
the second chip comprises one or more first sub-chips, the at least two modules of the peripheral analog circuit are integrated with the one or more first subchips [Figs 8A-8C; Para 0062, 0070-0071].
Dasalukunte also discloses the above limitation [[0021], [0023], [0024]: Analog router has ADC, DAC, Gaussian logic, etc.].
As per claim 5, Vrudhula discloses the computing-in-memory system according to claim 1, wherein the digital circuit comprises one or more of:
a post-processing operation circuit configured to perform a post-processing operation on first digital data obtained by the analog-to-digital conversion on the first analog data [Para 0071];
a random-access memory (RAM) [Figs 8A-8C; Para 0054-0056];
a central processing unit (CPU) [Figs 8A-8C; Para 0054-0056];
a graphics processing unit (GPU); and
a peripheral interface module [Figs 8A-8c; Para 0054-0056].
Dasalukunte also discloses the above first limitation [[0021], [0047]-[0055]: Each tile has processing circuitry (processor, memory); system includes CPU, GPU, ML accelerator, RAM, I/O].
As per claim 6, Vrudhula discloses the computing-in-memory system according to claim 1, wherein the digital circuit comprises at least two modules [Figs 8A-8C; Para 0070-0073], and
the second chip comprises one or more second sub-chips, the at least two modules of the digital circuit are integrated with the one or more second sub-chips [Figs 8A-8C; Para 0062, 0067].
Dasalukunte also discloses the above limitation [[0021], [0047]-[0055]: Modular digital logic].
As per claim 10, Vrudhula discloses a method comprising:
integrating an array of computing-in-memory cells on a first chip, wherein the array of computing-in-memory cells is configured to perform, a computation on received data [Fig. 8C, element 810, NPEs; Para 0112];
integrating a peripheral analog circuit and a digital circuit on a second chip [Fig. 8C; element 815, DA and Simpli-V; Para 0112]; and
packaging the first chip, the second chip, and an interface module, wherein the interface module communicatively couples the first chip and the second chip, and is configured to transfer data between the first chip and the second chip [Fig. 8C; element 850; Para 0112].
Vrudhula discloses a Logic Layer comprising Simply-V that performs floating operations and DA to act as a digital-to-analog converter [Fig. 8C].
However, the reference does not specifically teach “the array of computing-in-memory cells perform, based on an analog circuit, a computation on received data to obtain first analog data;” wherein the peripheral analog circuit comprises an analog-to-digital converter, coupled to the array of computing-in-memory cells and configured to convert the first analog data into first digital data; and “transfer data by using an analog signal, the analog signal comprising the first analog data”.
Dasalukunte discloses the array of computing-in-memory cells perform, based on an analog circuit, a computation on received data to obtain first analog data [Para [0019]-[0021], Fig. 1, 2A-2D: Each supertile/tile has analog CIM cells performing computations];
wherein the peripheral analog circuit comprises an analog-to-digital converter, coupled to the array of computing-in-memory cells and configured to convert the first analog data into first digital data [Para [0019]-[0024]: Analog router (ADC), [0021]: Each tile has analog and digital; [0023]: ADC in analog router];
an interface module communicatively couples the first chip and the second chip, and is configured to transfer data between the first chip and the second chip by using an analog signal, the analog signal comprising the first analog data [Para [0019]-[0025], [0028]-[0033]: Analog router transmits analog signals between tiles/supertile; bus connects supertiles].
Both Vrudhula and Dasalukunte are in the same field of endeavor and they are both in the in-memory computing art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Vrudhula with the teachings of Dasalukunte in order to overcome the well-known memory bottleneck affecting traditional AI digital accelerators.
Modification would improve system performance by reducing the amount of time and/or energy required to perform analog-to-digital conversions and digital-to-analog conversions and improves the time and amount of resources required to train neural networks and/or perform inference operations using the neural networks as taught by Dasalukunte (Para 0013).
As per claim 11, Vrudhula discloses the method according to claim 10, wherein the interface module comprises a through- silicon via (TSV) [Fig. 8C, TSV 850; Para 0112].
As per claim 19, Vrudhula discloses an apparatus comprising a computing-in-memory system which comprises:
a first chip, comprising an array of computing-in-memory cells, wherein the array of computing-in-memory cells is configured to perform a computation on received data [Fig. 8C, element 810, NPEs; Para 0112];
a second chip comprising a peripheral analog circuit and a digital circuit [Fig. 8C; element 815, DA and Simpli-V; Para 0112];
an interface module, configured to communicatively couple the first chip, the second chip, and configured to transfer data between the first chip and the second chip [Fig. 8C; element 850; Para 0112].
Vrudhula discloses a Logic Layer comprising Simply-V that performs floating operations and DA to act as a digital-to-analog converter [Fig. 8C].
However, the reference does not specifically teach “the array of computing-in-memory cells is configured to perform a computation on received data to obtain first analog data; wherein the peripheral analog circuit comprises an analog-to-digital converter, coupled to the array of computing-in-memory cells and configured to convert the first analog data into first digital data; and transfer data by using an analog signal, the analog signal comprising the first analog data”.
Dasalukunte discloses the array of computing-in-memory cells perform, based on an analog circuit, a computation on received data to obtain first analog data [Para [0019]-[0021], Fig. 1, 2A-2D: Each supertile/tile has analog CIM cells performing computations];
wherein the peripheral analog circuit comprises an analog-to-digital converter, coupled to the array of computing-in-memory cells and configured to convert the first analog data into first digital data [Para [0019]-[0024]: Analog router (ADC), [0021]: Each tile has analog and digital; [0023]: ADC in analog router];
an interface module communicatively couples the first chip and the second chip, and is configured to transfer data between the first chip and the second chip by using an analog signal, the analog signal comprising the first analog data [Para [0019]-[0025], [0028]-[0033]: Analog router transmits analog signals between tiles/supertile; bus connects supertiles].
Both Vrudhula and Dasalukunte are in the same field of endeavor and they are both in the in-memory computing art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Vrudhula with the teachings of Dasalukunte in order to overcome the well-known memory bottleneck affecting traditional AI digital accelerators.
Modification would improve system performance by reducing the amount of time and/or energy required to perform analog-to-digital conversions and digital-to-analog conversions and improves the time and amount of resources required to train neural networks and/or perform inference operations using the neural networks as taught by Dasalukunte (Para 0013).
As per claim 20, Vrudhula discloses the apparatus according to claim 19, wherein the interface module comprises a through-silicon via (TSV) structure [Fig. 8C, TSV 850; Para 0112].
As per claim 21, Vrudhula discloses the computing-in-memeory system according to claim 1, further comprising:
a dynamic random-access memory (DRAM), where the interface module is further configured to communicatively couple the DRAM, and configured to transfer data stored in the DRAM to the first chip or the second chip [Fig. 8C; DRAM layer; chip above element 815; element 850; Para 0112].
As per claim 22, Vrudhula discloses the computing-in-memory system according to claim 21, wherein the DRAM is integrated to a third chip, that is positioned between the first chip and the second chip [Fig. 8C; DRAM layer; chip above element 815; element 850; Para 0112].
As per claim 23, Vrudhula discloses the computing-in-memory according to claim 1, wherein the peripheral analog circuit comprises:
a digital-to-analog converter, coupled to the array of computing-in-memory cells and configured to convert second digital data to be input to the array of computing-in-memory cells into second analog data [Fig. 8C, DA; Para 0071, analog to digital converter (ADC)];
wherein the analog signal transferred by the interface module further comprises the second analog data [[Fig. 8C, DA; Para 0071, analog to digital converter (ADC)].
Dasalukunte also discloses the above limitation [Para [0021], [0023]: DAC in analog router, used for digital-to-analog conversion]; and
wherein the analog signal transferred by the interface module further comprises the second analog data [Para [0021], [0023]: DAC in analog router, used for digital-to-analog conversion)];
As per claim 24, Vrudhula discloses the computing-in-memory system according to claim 23, wherein the peripheral analog circuit further comprises one or more of:
a programming circuit, coupled to the array of computing-in-memory cells and configured to perform data programming on the array of computing-in-memory cells [Para 0062];
a phase-locked loop; and
an oscillator.
As per claim 25, Vrudhula discloses the method according to claim 10, wherein packaging the first chip, the second chip, and an interface module comprises:
packaging the first chip, the second chip, an interface module, and a dynamic random access memory (DRAM), wherein the interface module is further configured to communicatively couple the DRAM, and configured to transfer data stored in the DRAM to the first chip or the second chip [Fig. 8C; DRAM layer; chip above element 815; element 850; Para 0112]..
Claim(s) 7 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vrudhula et al. (US PGPub 2023/0385624 A1) and Dasalukunte (US 20210150328 A1) and Wu et al. (US PGPub 2024/0071829 A1).
As per claim 7 and 12, the claims recite the computing-in-memory system according to claim 1, wherein the array of computing-in-memory cells is integrated on the first chip through a first process node, the peripheral analog circuit and the digital circuit are integrated on the second chip through a second process node different from the first process node.
Vrudhula and Dasalukunte disclose the computing-in-memory cells arrays, the peripheral circuits and the DRAM integrated on different chips of the claimed invention as detailed above. Vrudhula and Dasalukunte do not explicitly teach a first process node different from the second process node as required by the claims.
Wu teaches an integrated circuit with several chips using different process nodes [Para 0002, the semiconductor industry has progressed into nanometer technology process nodes; Para 0021, A first gate cutting structure in the logic region is greater than a second gate cutting structure in the memory cell array region; Para 0023, Although the logic region 50A and the memory cell array region 50B are shown as being immediately adjacent to one another in FIG. 1, the logic region 50A and the memory cell array region 50B may be spaced apart from one another by another device region].
It is to be noted that process node is defined as the measure of the size of a chip’s transistors and other components and is often specified in terms of a minimum metal or feature pitch, conductor line width [See Spec. Para 0023].
Both Vrudhula and Dasalukunte and Wu are in the same field of endeavor and they are both in the memory industry nanometer technology art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date of the claimed invention was made to modify the teachings of Vrudhula and Dasalukunte with the teachings of Wu in order to provide different chips containing different elements with different process nodes in an integrated circuit.
Motivation would improve the performance, e.g., speed of the logic devices while
improving the density of the memory devices and provide process nodes in pursuit of higher
device density, higher performance, and lower costs as taught by Wu (Para 0002, 00021].
Claim(s) 8 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vrudhula et al. (US PGPub 2023/0385624 A1) and Dasalukunte (US 20210150328 A1) and Wu et al. US PGPub 2024/0071829 A1 and further in view of “Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth”, Hung et al., 2023.
As per claims 8 and 13, Vrudhula and Dasalukunte and Wu disclose the claimed invention as detailed above. Although Wu discloses using different gate structure widths [Para 0021]. Wu does not specifically teach a line width of the second process node is less than that of the first process node.
Hung discloses a line width of the second process node is less than that of the first process node [Section 1, second Para; Fig. 6].
Vrudhula, and Dasalukunte and Wu and Hung are in the same field of endeavor and they are both in the memory industry nanometer technology art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date of the claimed invention was made to modify the teachings of Vrudhula and Dasalukunte and Wu with the teachings of Hung in order to provide different chips containing different elements with different process nodes in an integrated circuit.
Motivation would improve the performance, e.g., speed of the logic devices while
improving the density of the memory devices and provide process nodes in pursuit of higher
device density, higher performance, and lower costs as taught by Wu (Para 0002, 00021] and
high bandwidth as taught by Hung [Section1, Para 3].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vrudhula et al. (US PGPub 2023/0385624 A1) and Dasalukunte (US 20210150328 A1) and “Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth”, Hung et al., 2023.
As per claim 9, the claim recites the computing-in-memory system according to claim 1, wherein the array of computing-in-memory cells, the peripheral analog circuit and the digital circuit are integrated, through a same process node, on the first chip and the second chip, respectively.
Vrudhula and Dasalukunte disclose the claimed invention as detailed above. Vrudhula and Garofalo do not specifically teach using a same process node to integrate the computing-in-memory cells arrays, the peripheral circuits and the DRAM on the chips.
Hung teaches using a same process node to integrate the computing-in-memory cells arrays, the peripheral circuits and the DRAM on the chips [Section 1, Para 2, Para 3; Section 2.1, Para 1, the Cu grains in the model are all designed with similar size; Para 2].
Both Vrudhula and Dasalukunte and Hung are in the same field of endeavor and they are both in the memory industry nanometer technology art and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective
filing date of the claimed invention was made to modify the teachings of Vrudhula and Dasalukunte with the teachings of Hung in order to provide different chips containing different elements with same process nodes in an integrated circuit.
Motivation would improve the performance of devices and the communication distance
between devices could be reduced and the devices could be integrated within a small form factor
and providing high bandwidth as taught by Hung [Section1, Para 1, 3].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a) Hoang et al. (US 20210397931 A1) discloses In an embodiment as a bonded die pair, as represented in FIGS. 6A and 6B, the memory arrays 1201, 1203, and 1205 could be part of the array structure 326 formed on the memory die 610 and the other elements of FIG. 12 (the ADCs, DACs, and other peripheral/control circuits) could be part of the control die 608. (Para 0081).
b) Zhou (US 11669443 B2) discloses PIM block 100 may further include a row sense amplifier 141 or a column sense amplifier 142 for read out data from a memory cell or for storing the data into a memory cell. In some embodiments, row sense amplifier 141 and column sense amplifier 142 may store data for buffering. In some embodiments, PIM block 100 can further include DAC 151 (digital-to-analog converter) or ADC 152 (analog-to-digital converter) to convert input signal or output data between analog domain and digital domain (Col. 4, lines 21-29).
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Pierre M. Vital whose telephone number is (571)272-4215. The examiner can normally be reached Mon-Fri, 8:00a-4:00p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dede Zecher can be reached at (571) 272-7771. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
June 24, 2026
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2162
Prosecution Insights