DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 – 20 have been considered but are moot because the new ground of rejection presented below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 9 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2, 4 – 9, 23, and 24 of copending Application No. 18/766,448 in view of US Patent Application Publication No. 2021/0050853 (hereinafter Camarota).
The claims of the copending application require all the limitations of the claims of the instant application, except the limitation “a plurality of first chips, each including one or more arrays of computing-in-memory cells and arranged to overlap each other” required by claim 1 of the instant application. The claims of the copending application do not require a plurality of first chips and that they are arranged to overlap each other.
However, Camarota teaches a computing-in-memory system which includes a plurality of first chips (Camarota; Figure 1 Items 106, Figure 2 Items 206) arranged to overlap each other (Camarota; Figure 1 Items 106, Figure 2 Items 206, Paragraph [0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the requirements of the claims of the copending application to include the plurality of first chips arranged to overlap each other because doing so is a known technique in chip fabrication.
The of the instant application are mapped to the claims of copending application 18/766,448 as follows:
Instant App
18/766,448
1
1, 23, 24
2
2
3
23, 24
4
4
5
5
6
6
7
7
8
8
9
9
This is a provisional nonstatutory double patenting rejection.
Claims 1 – 18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 18 of copending Application No. 18/770,332 in view of US Patent Application Publication No. 2021/0050853 (hereinafter Camarota).
The claims of the copending application require all the limitations of the claims of the instant application, except the limitation “a plurality of first chips, each including one or more arrays of computing-in-memory cells and arranged to overlap each other” required by claims 1 and 10 of the instant application. The claims of the copending application do not require the plurality of first chips are arranged to overlap each other.
However, Camarota teaches a computing-in-memory system which includes a plurality of first chips (Camarota; Figure 1 Items 106, Figure 2 Items 206) arranged to overlap each other (Camarota; Figure 1 Items 106, Figure 2 Items 206, Paragraph [0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the requirements of the claims of the copending application to include the plurality of first chips arranged to overlap each other because doing so is a known technique in chip fabrication.
The of the instant application are mapped to the claims of copending application 18/770,332 as follows:
Instant App
18/770,332
1
1, 3
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10, 15
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
This is a provisional nonstatutory double patenting rejection.
Claims 1 – 17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3 – 11, and 13 – 19 of copending Application No. 18/770,445 in view of US Patent Application Publication No. 2021/0050853 (hereinafter Camarota).
The claims of the copending application require all the limitations of the claims of the instant application, except the limitation “a plurality of first chips, each including one or more arrays of computing-in-memory cells and arranged to overlap each other” required by claims 1 and 10 of the instant application. The claims of the copending application do not require the plurality of first chips are arranged to overlap each other.
However, Camarota teaches a computing-in-memory system which includes a plurality of first chips (Camarota; Figure 1 Items 106, Figure 2 Items 206) arranged to overlap each other (Camarota; Figure 1 Items 106, Figure 2 Items 206, Paragraph [0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the requirements of the claims of the copending application to include the plurality of first chips arranged to overlap each other because doing so is a known technique in chip fabrication.
The of the instant application are mapped to the claims of copending application 18/770,445 as follows:
Instant App
18/770,445
1
1, 4
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11, 17
11
13
12
14
13
15
14
16
15
17
16
18
17
19
This is a provisional nonstatutory double patenting rejection.
Claims 1 – 3, 5, 7 – 15, and 17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4 – 10, and 13 – 18 of copending Application No. 18/786,329 in view of US Patent Application Publication No. 2021/0050853 (hereinafter Camarota).
The claims of the copending application require all the limitations of the claims of the instant application, except the limitation “a plurality of first chips, each including one or more arrays of computing-in-memory cells and arranged to overlap each other” required by claims 1 and 10 of the instant application. The claims of the copending application do not require the plurality of first chips are arranged to overlap each other.
However, Camarota teaches a computing-in-memory system which includes a plurality of first chips (Camarota; Figure 1 Items 106, Figure 2 Items 206) arranged to overlap each other (Camarota; Figure 1 Items 106, Figure 2 Items 206, Paragraph [0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the requirements of the claims of the copending application to include the plurality of first chips arranged to overlap each other because doing so is a known technique in chip fabrication.
The of the instant application are mapped to the claims of copending application 18/786,392 as follows:
Instant App
18/786,392
1
1, 5
2
4
3
5
5
6
7
7
8
8
9
9
10
10, 17
11
13
12
14
13
15
14
16
15
17
17
18
This is a provisional nonstatutory double patenting rejection.
Claims 1 – 18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 18 of copending Application No. 18/786,388 in view of US Patent Application Publication No. 2021/0050853 (hereinafter Camarota).
The claims of the copending application require all the limitations of the claims of the instant application, except the limitation “a plurality of first chips, each including one or more arrays of computing-in-memory cells and arranged to overlap each other” required by claims 1 and 10 of the instant application. The claims of the copending application do not require the plurality of first chips are arranged to overlap each other.
However, Camarota teaches a computing-in-memory system which includes a plurality of first chips (Camarota; Figure 1 Items 106, Figure 2 Items 206) arranged to overlap each other (Camarota; Figure 1 Items 106, Figure 2 Items 206, Paragraph [0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the requirements of the claims of the copending application to include the plurality of first chips arranged to overlap each other because doing so is a known technique in chip fabrication.
The of the instant application are mapped to the claims of copending application 18/786,388 as follows:
Instant App
18/786,388
1
1, 3
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10, 15
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 8, 10 – 13, and 15 – 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 2021/0050853 (hereinafter Camarota) in view of US Patent No. 12,086,461 (hereinafter Sun).
As per claims 1 and 19, Camarota teaches a computing-in-memory system (Camarota; Figure 1), comprising: a plurality of first chips (Camarota; Figure 1 Items 106, Figure 2 Items 206), each including an arrays of computing-in-memory cells (Camarota; Figure 1 Items 106, Paragraph [0032]) and arranged to overlap each other (Camarota; Figure 1 Items 106, Figure 2 Items 206, Paragraph [0037]), wherein the array of computing-in-memory cells is configured to perform computations on received data (Camarota; Paragraphs [0006] and [0258]) to obtain output data; a second chip (Camarota; Figure 1 Item 102, Figure 2 Item 202) that includes a peripheral analog circuit IP core (Camarota; Figure 1 Item 112, Paragraph [0039] “Analog-to-Digital Converters (ADC), Digital-to-Analog Converters (DAC)”) and a digital circuit IP core (Camarota; Figure 1 Items 110 and 114, Paragraphs [0038] – [0039]); and an interface module (Camarota; Figure 1 Items 116 and 124) configured to communicatively couple the second chip to each of the plurality of first chips (Camarota; Figure 1).
Camarota does not teach that the array of computing-in-memory cells are implemented based on an analog circuit and configured to perform computations on programmed data and received first analog data to obtain second analog data; wherein the peripheral analog circuit IP core includes a programming circuit coupled to the array of computing-in-memory cells and configured to perform data programming on the array of computing-in-memory cells to make the programmed data stored in the array of computing-in-memory cells; and the interface module to transfer the second analog data to the second chip using an analog signal.
However, Sun teaches a computing-in-memory system on which computing-in-memory cells (Sun; Figure 6A Item 614) are implemented based on an analog circuit (Sun; Col 4 Lines 22 – 30) and configured to perform computations on programmed data and received first analog data to obtain second analog data (Sun; Col 2 Lines 46 – 63, Col 11 Lines 9 – 13, Figure 8 Item 806); a peripheral analog circuit IP core (Sun; Figure 6A Item 602) including a programming circuit coupled to the array of computing-in-memory cells and configured to perform data programming on the array of computing-in-memory cells to make the programmed data stored in the array of computing-in-memory cells (Sun; Figure 8 Item 804); and transferring the second analog data to the second chip by using an analog signal (Sun; Col 11 Lines 24 – 28).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Camarota to include the analog circuitry and programming because doing so allows for processing efficiency (Sun; Col 2 Lines 22 – 24).
As per claims 2, 11, and 20, Camarota also teaches wherein the interface module comprises a through-silicon via (TSV) structure (Camarota; Paragraphs [0051]).
As per claims 3 and 15, Camarota also teaches wherein the peripheral analog circuit IP core includes one or more of: a digital-to-analog converter (Sun; Col 2 Lines 31 – 34) coupled to the array of computing-in-memory cells and configured to convert first digital data to be input to the array of computing-in-memory cells into the first analog data (Camarota; Paragraph [0039] “Digital-to-Analog Converters (DAC)”) (Sun; Col 2 Lines 31 – 34); an analog-to-digital conversion module coupled to the array of computing-in-memory cells and configured to convert the second analog data into digital data (Camarota; Paragraph [0039] “Analog-to-Digital Converters (ADC)”; a phase-locked loop; and an oscillator.
As per claims 4 and 16, Camarota also teaches wherein the peripheral analog circuit IP core includes one or more modules (Camarota; Paragraph [0039]), and the second chip includes a first sub-chip (Camarota; Paragraph [0038]) that includes a module of the one or more modules of the peripheral analog circuit IP core or a combination thereof (Camarota; Paragraph [0039]).
As per claims 5 and 17, Camarota also teaches wherein the digital circuit IP core includes one or more of: a post-processing operation circuit configured to perform a post-processing operation on the second digital data obtained by the analog-to-digital converter; a random-access memory (RAM); a central processing unit (CPU) (Camarota; Paragraph [0038] “ARM processor architecture, an x86 processor architecture” and “a mobile processor architecture, a reduced instruction set computer (RISC) architecture (e.g., RISC-V), or other suitable architecture that is capable of executing computer-readable program instruction code”); a graphics processing unit (GPU) (Camarota; Paragraph [0038] “a graphics processing unit (GPU) architecture”); and a peripheral interface module (Camarota; Paragraph [0039] “peripheral component interconnect express (PCIe) interfaces).
As per claims 6 and 18, Camarota also teaches wherein the digital circuit IP core includes one or more modules (Camarota; Paragraphs [0038] and [0039]), and wherein the second chip comprises a second sub-chip (Camarota; Paragraph [0038]) that includes a module of the one or more modules of the digital circuit IP core or a combination thereof (Camarota; Paragraph [0039]).
As per claims 7 and 12, Camarota also teaches wherein the array of computing-in-memory cells is integrated, through a first process node (Camarota; Paragraphs [0032] and [0050]), on each of the first plurality of chips, and the peripheral analog circuit IP core and the digital circuit IP core are integrated, through a second process node (Camarota; Paragraphs [0032] and [0050]) different from the first process node, on the second chip.
As per claims 8 and 13, Camarota also teaches wherein a line width of the second process node is less than a line width of the first process node (Camarota; Paragraphs [0032] and [0050]).
As per claim 10, Camarota teaches a method comprising: integrating an array of computing-in-memory cells (Camarota; Figure 1 Items 134) of a computing-in-memory system (Camarota; Figure 1) on each of a plurality of first chips (Camarota; Figure 1 Items 106) arranged to overlap each other (Camarota; Figure 1 Items 106, Figure 2 Items 206, Paragraph [0037]), wherein the array of computing-in-memory cells is configured to perform computations on received data (Camarota; Paragraphs [0006] and [0258]) to obtain output data; integrating a peripheral analog circuit IP core (Camarota; Figure 1 Item 112, Paragraph [0039] “Analog-to-Digital Converters (ADC), Digital-to-Analog Converters (DAC)”) and a digital circuit IP core (Camarota; Figure 1 Items 110 and 114, Paragraphs [0038] – [0039]) of the computing-in-memory system on a second chip (Camarota; Figure 1 Item 102, Figure 2 Item 202); and packaging the plurality of first chips and second chips (Camarota; Paragraph [0036]), wherein the second chip is communicatively coupled to each first chip (Camarota; Figure 1 Items 116 and 124).
Camarota does not teach that the array of computing-in-memory cells are implemented based on an analog circuit and configured to perform computations on programmed data and received first analog data to obtain second analog data; wherein the peripheral analog circuit IP core includes a programming circuit coupled to the array of computing-in-memory cells and configured to perform data programming on the array of computing-in-memory cells to make the programmed data stored in the array of computing-in-memory cells; and the interface module to transfer the second analog data to the second chip using an analog signal.
However, Sun teaches a computing-in-memory system on which computing-in-memory cells (Sun; Figure 6A Item 614) are implemented based on an analog circuit (Sun; Col 4 Lines 22 – 30) and configured to perform computations on programmed data and received first analog data to obtain second analog data (Sun; Col 2 Lines 46 – 63, Col 11 Lines 9 – 13, Figure 8 Item 806); a peripheral analog circuit IP core (Sun; Figure 6A Item 602) including a programming circuit coupled to the array of computing-in-memory cells and configured to perform data programming on the array of computing-in-memory cells to make the programmed data stored in the array of computing-in-memory cells (Sun; Figure 8 Item 804); and transferring the second analog data to the second chip by using an analog signal (Sun; Col 11 Lines 24 – 28).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Camarota to include the analog circuitry and programming because doing so allows for processing efficiency (Sun; Col 2 Lines 22 – 24).
Claim(s) 9 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 2021/0050853 (hereinafter Camarota) in view of US Patent No. 12,086,461 (hereinafter Sun), and further in view of US Patent Application Publication No. 2024/0063079 (hereinafter Shao).
As per claims 9 and 14, Camarota in combination with Sun teaches the invention as described per claims 1 and 10 (see rejection of claims 1 and 10 above).
Camarota in combination with Sun does not teach wherein the array of computing-in-memory cells, and the peripheral analog circuit IP core and the digital circuit IP core are respectively integrated, through a same process node, on each of the plurality of first chips and the second chip.
However, Shao teaches a system in which a logic layer is implemented in a same process node as a memory layer (Shao; Paragraph [0021] “The semiconductor devices 60A and 60B may be formed in processes of a same technology node…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Camarota in combination with Sun to include the same process node because doing so would be a design choice when balancing system size, cost, and speed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RICHARD B FRANKLIN/Examiner, Art Unit 2181
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
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