DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 9 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Hokazono et al. (US 2018/0198442 and Hokazono hereinafter)
Regarding claim 1, Hokazono discloses [figs. 4-5] a gate drive unit [100a] for a semiconductor switching element [500], the gate drive unit comprising: a voltage detection circuit [desaturation voltage detection circuit 201] configured to detect a rise of an inter-electrode voltage [collector-emitter voltage (Vce), par. 0041 and 0050, fig. 5] between a positive electrode [collector electrode 500] and a negative electrode [emitter electrode 500] when the semiconductor switching element is being turned off; and a drive circuit [218] configured to drive a gate of the semiconductor switching element [gate 500], wherein the drive circuit is configured to regulate a time [using delay circuit 32] to lower a gate drive capability [par. 52-54 and 57] from a first drive capability [initial strong pull down current (drive capability)] to a second drive capability [reduced pull down current (drive capability) triggered by Vdesat detection] based on a detection result [Vdesat] of the voltage detection circuit during a period [at time Te2, fig. 5] in which a control signal [H0] that controls ON and OFF of the semiconductor switch element is set to a level [low level, par. 0064] corresponding to an OFF period of the semiconductor switching element and the period is during a turn-off operation [cut off state, par. 64] of the semiconductor switching element [par. 0049-0065].
Regarding claim 2, Hokazono discloses [figs. 4-5], wherein the voltage detection circuit is configured to detect [201] the rise of the inter-electrode voltage [Vce at period Td and Te2, fig. 5] when the inter-electrode voltage becomes higher than a predetermined first determination voltage [Vdsth2] after the start of the turn-off operation [period Te2, fig. 5] of the semiconductor switching element, and the drive circuit is further configured to set the gate drive capability to the first drive capability at the start of the turn-off operation, and to lower the gate drive capability from the first drive capability to the second drive capability at a time when a predetermined first delay time [tth3, fig. 5] has elapsed after the voltage detection circuit detects the rise of the inter-electrode voltage.
Regarding claim 9, Hokazono discloses [figs. 4-5] wherein the voltage detection circuit [desaturation voltage detection circuit 201] is further configured to detect an unsaturation state [desaturation (the switching element not fully on)] of the semiconductor switching element based on the inter-electrode voltage when the semiconductor switching element is being turned on, and the drive circuit is further configured to drive the gate to turn off the semiconductor switching element when the unsaturation state is detected by the voltage detection circuit during the turn-on operation of the semiconductor switching element [par. 0049-0065].
Allowable Subject Matter
Claims 3-8 and 10-12 are objected to as being dependent upon a rejected base claim, but
would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed on 04/22/2026 have been fully considered but they are not persuasive.
Regarding claim 1, applicant argues that Hokazono fails to disclose “a period in which a control signal that controls ON and OFF of the semiconductor switch element is set to a level corresponding to an OFF period of the semiconductor switching element and the period is during a turn-off operation of the semiconductor switching element.” Examiner respectfully disagrees.
Hokazono discloses as shown in figure 5, a period [at time Te2, fig. 5] in which a control signal [H0] that controls ON and OFF of the semiconductor switch element is set to a level [low level, par. 0064] corresponding to an OFF period of the semiconductor switching element and the period is during a turn-off operation [cut off state, par. 64] of the semiconductor switching element [par. 0049-0065, during turn-off period at time Te2, transistor 500 enters its turn-off state due to Vdesat exceeding the threshold Vdsth2].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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