DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 6 and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ookawa et al. (US Pat. App. Pub. No. 2022/0024814) in view of Lee et al. (US Pat. App. Pub. No. 2021/0012964).
With respect to claim 1, Ookawa teaches a ceramic electronic component (see paragraph [0005]) comprising: a ceramic body (see FIG. 2, element 11 and paragraph [0048]) including an internal electrode layer (see FIG. 2, element 16 and paragraph [0050]); and an outer electrode on a surface of the ceramic body and electrically connected to the internal electrode layer (see FIG. 2, element 12 and paragraph [0048]); wherein the outer electrode includes: a base electrode layer including a SiO2-BaO-B2O3-CaO-based glass (see paragraph [0033], citing a borosilicate glass, and paragraph [0107] and Table 1, noting that Ba and Ca are included in the borosilicate glass); a protective layer covering a surface of the SiO2-BaO-B2O3-CaO-based glass exposed on a surface of the base electrode layer and including at least one of P, S, C, Si, Ba, F, N, Al, Sr, or B (see FIG. 2, element 15 and paragraph [0049], citing a silicate film); and a plating layer covering the base electrode layer and the protective layer (see paragraph [0052]).
Ookawa fails explicitly teach that the plating film is a Ni plating layer.
Lee, on the other hand, teaches that a Ni plating layer is formed over a base electrode layer. See FIG. 2, elements 131b and paragraph [0056], noting that protective layer 33, including S and Ba, is disposed between the glass G and Ni plating layer 31a. Such an arrangement results in improved mountability, structural reliability, and external durability. See paragraph [0056].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Ookawa, as taught by Lee, in order to improve mountability, structural reliability, and external durability.
With respect to claim 2, the combined teachings of Ookawa and Lee teach that the protective layer includes P or B. See Ookawa, paragraph [0042].
With respect to claim 6, the combined teachings of Ookawa and Lee teach that the ceramic electronic component is a capacitor. See Ookawa, paragraph [0005].
With respect to claim 9, the combined teachings of Ookawa and Lee teach that the ceramic body is a multilayer ceramic body. See Ookawa, paragraph [0005].
With respect to claim 10, the combined teachings of Ookawa and Lee teach that the ceramic electronic component is a multilayer ceramic capacitor. See Ookawa, paragraph [0005].
With respect to claim 11, the combined teachings of Ookawa and Lee teach that the multilayer ceramic capacitor has a substantially rectangular parallelepiped shape. See Ookawa, FIG. 2 and paragraph [0048].
With respect to claim 12, the combined teachings of Ookawa and Lee teach that the ceramic body includes a plurality of dielectric layers. See Ookawa, FIG. 2.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ookawa et al. (US Pat. App. Pub. No. 2022/0024814) in view of Lee et al. (US Pat. App. Pub. No. 2021/0012964), and further, in view of Kitahara et al. (US Pat. App. Pub. No. 2022/0102077).
With respect to claim 3, the combined teachings of Ookawa and Lee fail to explicitly teach that a thickness of the protective layer is equal to or more than about 1 nm and equal to or less than about 100 nm.
Kitahara, on the other hand, teaches that that a thickness of the protective layer is equal to or more than about 1 nm and equal to or less than about 100 nm. See paragraph [0112]. Such an arrangement results in the prevention of erosion of the glass G by the plating solution. See paragraph [0161]-[0162].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing dated of the invention, to modify the combined teachings of Ookawa and Lee, as taught by Kitahara, in order to prevent erosion of the glass G by the plating solution.
Claims 4, 5 and 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ookawa et al. (US Pat. App. Pub. No. 2022/0024814) in view of Lee et al. (US Pat. App. Pub. No. 2021/0012964), and further, in view of Nakano et al. (US Pat. App. Pub. No. 2021/0183581).
With respect to claim 4, the combined teachings of Ookawa and Lee fail to explicitly teach that a thickness of a thinnest portion of the base electrode layer is equal to or more than about 0.1 µm and equal to or less than about 5 µm.
Nakano, on the other hand, teaches that a thickness of a thinnest portion of the base electrode layer is equal to or more than about 0.1 µm and equal to or less than about 5 µm. See paragraphs [0052]-[0053]. Such an arrangement results in the ability to maintain miniaturization of the capacitor. See paragraph [0003].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing dated of the invention, to modify the combined teachings of Ookawa and Lee, as taught by Nakano, in order to maintain miniaturization of the capacitor.
With respect to claim 5, the combined teachings of Ookawa and Lee fail to teach that a thickness of the dielectric layer is equal to or more than about 0.3 µm and equal to or less than about 0.45 µm.
Nakano, on the other hand, teaches that a thickness of the dielectric layer is equal to or more than about 0.3 µm and equal to or less than about 0.45 µm. See paragraph [0036]. Such an arrangement results in the ability to maintain miniaturization of the capacitor. See paragraph [0003].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing dated of the invention, to modify the combined teachings of Ookawa and Lee, as taught by Nakano, in order to maintain miniaturization of the capacitor.
With respect to claim 13, the combined teachings of Ookawa and Lee fail to teach that a thickness of the dielectric layer is equal to or more than about 0.3 µm and equal to or less than about 0.45 µm.
Nakano, on the other hand, teaches that a thickness of the dielectric layer is equal to or more than about 0.3 µm and equal to or less than about 0.45 µm. See paragraph [0036]. Such an arrangement results in the ability to maintain miniaturization of the capacitor. See paragraph [0003].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing dated of the invention, to modify the combined teachings of Ookawa and Lee, as taught by Nakano, in order to maintain miniaturization of the capacitor.
With respect to claim 14, the combined teachings of Ookawa and Lee fail to teach that a thickness of the internal electrode layer is equal to or more than about 0.2 µm and equal to or less than about 2.0 µm. See paragraph [0042].
Nakano, on the other hand, teaches that a thickness of the internal electrode layer is equal to or more than about 0.2 µm and equal to or less than about 2.0 µm. See paragraph [0042]. Such an arrangement results in the ability to maintain miniaturization of the capacitor. See paragraph [0003].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing dated of the invention, to modify the combined teachings of Ookawa and Lee, as taught by Nakano, in order to maintain miniaturization of the capacitor.
With respect to claim 15, the combined teachings of Ookawa and Lee fail to teach that a Sn plating layer is on the Ni plating layer.
Nakano, on the other hand, teaches that a Sn plating layer is on the Ni plating layer. See paragraph [0055]. Such an arrangement results in improved wettability of solder used to mount the multilayer ceramic capacitor. See paragraph [0056].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing dated of the invention, to modify the combined teachings of Ookawa and Lee, as taught by Nakano, in order to improve the wettability of solder used to mount the multilayer ceramic capacitor.
Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ookawa et al. (US Pat. App. Pub. No. 2022/0024814) in view of Lee et al. (US Pat. App. Pub. No. 2021/0012964), and further, in view of Sakai (US Pat. App. Pub. No. 2021/0366657).
With respect to 7, the combined teachings of Ookawa and Lee fail to teach that the ceramic electronic component is an inductor.
Sakai, on the other hand, teaches that a ceramic component formed as a capacitor can also be formed as an inductor. See paragraph [0138]. Such a modification is known, based on the desired electrical characteristics of the device. See paragraph [0138].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing dated of the invention, to modify the combined teachings of Ookawa and Lee, as taught by Sakai, based on the desired electrical characteristics of the device.
With respect to claim 8, the combined teachings of Ookawa and Lee fail to teach that the ceramic electronic component is a varistor.
Sakai, on the other hand, teaches that a ceramic component formed as a capacitor can also be formed as an inductor. See paragraph [0138]. Such a modification is known, based on the desired electrical characteristics of the device. See paragraph [0138].
Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing dated of the invention, to modify the combined teachings of Ookawa and Lee, as taught by Sakai, based on the desired electrical characteristics of the device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kitahara et al. (US 2022/0102075) teaches an external electrode including glass that has a protective layer adjacent to the Ni plating layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION R FERGUSON whose telephone number is (571)270-7566. The examiner can normally be reached Monday-Friday, 5:30 a.m. - 4:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DION R. FERGUSON/Primary Examiner, Art Unit 2848