DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species I in the reply filed on 9/15/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 6-7, 10, 12, 13 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/15/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-9, 11 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US PG Pub 2022/0246837, hereinafter Lee).
Regarding claim 1, figure 7 of Lee discloses a semiconductor device, comprising:
lower conductive patterns (209) on a substrate (200) and horizontally spaced apart from each other;
upper conductive patterns (286) on the lower conductive patterns and horizontally spaced apart from each other; and
a first via contact (252d on the left) and a second via contact (224a/226a/253c) second from the left) between the lower conductive patterns and the upper conductive patterns and horizontally spaced apart from each other,
wherein the first via contact has a first width in a first direction parallel to a top surface of the substrate,
wherein the second via contact has a second width in the first direction that is wider than the first width,
wherein the second via contact comprises a first metal pattern (226a second from the left) and a second metal pattern (252c) on the first metal pattern,
wherein the first metal pattern comprises a same material as the first via contact (¶ 60, 66), and
wherein the second metal pattern comprises a different material from the first metal pattern and the first via contact (¶ 60).
Regarding claim 2, figure 7 of Lee discloses a lowermost surface of the first via contact (252d) is in contact with a top surface of a first lower conductive pattern (209) among the lower conductive patterns, and a lowermost surface of the second via contact (224a/226a/253c) is in contact with a top surface of a second lower conductive pattern among the lower conductive patterns, and
wherein an uppermost surface of the first via contact is in contact with a bottom surface of a first upper conductive pattern (286) among the upper conductive patterns, and an uppermost surface of the second via contact is in contact with a bottom surface of a second upper conductive pattern among the upper conductive patterns.
Regarding claim 3, figure 7 of Lee discloses an uppermost surface of the second metal pattern (252c) is in contact with the bottom surface of the second upper conductive pattern.
Regarding claim 4, figure 7 of Lee discloses an uppermost surface of the first metal pattern (226a) is located at a height from the top surface of the substrate (200) that is lower than a height of the uppermost surface of the first via contact (252d) from the top surface of the substrate.
Regarding claim 5, figure 7 of Lee discloses the second via contact (224a/226a/253c) further comprises a third metal pattern (252d second from the left) on the second metal pattern (252c),
wherein a first portion of the second metal pattern is between the first metal pattern (226a) and the third metal pattern, and a second portion of the second metal pattern is on a side surface of the third metal pattern, and
wherein an uppermost surface of the third metal pattern is in contact with the bottom surface of the second upper conductive pattern (286).
Regarding claim 8, figure 7 of Lee discloses a first interlayer insulating layer (204) on the substrate (200) and on side surfaces of the lower conductive patterns (209); and
a second interlayer insulating layer (214/240/242a) on the first interlayer insulating layer and on side surfaces of the first (252d on the left) and second (224a/226a/253c) via contacts,
wherein the upper conductive patterns (256) are on the second interlayer insulating layer,
wherein the first via contact extends into the second interlayer insulating layer and is electrically connected to a first lower conductive pattern among the lower conductive patterns and a first upper conductive pattern among the upper conductive patterns, and
wherein the second via contact extends into the second interlayer insulating layer and is electrically connected to a second lower conductive pattern among the lower conductive patterns and a second upper conductive pattern among the upper conductive patterns.
Regarding claim 9, figure 7 of Lee discloses the second via contact (224a/226a/253c) further comprises a third metal pattern (252d second from the left) on the second metal pattern (252c),
wherein the first metal pattern (226a) is between the second lower conductive pattern (209) and the second metal pattern, and wherein a first portion of the second metal pattern is between the first metal pattern and the third metal pattern, and a second portion of the second metal pattern is between the third metal pattern and the second interlayer insulating layer (214/240/242a).
Regarding claim 11, figure 7 of Lee discloses an overlay key pattern (253c, next one over in the array, see figure 3) in the second interlayer insulating layer (214/240/242a) and horizontally spaced apart from the first and second via contacts,
wherein the overlay key pattern comprises a first key pattern (252c) and a second key pattern (252d) on the first key pattern,
wherein a first portion of the first key pattern is between a bottom surface of the second key pattern and the second interlayer insulating layer, and a second portion of the first key pattern is between a side surface of the second key pattern and the second interlayer insulating layer, and
wherein the first key pattern comprises a same material as the second metal pattern (252c, second from the left).
second portion of the third key pattern is between a side surface of the first key pattern and the second interlayer insulating layer.
Regarding claim 20, figure 7 of Lee discloses a semiconductor device, comprising:
a first lower conductive pattern (209 on the left) on a substrate (200);
a second lower conductive pattern (209 second from the left) on the substrate and horizontally spaced apart from the first lower conductive pattern;
a first upper conductive pattern (286 on the left) on the first lower conductive pattern;
a second upper conductive pattern (286 second from the left) on the second lower conductive pattern and horizontally spaced apart from the first upper conductive pattern;
a first via contact (252d on the left) electrically connected between the first lower conductive pattern and the first upper conductive pattern; and
a second via contact (224a/226a/253c) electrically connected between the second lower conductive pattern and the second upper conductive pattern,
wherein the first via contact has a first width in a direction parallel to a top surface of the substrate,
wherein the second via contact has a second width in the direction that is different from the first width,
wherein the second via contact comprises a first metal pattern (226a second from the left) and a second metal pattern (252c) on the first metal pattern, and
wherein one (226a) of the first and second metal patterns comprises a same material as the first via contact (¶ 60, 66), and another one (252c) of the first and second metal patterns comprises a different material from the first via contact (¶ 60).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claim 14, figure 7 of Lee discloses a semiconductor device, comprising:
transistors (52) on a substrate (200);
lower conductive patterns (209) horizontally spaced apart from each other;
upper conductive patterns (286) on the lower conductive patterns and horizontally spaced apart from each other; and
a first via contact (252d on the left) and a second via contact (224a/226a/253c) between the lower conductive patterns and the upper conductive patterns and horizontally spaced apart from each other,
wherein the first via contact electrically connects a first lower conductive pattern among the lower conductive patterns to a first upper conductive pattern among the upper conductive patterns, and the second via contact electrically connects a second lower conductive pattern among the lower conductive patterns to a second upper conductive pattern among the upper conductive patterns,
wherein the first via contact has a first width in a first direction parallel to a top surface of the substrate,
wherein the second via contact has a second width in the first direction that is wider than the first width,
wherein the second via contact comprises a first metal pattern (226a second from the left) and a second metal pattern (252c) on the first metal pattern,
wherein the first metal pattern comprises a same material as the first via contact (¶ 60, 66), and
wherein the second metal pattern comprises a different material from the first metal pattern and the first via contact (¶ 60).
Lee does not explicitly disclose the lower conductive patterns are electrically connected to gate terminals or source/drain terminals of the transistors.
However, it would have been obvious to have the lower conductive patterns electrically connect to the gate terminals or source/drain terminals of the transistors in order to provide signals for operating the transistors.
Regarding claim 15, figure 7 of Lee discloses an interlayer insulating layer (214/240/242a) between the lower conductive patterns (209) and the upper conductive patterns (286),
wherein the first via contact (252d on the left) extends into the interlayer insulating layer and electrically connects the first lower conductive pattern to the first upper conductive pattern, and
wherein the second via contact (224a/226a/253c) extends into the interlayer insulating layer and electrically connects the second lower conductive pattern to the second upper conductive pattern.
Regarding claim 16, figure 7 of Lee discloses an overlay key pattern (253c, next one over in the array, see figure 3) horizontally spaced apart from the first and second via contacts,
wherein the substrate (200) comprises a first region and a second region different from the first region,
wherein the transistors, the lower conductive patterns (209), the upper conductive patterns (286), the first (252d on the left) and second via contacts (224a/226a/253c), and the interlayer insulating layer (214/240/242a) are on the first region of the substrate,
wherein the interlayer insulating layer extends onto the second region of the substrate,
wherein the overlay key pattern is in the interlayer insulating layer on the second region,
wherein the overlay key pattern comprises a first key pattern (252c) and a second key pattern (252d) on the first key pattern, and
wherein the first key pattern comprises a same material as the second metal pattern (252c, second from the left).
Regarding claim 16, figure 7 of Lee discloses a first portion of the first key pattern (252c) is between a bottom surface of the second key pattern (252d) and the interlayer insulating layer (214/240/242a), and a second portion of the first key pattern is between a side surface of the second key pattern and the interlayer insulating layer.
Regarding claim 18, figure 7 of Lee discloses the second via contact (224a/226a/253c) further comprises a third metal pattern (252d second from the left) on the second metal pattern (252c), and wherein the second key pattern (252d) comprises a same material as the third metal pattern.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
