DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 07/09/2024 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 07/09/2024. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Hayashi et al (US20110310515).
Regrading claim 1, Hayashi discloses a semiconductor device comprising(FIG 1; 4): a first power supply wiring configured to supply a first power supply voltage(Vdd1); a second power supply wiring configured to supply a second power supply voltage(Vdd2); a first ground wiring configured to supply a first ground voltage(Vss1); a second ground wiring configured to supply a second ground voltage(Vss2); an I/O cell connected between the first power supply wiring and the first ground wiring (FIG 4;I/O 41 between Vdd1 and Vss1) ; a core logic circuit connected between the second power supply wiring and the second ground wiring(12 is between Vdd2 and Vss2); a first power supply cell and a second power supply cell connected between the first power supply wiring and the first ground wiring(41 & 42 between Vdd1 and Vss1); and a third power supply cell and the fourth power supply cell connected between the second power supply wiring and the second ground wiring(51 & 55 between Vdd2 and Vss2), wherein each of the first, second, third and fourth power supply cell includes: a protection circuit connected between the corresponding power supply wiring and the corresponding ground wiring(EsDdd12, ESDdd23, ESDss14 & ESDss12 connected between corresponding power supply wiring and ground wiring); and a bi-directional diode connected between the first ground wiring and the second ground wiring (ESDss12 comprising bi-direction diode connected between Vss1 and Vss2).
Regrading claim 2, Hayashi discloses wherein each bi-directional diode of the first and second power supply cell is disposed between the core logic circuit and the protection circuit therein in a plan view(FIG 4; ESDdd12 comprising bi-direction diode is between 11 and 41), and wherein each bi-directional diode of the third and fourth power supply cell is disposed at a chip side so that the protection circuit is disposed between the core logic circuit and the bi-directional diode in the plan view(FIG 4; same applied e.g., EsDss12 in between of 12 and 41 and so on).
Allowable Subject Matter
Claims 3-6 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Yamanishi et al (US20110074438 FIG 1B; [0010]; discloses bi-direction diodes connected to transistors, power supply line, and a ground line).
Ikeda et al (US2006007760 FIG 9; discloses first power supply, first ground supply, circuit block 90 connected between first power supply and first ground supply, transistor, one directions diode 90a and 90b, wherein the diodes are connected to the transistors PMOS and NMOS connected to the second set diodes that are connected to circuit blocks 91, and wherein 91 is connected between a second power supply Vdd2 and second ground supply Vss2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827
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