Prosecution Insights
Last updated: August 17, 2026
Application No. 18/767,312

SEMICONDUCTOR PACKAGE

Non-Final OA §112
Filed
Jul 09, 2024
Priority
Jan 16, 2024 — RE 10-2024-0006781
Examiner
SOWARD, IDA M
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1263 granted / 1354 resolved
+33.3% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
43 currently pending
Career history
1383
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
37.7%
-2.3% vs TC avg
§102
36.4%
-3.6% vs TC avg
§112
25.0%
-15.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1354 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is in response to the application filed July 9, 2024. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR PACKAGE INCLUDING HORIZONTALLY ADJACENT CAPACITOR AND INTERPOSER CHIPS. The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: outer connection terminal, upper connection terminal and lower connection terminal. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The interchanging of the terminology of the connection terminals, connection patterns, interconnection patterns, interconnection layers, connection members, connection substrates and connection bumps makes it difficult and confusing to understand with clarity which is the outer connection terminal, upper connection terminal and lower connection terminal. Claims 16-20 are rejected as being dependent upon rejected claim 15. Allowable Subject Matter Claims 1-14 are allowed. The following is a statement of reasons for the indication of allowable subject matter: In regard to claim 1, The prior art of record (Hwang et al. (US 2019/0057949 A1)) does not disclose, make obvious, or otherwise suggest the structure of the applicant's claimed invention together with the other limitations of the dependent claims 2-7, such as the configuration of the redistribution layers, capacitor chip, mold layer, interposer chip, electrodes and capacitor dielectric layer; and In regard to claim 8, The prior art of record (Hwang et al. (US 2019/0057949 A1)) does not disclose, make obvious, or otherwise suggest the structure of the applicant's claimed invention together with the other limitations of the dependent claims 9-14, such as the configuration of the interposer substrate, semiconductor chip, redistribution layers, insulating patterns, interconnection patterns, interposer core structure, capacitor chip, interposer chip, electrodes and dielectric layer. As best understood, claims 15-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor packages: Byun et al. (US 2020/0185357 A1) Cheah et al. (US 2022/0302033 A1) Hwang et al. (US 2019/0057949 A1) Hsieh et al. (US 2019/0164905 A1) Kim (US 2022/0392843 A1) Kuan et al. (US 11,562,963 B2) Lee et al. (US 2022/0102315 A1) Lee et al. (US 2022/0165721 A1) Lyne et al. (US 8,957,525 B2) Pan et al. (US 11,646,255 B2) Shen et al. (CN 111211107 A) Shim et al. (US 2020/0161266 A1) Suk et al. (US 2022/0157810 A1) Ting et al. (US 10,867,954 B2) Tsui et al. (US 2021/0091005 A1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDA M SOWARD whose telephone number is (571)272-1845. The examiner can normally be reached Monday through Thursday, 7am to 5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. IMS July 16, 2026 /IDA M SOWARD/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Jul 09, 2024
Application Filed
Jul 21, 2026
Non-Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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DISPLAY PANEL AND DISPLAY APPARATUS INCLUDING TRANSMISSION AREA WITHIN COMPONENT AREA
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Patent 12695198
TERAHERTZ TRANSCEIVER INCLUDING TRIPLE-BARRIER RESONANT TUNNELING DIODE
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+5.5%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1354 resolved cases by this examiner. Grant probability derived from career allowance rate.

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