DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed May 22, 2026 has been entered. Claims 1-2, 4-5, 7-11, 13-14, and 16-20 remain pending in the application. Applicant’s amendments to the Specification, Drawings, and Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed February 23, 2026.
Response to Arguments
Applicant's arguments filed May 22, 2026 have been fully considered but they are not persuasive. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the feature upon which applicant relies (i.e., requiring an explicit numerical value) is not directly recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In the amended claim 1, the limitation requires “information with respect to a number of a plurality of input data”, not an explicit numerical value. In the broadest reasonable interpretation, the received information is related to the number of a plurality of input data, but does not have to exactly be the number of a plurality of input data. Shinichi teaches receiving bit stream data stored in memory, and the bit stream data structure includes indexing for each frame (Paragraph 0013, 0016 – “Reference numeral 102 denotes an MPEG4 decoder unit which reads MPEG4 bit stream data and performs MPEG4 decoding processing…FIG. 2 shows the data structure of the MPEG4 bitstream data stored in the MPEG4 bitstream data storage memory 103b, as well as index data for data search”). The indexing for the input frame data, which is shown in the screenshot of Fig. 2 below, is related to the number of input frame data since there is an index value for each piece of data and the value increments per piece of data. Thus, information (the index values) is received, and they are with respect to a number of input data stored in the input data buffer/memory since the index values relate to and depend on the number of input data.
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Screenshot of Fig. 2 (taken from Shinichi)
Despite Shinichi’s teachings, Yukio is used below in the rejection of claim 1 since Yukio already teaches receiving information with respect to a number of a plurality of input data (Paragraph 0003, 0042 – “the image to be processed is often divided into a number of rectangular blocks called tiles…if the number of input codes is less than the specified number of tiles (EOC is input earlier than the specified position), the tiles up to that point are decoded and the process ends. (An interrupt signal is generated when the operation is completed.)”; Note: the number of tiles is equivalent to the number of input data, since the tiles are the data to be processed. It is implied that the number of tiles is received since it is used to determine when the process ends) stored in an input data buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: encoded data, which is input data, is stored in the frame memory, which is equivalent to the input data buffer). See the rejection of claim 1 below for more information.
Claim Objections
Claim 10 recites the limitation "the codec" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yukio et al. (JP 2003101792 A), hereinafter Yukio.
Regarding claim 1, Yukio teaches an image processing method (Paragraph 0021 – “an image processing apparatus having an encoding device or a decoding device, an interrupt is performed when encoding or decoding of one screen is completed”), comprising:
receiving information with respect to a number of a plurality of input data (Paragraph 0003, 0042 – “the image to be processed is often divided into a number of rectangular blocks called tiles…if the number of input codes is less than the specified number of tiles (EOC is input earlier than the specified position), the tiles up to that point are decoded and the process ends. (An interrupt signal is generated when the operation is completed.)”; Note: the number of tiles is equivalent to the number of input data, since the tiles are the data to be processed. It is implied that the number of tiles is received since it is used to determine when the process ends) stored in an input data buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: encoded data, which is input data, is stored in the frame memory, which is equivalent to the input data buffer);
performing an image processing operation with respect to the plurality of input data (Paragraph 0030 – “During decoding, the decoder 100 receives a bit stream from the code data bus COD7-0, decodes it, and outputs image data to the image data bus IMD19-0”; Note: decoding is the image processing operation, and the bitstream is the input data) stored in the input data buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: encoded data, which is input data, is stored in the frame memory, which is equivalent to the input data buffer);
determining, based on information of the number of the plurality of input data, whether performing the image processing operation with respect to the plurality of input data has been finished (Paragraph 0042 – “if the number of input codes is less than the specified number of tiles (EOC is input earlier than the specified position), the tiles up to that point are decoded and the process ends. (An interrupt signal is generated when the operation is completed.)”; Note: the number of tiles is equivalent to the number of input data, since the tiles are the data to be processed, and it is used to determine when the process ends);
and based on performing the image processing operation being finished, transmitting an interrupt signal, the interrupt signal indicating that the image processing operation with respect to the plurality of input data has been finished (Paragraph 0019, 0042 – “the decoding device interrupts the image processing device when it has decoded data…if the number of input codes is less than the specified number of tiles (EOC is input earlier than the specified position), the tiles up to that point are decoded and the process ends. (An interrupt signal is generated when the operation is completed.)”; Note: when decoding is finished, an interrupt signal is generated. The interrupt signal is transmitted to the processing device).
Regarding claim 7, Yukio teaches the image processing method of claim 1. Yukio further teaches before the plurality of input data is stored in the input data buffer, receiving a power-ON signal (Paragraph 0047 – “After the decoding process starts, when the coded data to be input from the outside is ready, COFRM is set to `L` and the coded data is input using COMRDY and COJRDY”; Note: it is implied that a power-ON signal is received before storing the input data because the decoding process has already started even when it has not yet been confirmed that the input data is ready, and the decoding process cannot start without being powered on).
Note: inherently, all computers need power to operate, and hence must have a power on signal after power has cut off. The first power received by the computer after power off can be treated as power on signal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yukio.
Regarding claim 10, Yukio teaches a system-on-chip (Paragraph 0029 – “one-chip encoder/decoder 40”), comprising:
a processor (Paragraph 0029 – “The encoder/decoder 40 in FIG. 9 is composed of a pre- and post-processing unit 41”);
and a codec (Paragraph 0029 – “The encoder/decoder 40”) configured to perform an image processing operation with respect to the plurality of input data (Paragraph 0030 – “During decoding, the decoder 100 receives a bit stream from the code data bus COD7-0, decodes it, and outputs image data to the image data bus IMD19-0”; Note: decoding is the image processing operation, and the bitstream is the input data),
determine, based on information of a number of the plurality of input data, whether performing the image processing operation with respect to the plurality of input data has been finished (Paragraph 0042 – “if the number of input codes is less than the specified number of tiles (EOC is input earlier than the specified position), the tiles up to that point are decoded and the process ends. (An interrupt signal is generated when the operation is completed.)”; Note: the number of tiles is equivalent to the number of input data, since the tiles are the data to be processed, and it is used to determine when the process ends);
and based on performing the image processing operation with respect to the plurality of input data being finished, transmit an interrupt signal to the processor, the interrupt signal indicating that the image processing operation with respect to the plurality of input data has been finished (Paragraph 0019, 0042 – “the decoding device interrupts the image processing device when it has decoded data…if the number of input codes is less than the specified number of tiles (EOC is input earlier than the specified position), the tiles up to that point are decoded and the process ends. (An interrupt signal is generated when the operation is completed.)”; Note: when decoding is finished, an interrupt signal is generated. The interrupt signal is transmitted to the processing device).
Yukio does not directly teach that the system-on-chip comprises a processor configured to store a plurality of input data in an input data buffer. However, Yukio separately teaches a processor (Paragraph 0029 – “The encoder/decoder 40 in FIG. 9 is composed of a pre- and post-processing unit 41”) and storing a plurality of input data in an input data buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: the encoded data is equivalent to the input data, and the frame memory is equivalent to the input data buffer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the features of Yukio to have the processor be configured to store a plurality of input data in an input data buffer because logically, a processor is required to manage the data in the memory, and having the processor in the system-on-chip be able to handle the storage would make the system-on-chip more efficient and capable since it would not have to rely on an external processor.
Furthermore, Yukio does not directly teach wherein the processor is configured to transmit to the codec, information of a number of a plurality of input data stored in the input data buffer. However, Yukio separately teaches a processor (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: it is implied that a processor exists either comprising the memory controller or connected to it because the memory controller would not be able to work without a processor) and the codec receiving information of the number of the plurality of input data (Paragraph 0030, 0042 – “During decoding, the decoder 100 receives a bit stream from the code data bus COD7-0, decodes it, and outputs image data to the image data bus IMD19-0…if the number of input codes is less than the specified number of tiles (EOC is input earlier than the specified position), the tiles up to that point are decoded and the process ends. (An interrupt signal is generated when the operation is completed.)”; Note: the codec receives the number of tiles, which is equivalent to the number of input data) stored in the input data buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: encoded data, which is input data, is stored in the frame memory, which is equivalent to the input data buffer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the features of Yukio to have the processor transmit the information of the number of the plurality of input data to the codec because the purpose of the memory controller/processor is to manage the data stored in the memory, and the codec uses information of the number of data stored in order to determine if the processing is complete. Therefore, it would be logical and efficient for the memory controller/processor to transmit that information to the codec since based on the role of the memory controller/processor, it would likely have that information already available.
Claims 2, 4-5, 9, 11, 13-14, 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yukio in view of Shinichi (JP 2005167331 A), hereinafter Shinichi.
Regarding claim 2, Yukio teaches the image processing method of claim 1. Yukio does not teach based on the plurality of input data being stored in the input data buffer, receiving a power-ON signal. However, Shinichi teaches based on the plurality of input data being stored in the input data buffer, receiving a power-ON signal (Paragraph 0016, 0018, 0021-0022 – “FIG. 2 shows the data structure of the MPEG4 bitstream data stored in the MPEG4 bitstream data storage memory 103b, as well as index data for data search… Reference numeral 202 denotes index data for searching the start position of each frame of the bit stream data 201. The index data 202 stores a frame type flag 202a, a time stamp 202b, and a pointer 202c as a set for each frame…when a playback operation is instructed by pressing the playback button or the like on the operation unit 110, first, in step S301, the power supply to the MPEG4 decoder unit 102 is turned on…the address pointer 103d indicating the playback position is set to the position 202a in the index data 202 which indicates the first frame of the bit stream data.”; Note: it is implied that the power supply is turned on for the decoder after the input data is stored in the buffer (bitstream data storage memory) since the power supply is turned on in response to a playback operation; the playback operation logically can only occur if there is encoded data already stored to be played). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Shinichi to have a power-on signal after storing all the input data because “power is supplied to the hardware decoding means that decodes the video stream for the period required to perform processing in response to user input instructions, thereby reducing power consumption and providing advantages in terms of heat generation countermeasures” (Shinichi: Paragraph 0008). In other words, waiting to power on the decoder until it is needed helps save energy.
Regarding claim 4, Yukio in view of Shinichi teaches the image processing method of claim 1. Yukio further teaches generating an output data with reference to the input data (Paragraph 0030 – “During decoding, the decoder 100 receives a bit stream from the code data bus COD7-0, decodes it, and outputs image data to the image data bus IMD19-0.”). Yukio does not teach wherein performing the image processing operation comprises for each input data of the plurality of input data, reading the input data from a base address of the input data buffer. However, Shinichi teaches for each input data of the plurality of input data, reading the input data from a base address of the input data buffer (Paragraph 0016, 0018-0022, 0025 – “FIG. 2 shows the data structure of the MPEG4 bitstream data stored in the MPEG4 bitstream data storage memory 103b, as well as index data for data search…The index data 202 stores a frame type flag 202a, a time stamp 202b, and a pointer 202c as a set for each frame…The pointer 202c stores the start address of each frame of the bit stream data…in step S302, the address pointer 103d indicating the playback position is set to the position 202a in the index data 202 which indicates the first frame of the bit stream data. Then, in step S303, the bit stream data indicated by the address pointer position is read, and in step S304, the MPEG4 decoder unit 102 executes the decoding process…If it is determined that the frame is not the final frame, the address pointer is advanced by one in step S308, and the process returns to step S303 to perform the bitstream reading process again”; Note: the pointer is the base/start address of the frame. The frame is input data, and the bitstream data storage memory is the input data buffer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Shinichi to read each input data from a base address because in the art, the base address indicates where the data starts. Logically, it would not make sense to read data from the middle or the end, so using the base address to locate and retrieve the data would be most beneficial for future processing.
Regarding claim 5, Yukio in view of Shinichi teaches the image processing method of claim 4. Yukio further teaches the input data comprises information with respect to an encoded bitstream buffer (Paragraph 0032-0033, 0043 – “FIG. 10 shows an example of the format of the coded data output from the encoder/decoder 40 to the coded data bus COD7-0. The coded data always begins with the main header. The code indicating the beginning of the main header is SOC (Start of Codestream) 51…The tile part header of the bitstream 560 is made up of SOT 53 indicating the start of the tile part, T0 and TP0 (Tile 0 header maker segment) 540 indicating the contents of the tile part header, and SOD (Start of Data) 55 indicating the start of data… The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: the coded data, which is the input data, contains information regarding where the encoded bitstream starts/is located. The encoded bitstream is stored in the frame memory, which is equivalent to a buffer); and the output data comprises a decoded picture obtained based on performing decoding with respect to encoded bitstream (Paragraph 0030 – “During decoding, the decoder 100 receives a bit stream from the code data bus COD7-0, decodes it, and outputs image data to the image data bus IMD19-0”) stored in the encoded bitstream buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: encoded data is stored in the frame memory, which is equivalent to the encoded bitstream buffer).
Yukio does not teach the “encoded bitstream buffer address” in the limitation “wherein: the input data comprises information with respect to an encoded bitstream buffer address; and the output data comprises a decoded picture obtained based on performing decoding with respect to encoded bitstream stored in the encoded bitstream buffer address”. However, Shinichi teaches an encoded bitstream stored in the encoded bitstream buffer address (Paragraph 0016, 0018, 0022 – “FIG. 2 shows the data structure of the MPEG4 bitstream data stored in the MPEG4 bitstream data storage memory 103b, as well as index data for data search…The index data 202 stores a frame type flag 202a, a time stamp 202b, and a pointer 202c as a set for each frame…The pointer 202c stores the start address of each frame of the bit stream data…the address pointer 103d indicating the playback position is set to the position 202a in the index data 202 which indicates the first frame of the bit stream data. Then, in step S303, the bit stream data indicated by the address pointer position is read, and in step S304, the MPEG4 decoder unit 102 executes the decoding process”; Note: input data comprises information with respect to the encoded bitstream stored in an address, which is equivalent to the encoded bitstream buffer address. The bitstream data storage memory is equivalent to the buffer. Additionally, decoding is performed with respect to the encoded bitstream stored in an address, which is equivalent to the encoded bitstream buffer address). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Shinichi to store the encoded bitstream in an encoded bitstream buffer address because it is common in the art that when data is stored in memory, it has a corresponding address to indicate where in the memory it is stored. The address ensures that the data can be retrieved later on for future processing.
Regarding claim 9, Yukio teaches the image processing method of claim 1. Yukio teaches an interrupt signal (Paragraph 0042 – “An interrupt signal is generated when the operation is completed”). Yukio does not teach receiving a power-OFF signal based on the interrupt signal. However, Shinichi combined with Yukio teaches receiving a power-OFF signal based on the interrupt signal (Shinichi: Paragraph 0026 – “the MPEG4 decoder unit 102 is powered on only when a playback instruction is received, and is powered off when the series of decoding and playback operations are complete, thereby making it possible to reduce unnecessary power consumption”; Note: the decoder is powered off when decoding is finished. In Yukio, an interrupt signal is sent when decoding is finished. Thus, when Shinichi and Yukio are combined, a power off signal would be received based on the interrupt signal that indicates that the decoding is finished). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Shinichi to receive a power-off signal based on an interrupt signal because “the power consumption of the MPEG decoder can be reduced to essentially zero. Furthermore, when the power is turned on or when a series of video playback is completed or stopped, the power supply to the MPEG decoder can be set to zero unless a playback instruction is given again, thereby alleviating the problem of heat countermeasures” (Shinichi: Paragraph 0042). In other words, turning the power off when the image processing is complete helps save computing resources and reduce overheating.
Regarding claim 11, Yukio teaches the system-on-chip of claim 10. Yukio further teaches wherein the processor is configured to store the plurality of input data in the input data buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: it is implied that a processor exists either comprising the memory controller or connected to it because the memory controller would not be able to work without a processor. Furthermore, the encoded data is equivalent to the input data, and the frame memory is equivalent to the input data buffer). Yukio does not teach wherein the processor is configured to apply a power-ON signal to the codec. However, Shinichi teaches wherein the processor is configured to apply a power-ON signal to the codec (Paragraph 0013, 0021-0022 – “A switch 107 supplies or stops power to the MPEG4 decoder 107 based on a control signal from the CPU 101…when a playback operation is instructed by pressing the playback button or the like on the operation unit 110, first, in step S301, the power supply to the MPEG4 decoder unit 102 is turned on…the address pointer 103d indicating the playback position is set to the position 202a in the index data 202 which indicates the first frame of the bit stream data.”; Note: the CPU turns on the power supply for the decoder). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Shinichi to have the processor apply a power on signal to the decoder because “power is supplied to the hardware decoding means that decodes the video stream for the period required to perform processing in response to user input instructions, thereby reducing power consumption and providing advantages in terms of heat generation countermeasures” (Shinichi: Paragraph 0008). In other words, being able to control the power for the decoder helps save energy.
Regarding claim 13, Yukio in view of Shinichi teaches the system-on-chip of claim 10. Yukio further teaches wherein the codec is configured to generate an output data with reference to the input data (Paragraph 0030 – “During decoding, the decoder 100 receives a bit stream from the code data bus COD7-0, decodes it, and outputs image data to the image data bus IMD19-0.”). Yukio does not teach wherein for each input data of the plurality of input data, the codec is configured to read the input data from a base address of the input data buffer. However, Shinichi teaches wherein for each input data of the plurality of input data, the codec is configured to read the input data from a base address of the input data buffer (Paragraph 0016, 0018-0022, 0025 – “FIG. 2 shows the data structure of the MPEG4 bitstream data stored in the MPEG4 bitstream data storage memory 103b, as well as index data for data search…The index data 202 stores a frame type flag 202a, a time stamp 202b, and a pointer 202c as a set for each frame…The pointer 202c stores the start address of each frame of the bit stream data…in step S302, the address pointer 103d indicating the playback position is set to the position 202a in the index data 202 which indicates the first frame of the bit stream data. Then, in step S303, the bit stream data indicated by the address pointer position is read, and in step S304, the MPEG4 decoder unit 102 executes the decoding process…If it is determined that the frame is not the final frame, the address pointer is advanced by one in step S308, and the process returns to step S303 to perform the bitstream reading process again”; Note: the pointer is the base/start address of the frame. The frame is input data, and the bitstream data storage memory is the input data buffer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Shinichi to read each input data from a base address because in the art, the base address indicates where the data starts. Logically, it would not make sense to read data from the middle or the end, so using the base address to locate and retrieve the data would be most beneficial for future processing.
Regarding claim 14, Yukio in view of Shinichi teaches the system-on-chip of claim 13. Yukio further teaches the input data comprises information with respect to an encoded bitstream buffer (Paragraph 0032-0033, 0043 – “FIG. 10 shows an example of the format of the coded data output from the encoder/decoder 40 to the coded data bus COD7-0. The coded data always begins with the main header. The code indicating the beginning of the main header is SOC (Start of Codestream) 51…The tile part header of the bitstream 560 is made up of SOT 53 indicating the start of the tile part, T0 and TP0 (Tile 0 header maker segment) 540 indicating the contents of the tile part header, and SOD (Start of Data) 55 indicating the start of data… The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: the coded data, which is the input data, contains information regarding where the encoded bitstream starts/is located. The encoded bitstream is stored in the frame memory, which is equivalent to a buffer); and the output data comprises a decoded picture obtained based on performing decoding with respect to encoded bitstream (Paragraph 0030 – “During decoding, the decoder 100 receives a bit stream from the code data bus COD7-0, decodes it, and outputs image data to the image data bus IMD19-0”) stored in the encoded bitstream buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: encoded data is stored in the frame memory, which is equivalent to the encoded bitstream buffer).
Yukio does not teach the “encoded bitstream buffer address” in the limitation “wherein: the input data comprises information with respect to an encoded bitstream buffer address; and the output data comprises a decoded picture obtained based on performing decoding with respect to encoded bitstream stored in the encoded bitstream buffer address”. However, Shinichi teaches an encoded bitstream stored in the encoded bitstream buffer address (Paragraph 0016, 0018, 0022 – “FIG. 2 shows the data structure of the MPEG4 bitstream data stored in the MPEG4 bitstream data storage memory 103b, as well as index data for data search…The index data 202 stores a frame type flag 202a, a time stamp 202b, and a pointer 202c as a set for each frame…The pointer 202c stores the start address of each frame of the bit stream data…the address pointer 103d indicating the playback position is set to the position 202a in the index data 202 which indicates the first frame of the bit stream data. Then, in step S303, the bit stream data indicated by the address pointer position is read, and in step S304, the MPEG4 decoder unit 102 executes the decoding process”; Note: input data comprises information with respect to the encoded bitstream stored in an address, which is equivalent to the encoded bitstream buffer address. The bitstream data storage memory is equivalent to the buffer. Additionally, decoding is performed with respect to the encoded bitstream stored in an address, which is equivalent to the encoded bitstream buffer address). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Shinichi to store the encoded bitstream in an encoded bitstream buffer address because it is common in the art that when data is stored in memory, it has a corresponding address to indicate where in the memory it is stored. The address ensures that the data can be retrieved later on for future processing.
Regarding claim 16, Yukio teaches the system-on-chip of claim 10. Yukio further teaches wherein the codec is powered-on before the plurality of input data is stored in the input data buffer (Paragraph 0047 – “After the decoding process starts, when the coded data to be input from the outside is ready, COFRM is set to `L` and the coded data is input using COMRDY and COJRDY”; Note: it is implied that a power-ON signal is received before storing the input data because the decoding process has already started even when it has not yet been confirmed that the input data is ready, and the decoding process cannot start without being powered on). Yukio does not teach the processor is configured to apply a power-ON signal to the codec. However, Shinichi teaches the processor is configured to apply a power-ON signal to the codec (Paragraph 0013, 0021 – “A switch 107 supplies or stops power to the MPEG4 decoder 107 based on a control signal from the CPU 101. when a playback operation is instructed by pressing the playback button or the like on the operation unit 110, first, in step S301, the power supply to the MPEG4 decoder unit 102 is turned on. This is done by an instruction signal 106 from the CPU 101”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Shinichi to have the processor send a power-on signal to the codec because “power is supplied to the hardware decoding means that decodes the video stream for the period required to perform processing in response to user input instructions, thereby reducing power consumption and providing advantages in terms of heat generation countermeasures” (Shinichi: Paragraph 0008). In other words, being able to control the power for the decoder helps save energy.
Regarding claim 18, Yukio teaches the system-on-chip of claim 10. Yukio further teaches wherein the processor is configured to receive the interrupt signal (Paragraph 0019 – “the decoding device interrupts the image processing device when it has decoded data”; Note: the processing device receives the interrupt signal). Yukio does not teach wherein the processor is configured to apply a power-OFF signal to the codec. However, Shinichi teaches wherein the processor is configured to apply a power-OFF signal to the codec (Paragraph 0013, 0026 – “A switch 107 supplies or stops power to the MPEG4 decoder 107 based on a control signal from the CPU 101…the MPEG4 decoder unit 102 is powered on only when a playback instruction is received, and is powered off when the series of decoding and playback operations are complete, thereby making it possible to reduce unnecessary power consumption”; Note: the decoder is powered off when decoding is finished). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Shinichi to apply a power-off signal because “the power consumption of the MPEG decoder can be reduced to essentially zero. Furthermore, when the power is turned on or when a series of video playback is completed or stopped, the power supply to the MPEG decoder can be set to zero unless a playback instruction is given again, thereby alleviating the problem of heat countermeasures” (Shinichi: Paragraph 0042). In other words, turning the power off when the image processing is complete helps save computing resources and reduce overheating.
Regarding claim 19, Yukio teaches an image processing device (Fig. 16, Paragraph 0021 – “an image processing apparatus having an encoding device or a decoding device, an interrupt is performed when encoding or decoding of one screen is completed”; Note: the device shown in Fig. 16, including the memory controller 82, frame memory 81, and encoder/decoder 40, is equivalent to the image processing device; see screenshot of Fig. 16 below), comprising:
a working memory comprising an input data buffer and an output data buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: the frame memory is equivalent to the working memory, and it would be obvious that the frame memory has an input data buffer and output data buffer, as the frame memory stores encoded/input data and decoded/output data respectively);
and a system-on-chip (Paragraph 0029 – “one-chip encoder/decoder 40”) configured to
perform an image processing operation with respect to the plurality of input data (Paragraph 0030 – “During decoding, the decoder 100 receives a bit stream from the code data bus COD7-0, decodes it, and outputs image data to the image data bus IMD19-0”; Note: decoding is the image processing operation, and the bitstream is the input data),
determine whether the image processing operation with respect to the plurality of input data has been finished by comparing a number of times the image processing operation is performed with a number of the plurality of input data (Paragraph 0003, 0042 – “the image to be processed is often divided into a number of rectangular blocks called tiles…if the number of input codes is less than the specified number of tiles (EOC is input earlier than the specified position), the tiles up to that point are decoded and the process ends. (An interrupt signal is generated when the operation is completed.)”; Note: the number of input codes is equivalent to the number of times the image processing operation is performed, and the number of tiles is equivalent to the number of input data, since the tiles are the data to be processed. The number of input codes is compared to the number of tiles to determine if the process is finished),
and generate an interrupt signal based on determining that the image processing operation is finished (Paragraph 0019, 0042 – “the decoding device interrupts the image processing device when it has decoded data…if the number of input codes is less than the specified number of tiles (EOC is input earlier than the specified position), the tiles up to that point are decoded and the process ends. (An interrupt signal is generated when the operation is completed.)”).
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Screenshot of Fig. 16 (taken from Yukio)
Yukio does not directly teach that the system-on-chip is configured to store a plurality of input data in an input data buffer and store a plurality of output data corresponding to the plurality of input data in the output data buffer. However, Yukio separately teaches a system-on-chip (Paragraph 0029 – “one-chip encoder/decoder 40”), storing a plurality of input data in an input data buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: encoded data (input data) is stored in the frame memory (input data buffer)), and storing a plurality of output data corresponding to the plurality of input data in the output data buffer (Paragraph 0043 – “The memory controller 82 encodes image data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81, and decodes the encoded data from the frame memory 81 using the encoder/decoder 40 and stores it in the frame memory 81”; Note: decoded data (output data) is stored in the frame memory (output data buffer)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the features of Yukio to have the processor be configured to store input data in an input data buffer and store output data in an output data buffer because logically, a processor is required to manage the data in the memory, and having a processor in the system-on-chip that is able to handle the storage would make the system-on-chip more efficient and capable since it would not have to rely on an external processor.
Furthermore, Yukio does not teach based on storing the plurality of input data being finished, perform an image processing operation with respect to the plurality of input data. However, Shinichi teaches based on storing the plurality of input data being finished, perform an image processing operation with respect to the plurality of input data (Paragraph 0016, 0018, 0021-0022 – “FIG. 2 shows the data structure of the MPEG4 bitstream data stored in the MPEG4 bitstream data storage memory 103b, as well as index data for data search… Reference numeral 202 denotes index data for searching the start position of each frame of the bit stream data 201. The index data 202 stores a frame type flag 202a, a time stamp 202b, and a pointer 202c as a set for each frame…when a playback operation is instructed by pressing the playback button or the like on the operation unit 110, first, in step S301, the power supply to the MPEG4 decoder unit 102 is turned on…the address pointer 103d indicating the playback position is set to the position 202a in the index data 202 which indicates the first frame of the bit stream data. Then, in step S303, the bit stream data indicated by the address pointer position is read, and in step S304, the MPEG4 decoder unit 102 executes the decoding process”; Note: it is implied that decoding (image processing operation) starts only after the input data is stored in the bitstream data storage memory (buffer) since the power supply is turned on in response to a playback operation; the playback operation logically can only occur if there is encoded data already stored to be played). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Shinichi to perform the image processing after storing all the input data because “power is supplied to the hardware decoding means that decodes the video stream for the period required to perform processing in response to user input instructions, thereby reducing power consumption and providing advantages in terms of heat generation countermeasures” (Shinichi: Paragraph 0008). In other words, it would waste power and time to have to wait for the input data to be stored, so it would be beneficial to only start processing once all the input data is ready.
Regarding claim 20, Yukio in view of Shinichi teaches the image processing device of claim 19. Yukio further teaches wherein the number of the plurality of input data is greater than the number of the interrupt signals (Paragraph 0042 – “if the number of input codes is less than the specified number of tiles (EOC is input earlier than the specified position), the tiles up to that point are decoded and the process ends. (An interrupt signal is generated when the operation is completed.)”; Note: only one interrupt signal is generated, and there are multiple input codes).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yukio in view of Seiji (JP 2005196395 A) and Gibson et al. (US 6311258 B1), hereinafter Seiji and Gibson respectively.
Regarding claim 8, Yukio teaches the image processing method of claim 7. Yukio further teaches wherein performing the image processing operation comprises: generating a first output data with reference to the first input data (Paragraph 0030 – “During decoding, the decoder 100 receives a bit stream from the code data bus COD7-0, decodes it, and outputs image data to the image data bus IMD19-0”). Yukio does not teach receiving another interrupt signal, the interrupt signal indicating a start of decoding of a first input data of the plurality of input data; reading the first input data from a base address of the input data buffer based on a value of a count resistor being increased. However, Seiji teaches receiving another interrupt signal, the interrupt signal indicating a start of decoding of a first input data of the plurality of input data (Paragraph 0004, 0027, 0029 – “The overall control CPU 11 sends a command to the codec CPU 20 via the bus 50 to cause the codec CPU 20 to perform codec processing of the data…The first command transmission/reception management task 111A in the overall control CPU 11A writes a command for codec processing (encoding processing or decoding processing) to the command write area 251 of the memory 25 of the codec CPU 20A via the bus 50, and issues an interrupt signal (causes an interrupt) to the codec CPU 20A…if it is a demodulation process, reads the command to the decoding process management task 212 and sends the command to start the decoding process management task 212”; Note: the codec receives an interrupt signal indicating a command, which is to start decoding the input data). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Seiji to have an interrupt signal for indicating the start of decoding input data for the benefit of “preventing the memory from becoming filled with unreceived control commands” (Seiji: Paragraph 0001). In other words, the interrupt signal helps with ensuring that the decoding will start immediately or soon and prevents delays.
Yukio modified by Seiji still does not teach reading the first input data from a base address of the input data buffer based on a value of a count resistor being increased. However, Gibson teaches reading the first input data from a base address of the input data buffer based on a value of a count resistor being increased (Col. 85 lines 12-15, 20-25, 29-31, 39-43 – “the buffer is operating in the JPEG (mode2) for JPEG decompression operation. In this case, single component data blocks are stored in the buffer, and pixel data blocks are retrieved from the buffer…A pixel counter 1360 is used to keep track of the number of pixels extracted from the single component blocks stored in the buffer. The output of the pixel counter is used to generate the read addresses 1348, 1349, 1350 and 1351, and the output rotate control signal 1304…An offset is added to bit 3 and 4 of the output of the pixel counter to calculate the single component block index for a particular block…The increment signal 1308 is used as the pixel counter increment signal to increment the pixel counter 1360. The pixel counter 1360 is incremented after a pixel has been successfully retrieved from the buffer”; Note: the pixel counter, which is equivalent to the count resistor, is increased as the data in the buffer is being read. The pixel counter is also used to calculate the read addresses, which are the base addresses of the data). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Gibson to read input data from a base address based on a value of a counter being increased because the base address indicates where the data starts and the counter helps keep track of how much data needs to be read, so using both the base address and counter efficiently ensures that the right amount of data is retrieved for processing.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yukio in view of Seiji and Sozo (JP 2001245159 A), hereinafter Sozo.
Regarding claim 17, Yukio teaches the system-on-chip of claim 16. Yukio further teaches the codec is configured to generating a first output data with reference to the first input data (Paragraph 0030 – “During decoding, the decoder 100 receives a bit stream from the code data bus COD7-0, decodes it, and outputs image data to the image data bus IMD19-0”). Yukio does not teach based on storing a first input data of the plurality of input data is finished, the processor is configured to increase a value of a count resistor of the codec, and transmit another interrupt signal to the codec, the interrupt signal indicating a start of decoding of the first input data; and the codec is configured to receive the interrupt signal, and based on the value of the count resistor being increased, read the first input data from a base address of the input data buffer. However, Seiji teaches the processor is configured to transmit another interrupt signal to the codec, the interrupt signal indicating a start of decoding of the first input data; and the codec is configured to receive the interrupt signal (Paragraph 0004, 0027, 0029 – “The overall control CPU 11 sends a command to the codec CPU 20 via the bus 50 to cause the codec CPU 20 to perform codec processing of the data…The first command transmission/reception management task 111A in the overall control CPU 11A writes a command for codec processing (encoding processing or decoding processing) to the command write area 251 of the memory 25 of the codec CPU 20A via the bus 50, and issues an interrupt signal (causes an interrupt) to the codec CPU 20A…if it is a demodulation process, reads the command to the decoding process management task 212 and sends the command to start the decoding process management task 212”; Note: the codec receives an interrupt signal from the control CPU indicating a command, which is to start decoding the input data). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Seiji to have an interrupt signal for indicating the start of decoding input data for the benefit of “preventing the memory from becoming filled with unreceived control commands” (Seiji: Paragraph 0001). In other words, the interrupt signal helps with ensuring that the decoding will start immediately or soon and prevents delays.
Yukio modified by Seiji still does not teach based on storing a first input data of the plurality of input data is finished, the processor is configured to increase a value of a count resistor of the codec, and the codec is configured to: based on the value of the count resistor being increased, read the first input data from a base address of the input data buffer. However, Sozo teaches based on storing a first input data of the plurality of input data is finished, the processor is configured to increase a value of a count resistor of the codec (Paragraph 0063 – “when data is input, the image bus I/F controller 2021 counts up the write counter of the buffer memory, and the data is stored at the address indicated by the write counter”; Note: the write counter, which is equivalent to the counter resistor, is increased by the image bus I/F controller based on the input data being stored. The image bus I/F controller is interpreted to be the processor since a controller requires a processor to function), and based on the value of the count resistor being increased, the codec is configured to read the first input data from a base address of the input data buffer (Paragraph 0055, 0063 – “The control signals for input data in the JPEG codec chip 4 include an Irql signal, which is an input request signal, and an Iackl signal, which is an input enable signal. The Irql signal and the Iackl signal are always "High" before the start of the image processing operation…when data is input, the image bus I/F controller 2021 counts up the write counter of the buffer memory, and the data is stored at the address indicated by the write counter. When outputting, the image bus I/F controller 2021 counts up the read counter of the buffer memory, and the data is read from the address indicated by the read counter”; Note: after the input data is written to the buffer and the write counter is increased, the input data is read from the address indicated by the read counter, which is the base address). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Sozo to have a counter indicate storage of input data for the benefit of being able to stop “data input when the difference reaches a predetermined value within the capacity of the buffer memory, that is, when it is determined that the buffer memory is full, thereby preventing data from overflowing from the buffer memory” (Sozo: Paragraph 0063). In other words, a counter is useful for ensuring that there is not a buffer overflow error, and it can also keep track of how much data has been stored, which is useful for locating the data later on. It also would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yukio to incorporate the teachings of Sozo to have the codec read the input data from a base address based on the count resister being increased because the value of the counter keeps track of how much data there is and thus can assist in locating and retrieving the target data.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamaguchi (US 20060165300 A1) teaches a method of decoding image data based on a count of the pieces of data decoded.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE HAU MA whose telephone number is (571)272-2187. The examiner can normally be reached M-Th 7-5:30.
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/MICHELLE HAU MA/ Examiner, Art Unit 2617 /KING Y POON/Supervisory Patent Examiner, Art Unit 2617
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