Prosecution Insights
Last updated: August 16, 2026
Application No. 18/767,451

SUBSTRATE PROCESSING APPARATUS

Non-Final OA §103
Filed
Jul 09, 2024
Priority
Jul 11, 2023 — RE 10-2023-0089544
Examiner
SIDDIQUEE, TAMEEM
Art Unit
Tech Center
Assignee
Semes Co., Ltd.
OA Round
1 (Non-Final)
62%
Grant Probability
Moderate
1-2
OA Rounds
1y 1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 62% of resolved cases
62%
Career Allowance Rate
144 granted / 233 resolved
+1.8% vs TC avg
Strong +38% interview lift
Without
With
+38.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
28 currently pending
Career history
264
Total Applications
across all art units

Statute-Specific Performance

§101
8.5%
-31.5% vs TC avg
§103
59.0%
+19.0% vs TC avg
§102
13.4%
-26.6% vs TC avg
§112
16.7%
-23.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 233 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Allowable Subject Matter Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirata et al (US PUB. 20200012254, herein Hirata) in view of Wang (US PUB. 20210405625). Regarding claim 1, Hirata teaches A substrate processing apparatus, comprising: a processing module unit comprising at least a first processing module and a second processing module which are configured to perform different processes on substrates (0021 “processing unit 2 includes a plurality of (ten in this example) processing modules PM1 to PM10 for performing predetermined vacuum processing on a wafer W, and a first transfer device 11 for sequentially transferring the wafer W to the processing modules PM1 to PM10. The first transfer device 11 includes a plurality of transfer modules TM1 to TM5. The transfer modules TM1 to TM5 respectively have containers 30a, 30b, 30c, 30d, and 30e, each having a hexagonal planar shape and maintained in a vacuum state, and transfer mechanisms 31a, 31b, 31c, 31d and 31e that are respectively provided in the containers 30a, 30b, 30c, 30d, and 30e and have an articulated structure”)7; a transfer module unit comprising a first transfer module configured to queue and transfer a first substrate that can only be loaded into the first processing module, and a second transfer module configured to queue and transfer a second substrate that can only be loaded into the second processing module, wherein either the first transfer module or the second transfer module can be used to queue and transfer a third substrate that can be loaded into both the first and second processing modules (0005 “a first transfer device configured to transfer a substrate to the processing modules; a loading/unloading unit including a load port configured to hold a substrate accommodating container accommodating a plurality of substrates and a second transfer device configured to load/unload a substrate to/from the processing unit; and a control unit configured to control the processing modules, the first transfer device, and the second transfer device, wherein the control unit is configured to control the substrates to be sequentially and serially transferred to the processing modules, and wherein, when an error has occurred in a certain processing module, the control unit executes: collecting a substrate that has been unloaded from the substrate accommodating container but has not been processed in the substrate accommodating container”, 0020, 0035). The cited prior art do not teach and a sequence adjustment unit configured to adjust a process sequence according to a process flow recipe such that at least some of the first substrate, the second substrate, and the third substrate, which are junior to a substrate being processed in the process sequence, are prioritized for queuing and transferring using the first transfer module or the second transfer module that is in an idle state or about to become an idle state. Wang teaches and a sequence adjustment unit configured to adjust a process sequence according to a process flow recipe such that at least some of the first substrate, the second substrate, and the third substrate, which are junior to a substrate being processed in the process sequence, are prioritized for queuing and transferring using the first transfer module or the second transfer module that is in an idle state or about to become an idle state (0145 “In some embodiments, the topology information, historical timing information, and/or sequence recipe changes over time. In some examples, one or more components are added to and/or removed from the substrate processing system which changes the topology information. In some embodiments, one or more transfer operations, processing operations, and/or cleaning operations become faster or slower over time which changes the historical timing information. In some embodiments, method 200B of FIG. 2B is repeated with updated topology information, updated historical timing information, and/or updated sequence recipe to generate one or more of an updated takt time, one or more updated queue times, and/or an updated schedule for processing substrates in the substrate processing system.” 0079 “The sequence recipe has a list of operations. The odd number of operations is to robot locations, where the first operation is the robot operation that picks up a substrate from the cassette docked at the load port. Even number of operations are to chamber locations. Sequence operation s is start time (Ss) (time stamp when the sequence operation s is started). For a robot sequence operation, Ss is the timestamp when robot starts picking the substrate from the previous location. For a chamber operation, Ss is the timestamp when the process recipe (e.g., processing operation in the processing chamber) is started. The process recipe duration for sequence operation s is Ps. Queue time for operation s is Qs and is the duration for substrate staying in chamber for sequence operation s after process recipe is completed. Clean recipe duration for sequence operation s is Cs. Sequence operation s end time is Es (e.g., timestamp when the sequence operation is ended). For a robot sequence operation Es is the timestamp when the robot finishes picking substrate from the previous operation to the robot location, move to the location for the next sequence operation, put to empty location in next operation, or swap with the substrate in the next operation. For the chamber operation, Es is the timestamp when the process recipe and queue time for that operation are completed.”, 0145 “in some embodiments, the topology information, historical timing information, and/or sequence recipe changes over time. In some examples, one or more components are added to and/or removed from the substrate processing system which changes the topology information. In some embodiments, one or more transfer operations, processing operations, and/or cleaning operations become faster or slower over time which changes the historical timing information. In some embodiments, method 200B of FIG. 2B is repeated with updated topology information, updated historical timing information, and/or updated sequence recipe to generate one or more of an updated takt time, one or more updated queue times, and/or an updated schedule for processing substrates in the substrate processing system.”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to have modified the teachings of Hirata with the teachings of Wang since Wang teaches a means for “improved system throughput and improved substrate-to-substrate consistency” (0018). Regarding claim 2, the cited prior art teach The substrate processing apparatus of claim 1. Hirata teaches wherein when the process sequence according to the process flow recipe is such that the first substrate is queued and transferred first and then the second substrate is queued and transferred by the first transfer module, the sequence adjustment unit adjusts the process sequence such that the queuing and transferring of the second substrate is prioritized using the second transfer module which is in an idle state or about to become an idle state; or when the process sequence according to the process flow recipe is such that the second substrate queued and transferred first and then the first substrate is queued and transferred by the second transfer module, the sequence adjustment unit adjusts the process sequence such that the queuing and transferring of the first substrate is prioritized using the first transfer module which is in an idle state or about to become an idle state (0037 “If an error occurs during execution of a processing recipe of a certain processing module, the error detection unit 123 detects the error and notifies the transfer control unit 121 and the process control unit 122 of the error. When the error is notified, the control unit 4 operates in an error occurrence mode.”, 0038 “In the error occurrence mode, the unprocessed substrate collection instruction unit 124 is activated. The unprocessed substrate collection instruction unit 124 is displayed as an unprocessed substrate collection screen on the display device 104, and the transfer control unit 121 issues an unprocessed wafer collection instruction by pressing “OK” on the unprocessed substrate collection screen. The second transfer device 24 and the transfer mechanism 31a of the transfer module TM1 are controlled based on this instruction such that wafers W that have been unloaded from the load port 22 (FOUP 20) but have not been processed can be collected in the FOUP 20. The unprocessed wafers W exist at the loading/unloading unit 3, on the second transfer device 24, in the aligner module 23, and in the load-lock chamber LLM1.” 0039 “The transfer control unit 121 and the process control unit 122 control the processing module and the transfer unit such that the processing of the preceding wafer that has passed through the processing module in which the error has occurred can be continued” 0040-0046). Regarding claim 3, the cited prior art teach The substrate processing apparatus of claim 1. The cited prior art teach wherein when the process sequence according to the process flow recipe is such that the first substrate is queued and transferred by the first transfer module first, or the second substrate is queued and transferred by the second transfer module first, or both the first substrate and the second substrate are queued and transferred by the first transfer module and the second transfer module respectively (Hirata 0037 “If an error occurs during execution of a processing recipe of a certain processing module, the error detection unit 123 detects the error and notifies the transfer control unit 121 and the process control unit 122 of the error. When the error is notified, the control unit 4 operates in an error occurrence mode.”, 0038 “In the error occurrence mode, the unprocessed substrate collection instruction unit 124 is activated. The unprocessed substrate collection instruction unit 124 is displayed as an unprocessed substrate collection screen on the display device 104, and the transfer control unit 121 issues an unprocessed wafer collection instruction by pressing “OK” on the unprocessed substrate collection screen. The second transfer device 24 and the transfer mechanism 31a of the transfer module TM1 are controlled based on this instruction such that wafers W that have been unloaded from the load port 22 (FOUP 20) but have not been processed can be collected in the FOUP 20. The unprocessed wafers W exist at the loading/unloading unit 3, on the second transfer device 24, in the aligner module 23, and in the load-lock chamber LLM1.” 0039 “The transfer control unit 121 and the process control unit 122 control the processing module and the transfer unit such that the processing of the preceding wafer that has passed through the processing module in which the error has occurred can be continued” 0040-0046), queuing and transferring of the third substrate is scheduled to be performed after queuing and transferring of the first substrate, the second substrate, or the first and second substrates are finished, the sequence adjustment unit adjusts the process sequence so that queuing and transferring of the third substrate can be performed preferentially using the first transfer module or the second transfer module that is in an idle state, or the first transfer module or the second transfer module that is about to become an idle state (Wang 0145 “In some embodiments, the topology information, historical timing information, and/or sequence recipe changes over time. In some examples, one or more components are added to and/or removed from the substrate processing system which changes the topology information. In some embodiments, one or more transfer operations, processing operations, and/or cleaning operations become faster or slower over time which changes the historical timing information. In some embodiments, method 200B of FIG. 2B is repeated with updated topology information, updated historical timing information, and/or updated sequence recipe to generate one or more of an updated takt time, one or more updated queue times, and/or an updated schedule for processing substrates in the substrate processing system.” 0079 “The sequence recipe has a list of operations. The odd number of operations is to robot locations, where the first operation is the robot operation that picks up a substrate from the cassette docked at the load port. Even number of operations are to chamber locations. Sequence operation s is start time (Ss) (time stamp when the sequence operation s is started). For a robot sequence operation, Ss is the timestamp when robot starts picking the substrate from the previous location. For a chamber operation, Ss is the timestamp when the process recipe (e.g., processing operation in the processing chamber) is started. The process recipe duration for sequence operation s is Ps. Queue time for operation s is Qs and is the duration for substrate staying in chamber for sequence operation s after process recipe is completed. Clean recipe duration for sequence operation s is Cs. Sequence operation s end time is Es (e.g., timestamp when the sequence operation is ended). For a robot sequence operation Es is the timestamp when the robot finishes picking substrate from the previous operation to the robot location, move to the location for the next sequence operation, put to empty location in next operation, or swap with the substrate in the next operation. For the chamber operation, Es is the timestamp when the process recipe and queue time for that operation are completed.”, 0145 “in some embodiments, the topology information, historical timing information, and/or sequence recipe changes over time. In some examples, one or more components are added to and/or removed from the substrate processing system which changes the topology information. In some embodiments, one or more transfer operations, processing operations, and/or cleaning operations become faster or slower over time which changes the historical timing information. In some embodiments, method 200B of FIG. 2B is repeated with updated topology information, updated historical timing information, and/or updated sequence recipe to generate one or more of an updated takt time, one or more updated queue times, and/or an updated schedule for processing substrates in the substrate processing system.”). Regarding claim 4, the cited prior art teach The substrate processing apparatus of claim 3. Hirata teaches wherein when the process sequence according to the process flow recipe in the first transfer module is such that queuing and transferring of the third substrate is performed after finishing queuing and transferring of the first substrate, the sequence adjustment unit adjusts the process sequence so that queuing and transferring of the third substrate can be performed preferentially by using the second transfer module, and wherein when queuing and transferring of the first substrate is finished by the first transfer module and queuing and transferring of the third substrate is finished by the second transfer module, the sequence adjustment unit re-adjusts the process sequence so that queuing and transferring of the third substrate can be performed preferentially by using the first transfer module (“[0045] (5) Instruction for performing remaining processing on the error wafer after the recovery in the processing modules. [0046] The post-restoration processing management screen is used for managing post-restoration processing such as re-execution (recovery) after the restoration, or the like. For example, a retreated error wafer is managed, and a state of an error wafer or navigation of a restoration procedure is displayed. [0047] After the operation of the post-restoration processing instruction unit 125 is carried out, the substrate retreat position selection unit 126 is activated. The substrate retreat position selection unit 126 is displayed as a substrate retreat position selection screen on the post-restoration processing management screen of the display device 104. By selecting a predetermined position from the positions to which the wafer can be retreated displayed on the substrate retreat position selection screen, the transfer control unit 121 causes the transfer module to retreat the error wafer. The retreat position may be the delivery units 41 to 44 and/or a processing module used as a standby module among the processing modules PM1 to PM10.”) Regarding claim 8, the cited prior art teach The substrate processing apparatus of claim 3. Wang teaches wherein when the process sequence according to the process flow recipe is such that queuing and transferring of the first substrate and the second substrate are performed by the first and second transfer module respectively first, and then queuing and transferring of the third substrate is performed after the queuing and transferring of either the first substrate or the second substrate is finished by either the first transfer module or the second transfer module, the sequence adjustment unit adjusts the process sequence so that queuing and transferring of the third substrate can be preferentially performed by any one out of the first transfer module and the second transfer module, whichever finishes the transferring first (0145 “In some embodiments, the topology information, historical timing information, and/or sequence recipe changes over time. In some examples, one or more components are added to and/or removed from the substrate processing system which changes the topology information. In some embodiments, one or more transfer operations, processing operations, and/or cleaning operations become faster or slower over time which changes the historical timing information. In some embodiments, method 200B of FIG. 2B is repeated with updated topology information, updated historical timing information, and/or updated sequence recipe to generate one or more of an updated takt time, one or more updated queue times, and/or an updated schedule for processing substrates in the substrate processing system.” 0079 “The sequence recipe has a list of operations. The odd number of operations is to robot locations, where the first operation is the robot operation that picks up a substrate from the cassette docked at the load port. Even number of operations are to chamber locations. Sequence operation s is start time (Ss) (time stamp when the sequence operation s is started). For a robot sequence operation, Ss is the timestamp when robot starts picking the substrate from the previous location. For a chamber operation, Ss is the timestamp when the process recipe (e.g., processing operation in the processing chamber) is started. The process recipe duration for sequence operation s is Ps. Queue time for operation s is Qs and is the duration for substrate staying in chamber for sequence operation s after process recipe is completed. Clean recipe duration for sequence operation s is Cs. Sequence operation s end time is Es (e.g., timestamp when the sequence operation is ended). For a robot sequence operation Es is the timestamp when the robot finishes picking substrate from the previous operation to the robot location, move to the location for the next sequence operation, put to empty location in next operation, or swap with the substrate in the next operation. For the chamber operation, Es is the timestamp when the process recipe and queue time for that operation are completed.”, 0145 “in some embodiments, the topology information, historical timing information, and/or sequence recipe changes over time. In some examples, one or more components are added to and/or removed from the substrate processing system which changes the topology information. In some embodiments, one or more transfer operations, processing operations, and/or cleaning operations become faster or slower over time which changes the historical timing information. In some embodiments, method 200B of FIG. 2B is repeated with updated topology information, updated historical timing information, and/or updated sequence recipe to generate one or more of an updated takt time, one or more updated queue times, and/or an updated schedule for processing substrates in the substrate processing system.”). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMEEM SIDDIQUEE whose telephone number is (571)272-1627. The examiner can normally be reached M-F 8:00-4:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Lo can be reached at (571) 272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAMEEM D SIDDIQUEE/ Primary Examiner Art Unit 2116
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Prosecution Timeline

Jul 09, 2024
Application Filed
Jul 29, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
62%
Grant Probability
99%
With Interview (+38.1%)
3y 2m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 233 resolved cases by this examiner. Grant probability derived from career allowance rate.

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