Prosecution Insights
Last updated: October 23, 2026
Application No. 18/767,476

SERIALIZER-DESERIALIZER SENSOR SYSTEM CONFIGURATIONS

Non-Final OA §103
Filed
Jul 09, 2024
Priority
Mar 15, 2024 — provisional 63/565,959
Examiner
RIVERA VARGAS, MANUEL A
Art Unit
2857
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Analog Devices Inc.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
525 granted / 648 resolved
+13.0% vs TC avg
Moderate +12% lift
Without
With
+12.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
40 currently pending
Career history
691
Total Applications
across all art units

Statute-Specific Performance

§101
29.1%
-10.9% vs TC avg
§103
20.2%
-19.8% vs TC avg
§102
27.3%
-12.7% vs TC avg
§112
20.0%
-20.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 648 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gredegard et al. (US 2015/0347607, hereinafter Gre) and further in view of Qiang (US 2023/0333615, hereinafter Qia). Regarding claim 1, Gre discloses a method by a serializer of a sensor circuit (see para. 0047), comprising: receiving an indication indicating the sensor circuit is connected to a controller circuit (see para. 0050 and 0054); identifying a sensor identifier associated with the sensor circuit from an internal memory of the serializer (see para. 0045); transmitting the sensor identifier from the serializer to the controller circuit to a deserializer (see para. 0054); transmitting sensor calibration data from the memory circuit on the sensor circuit to the controller circuit (see para. 0055); and transmitting sensor data to the deserializer (see para. 0010 and 0047 and 0050). However, Gre fails to disclose to identify and load a sensor circuit driver associated with the sensor identifier. Qia discloses discloses to identify and load a sensor circuit driver (see para. 0090 and 0128). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gre’s invention to incorporate Qia’s teachings of loading sensor circuit drivers for the benefit of initializing the controllers operation. Regarding claim 2, Gre in view of Qia discloses the method of claim 1, further comprising transmitting circuit data for one or more of the serializer, the deserializer and a sensor circuit initialization sequence (see Gre abstract and para. 0011, 0013 and 0050). Regarding claim 3, Gre in view of Qia discloses the method of claim 2, further comprising receiving signals, from the controller circuit, for initializing one or more of the serializer or the sensor circuit (see Gre abstract and para. 0010 and 0013). Regarding claim 4, Gre in view of Qia discloses the method of claim 1, further comprising loading serializer data for the serializer and a sensor circuit initialization sequence (see Gre para. 0013). Regarding claim 5, Gre in view of Qia discloses the method of claim 4, further comprising initializing one or more of the serializer or the sensor circuit (see Gre para. 0017 and 0050). Regarding claim 6, Gre in view of Qia discloses the method of claim 1, wherein the sensor identifier is stored in a serializer one-time programmable (OTP) memory (see Gre abstract and para. 0024). Regarding claim 7, Gre in view of Qia discloses the method of claim 6, wherein the sensor identifier is a unique identifier associated with the serializer or the sensor circuit (see abstract and para. 0010 and 0047). Regarding claim 8, Gre discloses a serializer of a sensor circuit (see para. 0047), comprising: a one time programmable (OTP) memory having a sensor identifier (see abstract and para. 0024); wherein the serializer is configured to: receive an indication indicating the sensor circuit is connected to a controller circuit (see para. 0050 and 0054); identify the sensor identifier associated with the sensor circuit from an internal memory of the serializer (see para. 0045); transmit the sensor identifier from the serializer to the controller circuit to a deserializer (see para. 0054); transmit sensor calibration data from the memory circuit on the sensor circuit to the controller circuit (see para. 0055); and transmit sensor data to the deserializer (see para. 0010 and 0047 and 0050). However, Gre fails to disclose to identify and load a sensor circuit driver associated with the sensor identifier. Qia discloses discloses to identify and load a sensor circuit driver (see para. 0090 and 0128). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gre’s invention to incorporate Qia’s teachings of loading sensor circuit drivers for the benefit of initializing the controllers operation. Regarding claim 9, Gre in view of Qia discloses the serializer of claim 8, wherein the serializer is further configured to transmit circuit data for one or more of the serializer, the deserializer and a sensor circuit initialization sequence (see Gre abstract and para. 0011, 0013 and 0050). Regarding claim 10, Gre in view of Qia discloses the serializer of claim 9, wherein the serializer is further configured to receive signals, from the controller circuit, for initializing one or more of the serializer or the sensor circuit (see Gre abstract and para. 0010 and 0013). Regarding claim 11, Gre in view of Qia discloses the serializer of claim 8, wherein the serializer is further configured to load serializer data for the serializer and a sensor circuit initialization sequence (see Gre para. 0013). Regarding claim 12, Gre in view of Qia discloses the serializer of claim 8, further comprising a microcontroller configured to initialize one or more of the serializer or the sensor circuit (see Gre para. 0045). Regarding claim 13, Gre in view of Qia discloses the serializer of claim 8, wherein the sensor identifier is a unique identifier associated with the serializer (see abstract and para. 0010 and 0047). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANUEL A RIVERA VARGAS whose telephone number is (571)270-7870. The examiner can normally be reached M-F 9:00-6:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shelby Turner can be reached at 571-272-6334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MANUEL A RIVERA VARGAS/Primary Examiner, Art Unit 2857
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Prosecution Timeline

Jul 09, 2024
Application Filed
Sep 30, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
93%
With Interview (+12.1%)
3y 0m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 648 resolved cases by this examiner. Grant probability derived from career allowance rate.

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