DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements submitted on 9 Jul 2024 and 9 Jun 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1-14 are objected to because of the following informalities:
Claim 1: recites the limitation "the other of the differential input pair" in line 10. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-14 depend from Claim 1 and thus have at least the same defect.
Claim 2: "outputting the reference voltage node" should be replaced with "outputting the reference voltage".
Claims 3-4 depend from Claim 2 and thus have at least the same defect.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-12, 14-15, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (CN 104166421 A) in view of Zarei (US 8947067 B1).
Regarding Claim 1, Wu discloses reference voltage generator circuit (100A-B, Fig 2), comprising: a resistor circuit (R1, R2, Rb, Fig 2) configured to be electrically connected between a first node (R1 connected to node Vbg, Fig 2) and a second node (R1 connected between Vbg and node A, Fig 2) and between the first node and a third node (R1 connected between Vbg and node B, Fig 2), the resistor circuit including a variable resistor (Rb, Fig 2/4) whose resistance value varies according to a first control signal (Rb is controlled by signals from 106, Fig 3-4); a differential amplifier circuit (102, Fig 2) in which one of a differential input pair is electrically connected to the second node (+ input of 102 is connected to A, Fig 2) and the other of the differential input pair is electrically connected to the third node (- input of 102 is connected to B, Fig 2), the differential amplifier circuit configured to generate a reference voltage at an output node (102 generates reference voltage Vbg at its output, Fig 2); a current source circuit (Q1-2, Fig 2) configured to be electrically connected between the second node and a fourth node (Q1 connected between A and ground, Fig 2) and between the third node and the fourth node (Q2 connected between B and ground, Fig 2).
Wu does not disclose an adjuster circuit configured to be electrically connected to the output node, the adjuster circuit configured to generate the first control signal by comparing at least two target voltages with the reference voltage.
Zarei teaches a conventional automatic bandgap voltage calibration circuit for use in a bandgap voltage generator circuit (406, Fig 5/6) including an adjuster circuit (406, Fig 5/6) configured to be electrically connected to the output node (406 is connected to V_BG through R2, Fig 5), the adjuster circuit configured to generate the first control signal (e.g. S1 of 502 controls 506, Fig 5/6) by comparing at least two target voltages with the reference voltage (comparators 614, 616, 616, & 618 compare voltages Vref1-4 with Vout, Fig 6).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the automatic bandgap voltage calibration circuit in Wu, as taught by Zarei, as it provides the advantage of reducing the effect of process variations on the bandgap voltage and improve accuracy (abstract of Zarei).
Regarding Claim 7, the combination of Wu and Zarei teaches all of the limitations of Claim 1 above, and further teaches
Regarding Claim 8, the combination of Wu and Zarei teaches all of the limitations of Claim 1 above, and further teaches wherein the current source circuit includes: a first transistor configured to be connected between the second node and the fourth node (Q1, Fig 2 of Wu); and a first resistor and a second transistor configured to be connected between the third node and the fourth node (Q2, Fig 2 of Wu), and the first transistor and the second transistor are each configured to be diode connected (Q1-2 are diode connected, Fig 2 of Wu).
Regarding Claim 9, the combination of Wu and Zarei teaches all of the limitations of Claim 1 above, and further teaches wherein the fourth node is a ground potential node (Fig 2 of Wu).
Regarding Claim 10, the combination of Wu and Zarei teaches all of the limitations of Claim 1 above, and further teaches wherein the output node is configured to be electrically connected to the first node (A connected to Vbg, Fig 2 of Wu).
Regarding Claim 11, the combination of Wu and Zarei teaches all of the limitations of Claim 1 above, and further teaches wherein the at least two target voltages include a first target voltage (e.g. Vref1, Fig 6 of Zarei) and a second target voltage (e.g. Vref2, Fig 6 of Zarei), and the adjuster circuit includes: a first comparator circuit configured to compare the reference voltage with the first target voltage (e.g. 614 compares Vref1 with Vout, Fig 6 of Zarei); and a second comparator circuit configured to compare the reference voltage with the second target voltage voltage (e.g. 616 compares Vref2 with Vout, Fig 6 of Zarei).
Regarding Claim 12, the combination of Wu and Zarei teaches all of the limitations of Claim 1 above, and further teaches wherein the adjuster circuit includes a resistor series-connected circuit configured to generate the at least two target voltages by resistively dividing a first power supply voltage (resistor ladder Rref1-4 divide VDD into Vref1-4, Fig 6 of Zarei).
Regarding Claim 14, the combination of Wu and Zarei teaches all of the limitations of Claim 11 above, and further teaches the adjuster circuit includes a logic circuit configured to generate the first control signal according to an output signal of the first comparator circuit and an output signal of the second comparator circuit (105, Fig 2/6 of Zarei).
Regarding Claim 15, Wu discloses a semiconductor integrated circuit ("the band gap reference source adjusting circuit, self-alignment adjusting circuit and band-gap reference source circuit are integrated in the same silicon wafer", Fig 2, [0009]), comprising: a reference voltage generator circuit (100A-B, Fig 2); wherein the reference voltage generator circuit includes: a resistor circuit (R1, R2, Rb, Fig 2) configured to be electrically connected between a first node (R1 connected to node Vbg, Fig 2) and a second node (R1 connected between Vbg and node A, Fig 2) and between the first node and a third node (R1 connected between Vbg and node B, Fig 2), the resistor circuit including a variable resistor (Rb, Fig 2/4) whose resistance value varies according to a first control signal (Rb is controlled by signals from 106, Fig 3-4); a differential amplifier circuit (102, Fig 2) in which one of a differential input pair is electrically connected to the second node (+ input of 102 is connected to A, Fig 2) and the other of the differential input pair is electrically connected to the third node (- input of 102 is connected to B, Fig 2), the differential amplifier circuit configured to generate a reference voltage at an output node (102 generates reference voltage Vbg at its output, Fig 2); a current source circuit (Q1-2, Fig 2) configured to be electrically connected between the second node and a fourth node (Q1 connected between A and ground, Fig 2) and between the third node and the fourth node (Q2 connected between B and ground, Fig 2).
Wu does not disclose a first circuit configured to be connected to the reference voltage generator circuit, an adjuster circuit configured to be electrically connected to the output node, the adjuster circuit configured to generate the first control signal by comparing at least two target voltages with the reference voltage, and the first circuit is configured to operate by receiving supply of the reference voltage from the reference voltage generator circuit.
Zarei teaches a conventional automatic power control circuit with a bandgap voltage reference (100/116, Fig 1) including semiconductor integrated circuit ("FIG. 1, for example, is an example of a circuit design 412 that may incorporate the bandgap voltage reference source 402 of the present disclosure. The circuit design 412, in turn, may be incorporated on an Integrated Circuit (IC) chip 422a.", Fig 1 & 4A-C, Col 6[4-7]), an adjuster circuit (406, Fig 5/6) configured to be electrically connected to the output node (406 is connected to V_BG through R2, Fig 5), the adjuster circuit configured to generate the first control signal (502 controls R2, Fig 5/6) by comparing at least two target voltages with the reference voltage (comparators 614, 616, 616, & 618 compare voltages Vref1-4, Fig 6), and the first circuit is configured to operate by receiving supply of the reference voltage from the reference voltage generator circuit (118 receives Vref from bandgap voltage reference circuit 116, Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the automatic power control circuit with a bandgap voltage reference in Wu, as taught by Zarei, as it provides the advantage of reducing the effect of process variations on the bandgap voltage and improve accuracy (abstract of Zarei).
Regarding claim 19, it is rejected for the same reasons as stated above for Claim 11.
Regarding Claim 20, it is rejected for the same reasons as stated above for Claim 12.
Claims 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (CN 104166421 A) in view of Zarei (US 8947067 B1) and further in view of Wortel (US 10013013 B1).
Regarding Claim 2, the combination of Wu and Zarei teaches all of the limitations of Claim 1 above, and further teaches wherein the adjuster circuit is configured to generate the second control signal (e.g. S2 of 502 controls R2, Fig 5/6 of Zarei) according to a result of comparison between the at least two target voltages and the reference voltage (comparators 614, 616, 616, & 618 compare four voltages Vref1-4, Fig 6 of Zarei).
The combination of Wu and Zarei does not teach a switch circuit configured to connect the output node to a reference voltage node according to a second control signal, the reference voltage node being a node for outputting the reference voltage.
Regarding claim 16, it is rejected for the same reasons as stated above for Claim 2.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wu (CN 104166421 A) in view of Zarei (US 8947067 B1) and further in view of Abugharbieh (US 8638084 B1).
Regarding Claim 13, the combination of Wu and Zarei teaches all of the limitations of Claim 11 above, and further teaches wherein the adjuster circuit includes a resistor series-connected circuit configured to generate the at least two target voltages by resistively dividing a first power supply voltage (resistor ladder Rref1-4 divide VDD into Vref1-4, Fig 6 of Zarei).
The combination of Wu and Zarei does not teach the first comparator circuit and the second comparator circuit are configured to operate by receiving supply of a second power supply voltage from a node independent of a node from which the first power supply voltage is configured to be supplied.
Abugharbieh (US 8638084 B1) Abugharbieh teaches a conventional bandgap reference circuit (see Fig 5) including the adjuster circuit includes a resistor series-connected circuit (resistor ladder 509, Fig 5) configured to generate the at least two target voltages (511-514, Fig 5) by resistively dividing a first power supply voltage ("reference voltage 510 may, but need not, be a supply level voltage" and "reference voltage ("Vref") 510 may be an externally supplied reference voltage.", Fig 5, Col 9[29-30] & Col 8[41-2]), and the first comparator circuit and the second comparator circuit are configured to operate by receiving supply of a second power supply voltage from a node independent of a node from which the first power supply voltage is configured to be supplied (comparators 521-524 have a different power supply than 509, "reference voltage 510 may, but need not, be a supply level voltage" and "reference voltage ("Vref") 510 may be an externally supplied reference voltage." while the rest of the circuit is supplied by Vcc, Fig 3/5, Col 8[41-2]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the bandgap reference circuit in Wu, as taught by Abugharbieh, as it provides the advantage of adding noise isolation to the circuit.
Allowable Subject Matter
Claims 3-6 & 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the combination of Wu, Zarei, and Wortel teaches all of the limitations of Claim 2 above.
The combination of Wu, Zarei, and Wortel does not teach the switch circuit is configured to connect the reference voltage node to a ground potential node when disconnecting the output node from the reference voltage node.
Prior art Carvalho (US 20060043957 A1) and Abugharbieh (US 8638084 B1) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach or fairly suggest “the switch circuit is configured to connect the reference voltage node to a ground potential node when disconnecting the output node from the reference voltage node."
Regarding Claim 4, the combination of Wu, Zarei, and Wortel teaches all of the limitations of Claim 2 above, and further teaches the at least two target voltages include a first target voltage (e.g. Vref1, Fig 6 of Zarei) and a second target voltage (e.g. Vref2, Fig 6 of Zarei), and the switch circuit is configured to connect the output node to the reference voltage node (S4, Fig 2 of Wortel).
The combination of Wu, Zarei, and Wortel does not teach when the reference voltage is a voltage between the first target voltage and the second target voltage, and the switch circuit is configured to disconnect the output node from the reference voltage node when the reference voltage is not a voltage between the first target voltage and the second target voltage.
Prior art Carvalho (US 20060043957 A1) and Abugharbieh (US 8638084 B1) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach or fairly suggest “when the reference voltage is a voltage between the first target voltage and the second target voltage, and the switch circuit is configured to disconnect the output node from the reference voltage node when the reference voltage is not a voltage between the first target voltage and the second target voltage."
Regarding Claim 5, the combination of Wu and Zarei teaches all of the limitations of Claim 1 above, and further teaches a second variable resistor configured to be connected between the first node and the third node (Rb is connected to B and to the output of the amplifier through 100B, Fig 2).
The combination of Wu and Zarei does not teach wherein the resistor circuit includes: a first variable resistor configured to be connected between the first node and the second node.
Prior art Wortel (US 10013013 B1), Carvalho (US 20060043957 A1), and Abugharbieh (US 8638084 B1) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach or fairly suggest “wherein the resistor circuit includes: a first variable resistor configured to be connected between the first node and the second node; and a second variable resistor configured to be connected between the first node and the third node."
Regarding Claim 6, the combination of Wu and Zarei teaches all of the limitations of Claim 1 above, and further teaches the at least two target voltages include a first target voltage (e.g. Vref1, Fig 6 of Zarei) and a second target voltage (e.g. Vref2, Fig 6 of Zarei).
The combination of Wu and Zarei does not teach the resistor circuit is configured to increase a resistance value between the first node and the second node and a resistance value between the first node and the third node when the reference voltage is lower than the first target voltage and the second target voltage, the resistor circuit is configured to maintain the resistance value between the first node and the second node and the resistance value between the first node and the third node when the reference voltage is a voltage between the first target voltage and the second target voltage, and the resistor circuit is configured to reduce the resistance value between the first node and the second node and the resistance value between the first node and the third node when the reference voltage is higher than the first target voltage and the second target voltage.
Prior art Wortel (US 10013013 B1), Carvalho (US 20060043957 A1), and Abugharbieh (US 8638084 B1) are considered to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach or fairly suggest “the resistor circuit is configured to increase a resistance value between the first node and the second node and a resistance value between the first node and the third node when the reference voltage is lower than the first target voltage and the second target voltage, the resistor circuit is configured to maintain the resistance value between the first node and the second node and the resistance value between the first node and the third node when the reference voltage is a voltage between the first target voltage and the second target voltage, and the resistor circuit is configured to reduce the resistance value between the first node and the second node and the resistance value between the first node and the third node when the reference voltage is higher than the first target voltage and the second target voltage."
Regarding Claim 17, it is indicated as allowable for the same reasons as stated above for Claim 4.
Regarding claim 18, it is indicated as allowable for the same reasons as stated above for Claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off.
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/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 4/03/2026
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