DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. §112(f) in this application.
Claim Objections
Applicant is advised that should claim 1 be found allowable, claim 5 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. Furthermore, should claim 11 be found allowable, claim 19 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112(d)
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 19 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 11
Claim 19
11. An operation method of a storage device comprising…
…checking whether the current power consumption of each of the plurality of memory devices exceeds the power budget of the storage device…
…performing a command according to the plurality of commands based on the determined operation order based on the current power consumption of each of the plurality of memory devices not exceeding the power budget of the storage device, and…
…updating the current power consumption of each of the plurality of memory devices...
19. The operation method of the storage device of claim 11, further comprising…
…checking whether the current power consumption of each of the plurality of memory devices exceeds the power budget of the storage device…
…performing one or more commands of the plurality of the commands according to the operation order based on the current power consumption of each of the plurality of memory devices not exceeding the power budget of the storage device, and…
…updating the current power consumption of each of the plurality of memory devices.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections – 35 USC §112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites, “the external factors”. However, claim 1 introduces “external factors of each of the plurality of memory devices” and claim 5 introduces “external factors that affect the power consumptions of the plurality of memory devices”. Accordingly, it is unclear which “external factors” the recitation of “the external factors” from claim 6 refers to, or if, in fact, the two recitations in claims 1 and 5 actually refer to the same “external factors”. Accordingly, the scope of the claim cannot be determined and the claim is indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-11 and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2020/0104062 A1 (Cho) in view of US Patent Application Publication No. US 2019/0212932 A1 (Lee) in further view of US Patent Application Publication No. US 2019/0051341 A1 (Li) as motivated by the paper by Jason Heidecker of JPL of NASA titled, “MRAM Technology Status” as published on 2 January 2013 (Heidecker) in further view of US Patent Application Publication No. US 2022/0382466 A1 (Zhu) in further view of US Patent Application Publication No. US 2022/0157350 A1 (Guo).
Regarding claim 1 and analogous claims 11:
Cho discloses, a storage device (1000) comprising: a plurality of memory devices (see (1100) in [Fig. 2] with a plurality of memory devices (MD1-MDk) on each channel (CH1-CHi) [Fig. 2]), and a storage controller (1200) configured to receive, from an external host device (2000), a plurality of commands that operate the plurality of memory devices ([Fig. 9] shows the commands received from the CPU (200) of the host device (2000) [0086]. The power is supplied to the storage device (1000) from VCCE [Fig. 1] generate, based on a plurality of characteristic information respectively corresponding to the plurality of memory devices, a power consumption profile table including a plurality of power information respectively indicating expected power consumptions of the plurality of memory devices (by teaching that basic profile information (characteristic information) may be stored in memory systems during their manufacture, which may be formed through test operations. Since differences may occur in electrical characteristics when the plurality of memory devices are manufactured, the profile data storage may adjust the basic profile data in response to a power compensation signal P_COM to generate the profile data storage (PF_DATA) (i.e., expected power consumptions of each of the plurality of memory devices) according to electrical characteristics (characteristic information) of each memory device [0064-0066] [0072] [0077-0082] [Figs. 7-8]) determine an operation order of the plurality of memory devices according to the plurality of commands based on the power consumption profile table (by disclosing that the operation order of the commands for each of the memory devices MD1-MDk may get rearranged based on a modified power consumption information (MDF_IF) by the command manager (55) of the flash interface layer (250) of the controller (1200) based on the power consumption amount of each of the memory devices in the storage device [0056] [0068]. The modified power consumption information (MDP_IF) is based on profile data (53) (power consumption profile table) (PF_DATA) [0067] relating the power consumption of each command for each of the memory devices [0064-0065] [Fig. 6] [0077-0078]) wherein the storage controller is further configured to: determine the operation order of the plurality of memory devices based on the power consumption profile table; and perform the one or more commands of the plurality of the commands based on the determined order (by teaching that the power manager may adjust a power consumption of each of the memory devices in real time according to the power information P_IF, the power consumption profile data PF_Data, and the adjusted power information MDF_IF, so that a power limit may not be exceeded [0064-0067]. When the calculations indicate that a peak power level limit is going to be exceeded, one of the commands to one of the memory devices is delayed so that its peak power period occurs at a later time and the limit is not exceeded, otherwise, the command may be issued and performed [0068-0070] [0085-0094]).
Cho does not explicitly disclose, but Lee teaches wherein the controller is configured to determine a marginal power of the storage device, wherein the marginal power of the storage device is determined based on a current power consumption of each of the plurality of memory devices and a power budget of the storage device; such that determining the operation order is based on the marginal power and the power consumption profile table (by teaching to derive the total power consumption amount by summing up power consumption amounts generated from non-volatile memory devices (S901), and then determine a remaining value (marginal power) by subtracting the total power consumption amount from a maximum power budget (S902), and then to schedule either a read, program, or erase command depending on whether the peak power value of those commands is less than the power consumption remaining value (S903, S910, S911). Where the peak power value of those commands is stored in a table (power consumption profile table) (714) [Fig. 11] [Fig. 9] [0128-0146] [0181-0208]. Some commands are given priority over others, such as program commands over erase commands, or read commands over all other commands [0177-0178] [0182-0188]) check whether the current power consumption of each of the plurality of memory devices exceeds the power budget of the storage device, perform one or more commands of the plurality of commands based on the determined operation order based on the current power consumption of each of the plurality of memory devices not exceeding the power budget of the storage device, and update the current power consumption of each of the plurality of memory devices (by teaching determining whether the power consumption value summed from all of the memory devices exceeds the power budget of the storage device, and if not, performing a command that fits within the power consumption remaining value. This method may be performed over and over (updating the current power consumption value). The value is current because it is used to control the power consumption instantaneously, and is derived from signals and measurements taken as the operations are performed [0063] [0163-0168] [0182-0193] [Fig. 11]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a live and updated reading of a total power consumption amount and a remaining power budget taking into account peak power consumption of those commands in order from highest power consumption command to lowest power consumption, as well as the priority order of those commands as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Cho in view of Lee does not explicitly disclose, but Li teaches, monitor changes in external factors of each of the plurality of memory devices (by teaching that the system may measure the MTJ process variation as well as the temperature from the MRAM bit cell PVMC [0074]. The power management circuit is configured to store the ambient temperature measurement in the power management circuit, and then dynamically adjust the supply voltage based on the ambient temperature, which is used to determine different temperature coefficients [0096-0097] [0074]. These measured factors would have an effect on power consumption of the memory cells as they are used to adjust voltage, which changes the power consumption of the memory cells [0007]) wherein each characteristic information of the plurality of the characteristic information includes a respective corner value of each of the plurality of memory devices; wherein each respective corner value is determined according to operation speed characteristics of transistors of a memory cell inside the corresponding memory device, wherein the characteristic information of each of the plurality of memory devices is respectively stored in the corresponding memory device of the plurality of memory devices (by teaching that an MRAM memory array (404) includes a plurality of memory cells. The memory cells experience process variations during manufacturing. The process variations change the switching speed of the access transistor (104) in the MRAM bit cell (102) [0007]. As a result a number of MTJ circuits (438) and MTJ devices (442) are provided for an MRAM array that can measure the process variation of the MRAM IC (409), as they have the same or similar process variations to the access transistor (414) and MTJ device (412) of the MRAM bit cells (406) [0011] [0056-0058]. The measured process variation (corner value) may be stored in the storage space (448) of the power management circuit (434) [0060] [0074]. This enables the power management circuit to adapt the voltage of the MRAM IC (409) to adjust the power consumption and reduce errors [0038] [0047] [0052] [0060] [0074] [0088]. The process variation inherently cause differences in power consumption as discussed [0007] [0040] [0043]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory devices which each have their power consumption measured for each of a plurality of different memory operations as taught by Cho to each be the MRAM ICs with the MRAM arrays that control voltages using MTJ circuits and devices and that store the process variations of the MRAM access transistors in the power management circuit of the corresponding MRAM IC as taught by Li, where the process variations would necessarily influence the power consumption of the MRAM array as taught by Li and therefore the measured power consumption for each of the memory devices for each of the memory operations as taught by Cho, and to further monitor the ambient temperature of the MRAM array memory devices, so that that the control voltages can be adjusted to account for the ambient temperature as taught by Li.
One of ordinary skill in the art would have been motivated to make this modification because Heidecker teaches that MRAM is very attractive for its unlimited endurance, unlimited retention, radiation hardness, and low standby power as compared to NAND flash as taught by Heidecker in [Heidecker, pg. 22, ¶1-2] [Heidecker, Table 5.0-1. NVM Comparison]. Furthermore, adjusting the control voltages to account for ambient temperature and process variations can ensure that data can be reliably read and written without bit errors and without damaging the access transistors as taught by Li in [0007-0009].
Cho in view of Lee in further view of Li as motivated by Heidecker does not explicitly disclose, but Zhu teaches correct each of the plurality of power information in the power consumption profile table based on the monitored changes in the external factors (by teaching that individual power consumption values maintained in a look up table for a plurality of different memory operations for a plurality of different memory devices may be adjusted based on environmental conditions, such as temperature [0047-0049] [0051]. The individual power consumption values are used to determine whether or not executing a command would cause the memory device to exceed a power budget [0049-0050]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power consumption profile data storing the expected power consumptions of the different operations on the different memory devices as taught by Cho to include being adjusted based on environmental conditions such as temperature to as taught by Zhu in [0051].
One of ordinary skill in the art would have been motivated to make this modification because it would cause the power consumption values to more accurately reflect the actual power consumption under different conditions as taught by Zhu in [0051].
Cho in view of Lee in further view of Li as motivated by Heidecker in further view of Zhu does not explicitly disclose, but Guo teaches that the changes in external factors of each of the plurality of memory devices may be monitored with a predetermined period (by teaching that obtaining a temperature of a non-volatile memory device may incur latency, and accordingly, a memory device may include a thermal sensor to detect a temperature of the non-volatile memory device and store the sampled temperature of the non-volatile memory device at regular intervals. In this way, when the temperature is needed/requested, it may be immediately available without resampling the temperature [0063]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the measurement and use of measured temperatures of the memory devices as taught by Cho in view of Lee in further view of Li as motivated by Heidecker in further view of Zhu to include the sample and hold technique at regular intervals with the temperature measurement scheme as taught by Guo.
One of ordinary skill in the art would have been motivated to make this modification because when the temperature is needed it may be provided without the latency of sampling it again as taught by Guo in [0063] [Abstract].
Regarding claim 5:
The storage device of claim 1 is made obvious by Cho in view of Lee in further view of Li as motivated by Heidecker in further view of Zhu in further view of Guo (Cho-Lee-Li-Heidecker-Zhu-Guo).
Cho does not explicitly disclose, but Zhu teaches, wherein: the storage controller is further configured to correct the plurality of power information based on changes in external factors that affect the power consumptions of the plurality of memory devices (by teaching to correct individual power consumption values based on environmental conditions, such as temperature, to more accurately reflect the actual power consumption values [0051]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power consumption values determine for each command and for each memory device as taught by Cho with the temperature correction as taught by Zhu.
One of ordinary skill in the art would have been motivated to make this modification because it would more accurately reflect the actual power consumption as taught by Zhu in [0051].
Regarding claim 8:
The storage device of claim 1 is made obvious by Cho-Lee-Li-Heidecker-Zhu-Guo.
Cho further discloses a first power information of a first memory device among the plurality of memory devices based on the power consumption profile table (by teaching that the power consumption stored in the power profile data storage (53) is for each type of command as it is performed on each of the memory devices. Accordingly, each memory device may have a different power consumption for the same command type [0064-0068]).
Cho does not explicitly disclose, but Lee teaches wherein: the storage controller is further configured to determine that the power information of a first memory device among the plurality of memory devices is less than the marginal power based on the marginal power and the power consumption profile table, and determine the operation order of the plurality of memory devices so that the first memory operates firstly among the plurality of memory devices (by teaching to derive the total power consumption amount by summing up power consumption amounts generated from non-volatile memory devices (S901), and then determine a remaining value (marginal power) by subtracting the total power consumption amount from a maximum power budget (S902), and then to schedule either a read, program, or erase command depending on whether the peak power value of those commands (corresponding to which memory device they would operate on as taught by Cho) is less than the power consumption remaining value (S903, S910, S911). Where the peak power value of those commands is stored in a table (power consumption profile table). (714) [Fig. 11] [Fig. 9]. If the power consumption is less, then the command is scheduled to be released next (so that the operation of the first memory device among the plurality of memory devices is performed first before the other queued commands) [0128-0146] [0181-0208]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a remaining power budget as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Regarding claim 9:
The storage device of claim 1 is made obvious by Cho-Lee-Li-Heidecker-Zhu-Guo.
Cho further discloses to delay a peak power period if it is going to exceed the power limit [0067-0070]).
Cho does not explicitly disclose, but Lee teaches, wherein: the storage controller is further configured to: compare the plurality of power information with the marginal power of the storage device based on the power consumption profile table; determine that each of the plurality of memory devices are expected to consume more power than the marginal power; and wait until the marginal power exceeds at least one of the plurality of power information (by teaching that if each of the commands cannot be executed without exceeding the power consumption remaining value, the process will loop back to the beginning (wait), determine the power consumption and remaining power consumption value again, and then again determine if any of the commands can be executed without exceeded the power consumption remaining value before looping back to the beginning if none of the commands can be executed without exceeding the power consumption remaining value (wait until the marginal power exceeds at least one of the plurality of power information) [0179] [Fig. 11] [0128-0146] [0181-0208]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a remaining power budget as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Regarding claim 10:
The storage device of claim 1 is made obvious by Cho-Lee-Li-Heidecker-Zhu-Guo.
Cho does not explicitly disclose, but Lee teaches, wherein: the storage controller is further configured to: compare the plurality of power with the marginal power of the storage device based on the power consumption profile table; determine that a first plurality of memory devices among the plurality of memory devices are consuming less power that the marginal power; and determine an operation order of the first plurality of memory devices with an order of a largest power information to a smallest power information (by teaching that the commands are released for execution in an order based upon power consumption, where the commands are tested in order of a highest peak power consumption to a lowest peak power consumption [Fig. 11] [0182], as the process continues, commands will continue to be released until the power budget would be [0128-0146] [0181-0208]. Multiple commands may be performed in parallel [0056] [0154]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a remaining power budget in order from highest power consumption to lowest power consumption as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Regarding claim 14:
The operation method of claim 11 is made obvious by Cho-Lee-Li-Heidecker-Zhu-Guo.
Cho further discloses, wherein the plurality of commands includes a first plurality of commands and a second plurality of commands (by teaching that the controller may receive a plurality of read and write commands, including read (first plurality of commands) and write (second plurality of commands) commands [0065-0069])
Cho does not explicitly disclose, but Lee teaches, wherein the determining of the priority comprises determining that a first priority of the first plurality of commands with higher than a second priority of the second plurality of commands (by teaching that the read commands are tested for whether or not they fit within a power consumption remaining value first and therefore released for execution first before a program/write command [Fig. 11], as the read commands are given higher priority [0182-0195]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a remaining power budget in order of priority from highest power consumption to lowest power consumption as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Regarding claim 15:
The operation method of claim 14 is made obvious by Cho-Lee-Li-Heidecker-Zhu-Guo.
Cho-Lee-Li-Heidecker further make obvious wherein the determining the operation order comprises: obtaining, from the power consumption profile table, a power information of each of a first plurality of memory devices among the plurality of memory devices, wherein the first plurality of memory devices are configured to perform operations according to the first plurality of commands, and comparing the marginal power and the power information of each of the first plurality of memory devices (through the analysis performed for claim 14 – i.e., the memory devices for which there is a queued read command).
Regarding claim 16:
The operation method of claim 15 is made obvious by Cho-Lee-Li-Heidecker-Zhu-Guo.
Cho-Lee-Li-Heidecker further make obvious, further comprising: determining that a first power information of a first memory device among the first plurality of memory devices is less than the marginal power, and determining the operation order of the plurality of commands so that an operation for a command corresponding to the first memory device among the first plurality of commands is performed first (through the analysis performed for claim 15).
Regarding claim 17:
The operation method of claim 15 is made obvious by Cho-Lee-Li-Heidecker-Zhu-Guo.
Cho-Lee-Li-Heidecker further make obvious, further comprising: determining that there is no power information less than the marginal power among the each power information of the first plurality of memory devices, and determining that the operation order of the plurality of commands is to wait until the marginal power exceeds at least one power information of each of the first plurality of memory devices (through the analysis performed for claim 15).
Regarding claim 18:
The operation method of claim 15 is made obvious by Cho-Lee-Li-Heidecker-Zhu-Guo.
Cho-Lee-Li-Heidecker further make obvious, further comprising: determining that there is no power information less than the marginal power among the each power information of the first plurality of memory devices, obtaining from the power consumption profile table, a power information of a second plurality of memory devices that operate according to the second plurality of commands, comparing the marginal power and the power information of the second plurality of memory devices, determining that a second power information of a second memory device among the second plurality of memory devices is less than the marginal power, and determining the operation order of the plurality of commands so that an operation for a command corresponding to the second memory device among the second plurality of commands is performed first (through the analysis performed for claim 15).
Regarding claim 19:
The operation method of claim 11 is made obvious by Cho-Lee-Li-Heidecker-Zhu-Guo.
Cho does not explicitly disclose, but Lee teaches further comprising: checking whether the current power consumption of each of the plurality of memory devices exceeds the power budget of the storage device, performing a command according to the plurality of commands based on the determined operation order if the current power consumption of each of the plurality of memory devices does not exceed the power budget of the storage device, and updating the current power consumption of the plurality of memory devices (by teaching determining whether the power consumption value summed from all of the memory devices exceeds the power budget of the storage device, and if not, performing a command that fits within the power consumption remaining value. This method may be performed over and over (updating the current power consumption value). The value is current because it is used to control the power consumption instantaneously, and is derived from signals and measurements taken as the operations are performed [0063] [0163-0168] [0182-0193] [Fig. 11]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a live and updated reading of a total power consumption amount and a power budget in order from highest power consumption command to lowest power consumption command as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Regarding claim 20:
Cho discloses, a storage system ((1000) [Fig. 1]) comprising: a power supply that supplies a power input from an outside device ((VCCE) [Fig. 1]), a plurality of non-volatile memory devices (1100) including (MD1-MDk) on each channel (CH1-CHi) [Fig. 2]) configured to store a plurality of data input from the outside device (the host (2000) inputs write commands to the storage device), and a storage controller configured to: create, based on respective characteristics of the plurality of non-volatile memory devices, a power consumption profile table representing expected power consumptions respectively corresponding to the plurality of non-volatile memory (by teaching the profile data storage that may stores power related data. It starts with a basic profile data on power consumption (characteristic of the non-volatile memory devices) and then outputs adjusted power information MDP_IF which is corrected based on a power compensation signal P_COM, which is output as profile data PF_DATA to the power manager (i.e., create a power consumption profile table representing expected power consumptions of the plurality of non-volatile memory devices) [0064-0068]), determine an operation order of the plurality of non-volatile memory devices (by teaching that the command manager may receive the commands and change an execution order according to the adjusted power information MDP_IF [0068]) based on a current power consumption of each of the plurality of non-volatile memory devices (by teaching that the power monitor component may monitor the power supplied to the storage device (1100) and measure the total amount of current flowing on the power supply line (TCR) which the external voltage are applied to and may measure the total amount of current applied to each of the memory devices during an actual operation of the storage device in real-time [0063]) perform one or more commands of the plurality of commands according to the determined operation order based on the current power consumption of each of the plurality of non-volatile memory devices (when the calculations indicate that a peak power level limit is going to be exceeded, one of the commands to one of the memory devices is delayed so that its peak power period occurs at a later time and the limit is not exceeded, otherwise, the command may be issued and performed [0068-0070] [0085-0094]
Cho does not explicitly disclose, but Lee teaches to determine an operation order of the plurality of non-volatile memory devices based on comparison results of a power budget and a current power consumption of each of the plurality of non-volatile memory devices, in response to receiving a plurality of commands from the outside device instructing to store the plurality of data, to perform one or more commands of the plurality of commands according to the determined operation order based on the current power consumption of each of the plurality of non-volatile memory devices not exceeding the power budget, and update the current power consumption of each of the plurality of memory devices (by teaching to determine a remaining value by subtracting the total power consumption amount from a maximum power budget (S902), and then to schedule either a read, program (a plurality of commands from the outside device instructing to save the plurality of data), or erase command depending on whether the peak power value of those commands is less than the power consumption remaining value (S903, S910, S911) (comparison of the power budget and current power consumption). Where the peak power value of those commands is stored in a table (power consumption profile table) (714) [Fig. 11] [Fig. 9] [0128-0146] [0181-0208]. This method may be performed over and over (updating the current power consumption value) [Fig. 11]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on peak power information and a remaining power budget after determining the amount of power consumed by the memory devices compared to a power budget as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Cho in view of Lee do not explicitly disclose, but Li teaches, monitor changes in external factors of each of the plurality of non-volatile memory devices (by teaching that the system may measure the MTJ process variation as well as the temperature from the MRAM bit cell PVMC [0074]. The power management circuit is configured to store the ambient temperature measurement in the power management circuit, and then dynamically adjust the supply voltage based on the ambient temperature, which is used to determine different temperature coefficients [0096-0097] [0074]. These measured factors would have an effect on power consumption of the memory cells as they are used to adjust voltage, which changes the power consumption of the memory cells [0007]) wherein each of the respective characteristics of the plurality of non-volatile memory devices includes a respective corner value of a corresponding of the plurality of non-volatile memory devices, wherein the respective corner value is determined according to operation speed characteristics of transistors of a memory cell inside a corresponding non-volatile memory device, wherein each of the respective characteristics of the plurality of non-volatile memory devices is stored in the corresponding non-volatile memory device of the plurality of non-volatile memory devices (by teaching that an MRAM memory array (404) includes a plurality of memory cells. The memory cells experience process variations during manufacturing. The process variations change the switching speed of the access transistor (104) in the MRAM bit cell (102) [0007]. As a result a number of MTJ circuits (438) and MTJ devices (442) are provided for an MRAM array that can measure the process variation of the MRAM IC (409), as they have the same or similar process variations to the access transistor (414) and MTJ device (412) of the MRAM bit cells (406) [0011] [0056-0058]. The measured process variation (corner value) may be stored in the storage space (448) of the power management circuit (434) [0060] [0074]. This enables the power management circuit to adapt the voltage of the MRAM IC (409) to adjust the power consumption and reduce errors [0038] [0047] [0052] [0060] [0074] [0088]. The process variation inherently cause differences in power consumption as discussed [0007] [0040] [0043]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory devices which each have their power consumption measured for each of a plurality of different memory operations as taught by Cho to each be the MRAM ICs with the MRAM arrays that control voltages using MTJ circuits and devices and that store the process variations of the MRAM access transistors in the power management circuit of the corresponding MRAM IC as taught by Li, where the process variations would necessarily influence the power consumption of the MRAM array as taught by Li and therefore the measured power consumption for each of the memory devices for each of the memory operations as taught by Cho, and to further monitor the ambient temperature of the MRAM array memory devices, so that that the control voltages can be adjusted to account for the ambient temperature as taught by Li.
One of ordinary skill in the art would have been motivated to make this modification because Heidecker teaches that MRAM is very attractive for its unlimited endurance, unlimited retention, radiation hardness, and low standby power as compared to NAND flash as taught by Heidecker in [Heidecker, pg. 22, ¶1-2] [Heidecker, Table 5.0-1. NVM Comparison]. Furthermore, adjusting the control voltages to account for ambient temperature and process variations can ensure that data can be reliably read and written without bit errors and without damaging the access transistors as taught by Li in [0007-0009].
Cho in view of Lee in further view of Li as motivated by Heidecker does not explicitly disclose, but Zhu teaches correct the expected power consumptions in the power consumption profile table based on the monitored changes in the external factors (by teaching that individual power consumption values maintained in a look up table for a plurality of different memory operations for a plurality of different memory devices may be adjusted based on environmental conditions, such as temperature [0047-0049] [0051]. The individual power consumption values are used to determine whether or not executing a command would cause the memory device to exceed a power budget [0049-0050]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power consumption profile data storing the expected power consumptions of the different operations on the different memory devices as taught by Cho to include being adjusted based on environmental conditions such as temperature to as taught by Zhu in [0051].
One of ordinary skill in the art would have been motivated to make this modification because it would cause the power consumption values to more accurately reflect the actual power consumption under different conditions as taught by Zhu in [0051].
Cho in view of Lee in further view of Li as motivated by Heidecker in further view of Zhu does not explicitly disclose, but Guo teaches that the changes in external factors of each of the plurality of memory devices may be monitored with a predetermined period (by teaching that obtaining a temperature of a non-volatile memory device may incur latency, and accordingly, a memory device may include a thermal sensor to detect a temperature of the non-volatile memory device and store the sampled temperature of the non-volatile memory device at regular intervals. In this way, when the temperature is needed/requested, it may be immediately available without resampling the temperature [0063]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the measurement and use of measured temperatures of the memory devices as taught by Cho in view of Lee in further view of Li as motivated by Heidecker in further view of Zhu to include the sample and hold technique at regular intervals with the temperature measurement scheme as taught by Guo.
One of ordinary skill in the art would have been motivated to make this modification because when the temperature is needed it may be provided without the latency of sampling it again as taught by Guo in [0063] [Abstract].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cho-Lee-Li-Heidecker-Zhu-Guo in further view of US Patent Application Publication No. US 2023/0019224 A1 (Palmer).
Regarding claim 6:
The storage device of claim 5 is made obvious by Cho-Lee-Li-Heidecker-Zhu-Guo.
Cho does not explicitly disclose, but Zhu teaches, wherein: the external factors include a surrounding temperature of each of the plurality of memory devices (through the analysis performed for claim 5).
Cho in view of Zhu does not explicitly disclose, but Palmer teaches and an access frequency to each of the plurality of memory devices of the storage controller (by teaching that trim settings can affect power consumption, and include a clock setting (access frequency to each of the plurality of memory devices of the storage controller). Trim settings may be stored for each power identifier, and include settings such as clock rates, capacitor charge rates, etc. [0033]. The trim settings may be used to control a command to operate at a variety of power levels, with different latencies [0033-0041]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power profile information as taught by Cho to additionally include multiple power profiles for each of a plurality of power levels including a plurality of trim settings for each power level, including clock rates and capacitor charge rates as taught by Palmer.
One of ordinary skill in the art would have been motivated to make this modification because it allows operations that could not previously have been operated concurrently within a power budget to operate concurrently, which results in increased performance as taught by Palmer in [0041].
Response to Arguments/Amendments
In response to the amendments to the claims, the previous objections to the claims are withdrawn. However, a new warning has been added to the claim objection section regarding substantially duplicate claim pairs 1 and 5 and 11 and 19.
In response to the amendments to the claims, a new 35 USC §112(d) rejection has been made to claim 19 as seen in the corresponding rejection section above.
In response to the amendments to the claims, the previous 35 USC §112(a) rejection has been withdrawn.
In response to the amendments to the claims, a new 35 USC §112(b) rejection has been made to claim 6 as seen in the corresponding rejection section above.
In response to the amendments to the claims, the 35 USC §103 rejection has been updated to claims 1, 5-6, 8-11 and 14-20 to reflect the newly amended subject matter. Applicant’s arguments have been fully considered, but are not persuasive. Applicant argues, without more, that the combination of references fails to disclose the combination of limitations as amended. The Examiner respectfully disagrees as the references make obvious the newly amended limitations as seen in the corresponding rejection section above. Accordingly, the claims are not indicated as allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. US 2019/0138233 A1 (Mun) teaches a peak information memory (222) that is used to determine an operation order of a set of commands on a set of memory devices [see Fig. 9C] to stay within a power budget. It may choose to delay commands that do not fit within the power budget [Fig. 13] [0031].
US Patent Application Publication No. US 2020/0209944 A1 (Palmer_2) teaches that the memory controller can monitor and sum instantaneous power usage and compare it to a threshold [0076]. If there is spare capacity available, additional operations may be queued [0077] [see Fig. 9].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CURTIS JAMES KORTMAN/ Primary Examiner, Art Unit 2139
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