DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06 March 2026 and 08 April 2026 has been entered.
Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. §112(f) in this application.
Claim Objections
Claims 1, 5-6, 8-11 and 13-20 are objected to because of the following informalities:
Claim 1 recites, “wherein each of the plurality of the characteristic information includes a respective corner value of each of the plurality of memory devices”, which as best understood by the Examiner in light of the specification should be amended to recite, “wherein each characteristic information of the plurality of the characteristic information includes a respective corner value of a corresponding memory device of the plurality of memory devices”, because it is understood from the specification that each corner value of the plurality of corner values corresponds to one of the plurality of memory device (the one it is stored on) (see [0059]).
Claim 1 recites, “wherein the respective corner value is determined according to operation speed characteristics of transistors of a memory cell inside a corresponding memory device” which as best understood by the Examiner in light of the specification should be amended to recite, “wherein each respective corner value is determined according to operation speed characteristics of transistors of a memory cell inside [[a]]the corresponding memory device” because it is understood from the specification that each corner value of the plurality of corner values corresponds to one of the plurality of memory device (the one it is stored on) (see [0059]).
Claim 8 recites, “the first memory operates firstly”, which as best understood by the Examiner in light of the specification should be amended to recite, “the first memory device operates firstly”.
Claim 11 recites, “wherein each of the plurality of characteristic information includes a respective corner value of each of the plurality of memory devices, wherein the respective corner value is determined according to operation speed characteristics of transistors of a memory cell inside a corresponding memory device” which as best understood by the Examiner in light of the specification should be amended to recite, “wherein each characteristic information of the plurality of characteristic information includes a respective corner value of a corresponding memory device of the plurality of memory devices, wherein the each respective corner value is determined according to operation speed characteristics of transistors of a memory cell inside [[a]]the corresponding memory device” for reasons similar to claim 1.
Claim 14 recites, “a first priority of the first plurality of commands with higher than a second priority of the second plurality of commands” which as best understood by the Examiner in light of the specification should be amended to recite, “a first priority of the first plurality of commands [[with]]is higher than a second priority of the second plurality of commands”.
Claim 17 recites, “the marginal power exceeds at least one power information of plurality of power information corresponding to first plurality of memory devices”.
Claim 20 recites, “create, based on characteristics of the plurality of non-volatile memory devices”, which as best understood by the Examiner in light of the specification should be amended to recite, “create, based on respective characteristics of the plurality of non-volatile memory devices”.
Claim 20 recites, “wherein each of the characteristics includes a respective corner value of each of the plurality of non-volatile memory devices, wherein the respective corner value is determined according to operation speed characteristics of transistors of a memory cell inside a corresponding non-volatile memory device” which as best understood by the Examiner in light of the specification should be amended to recite, “wherein each of the characteristics of the respective characteristics of the plurality of non-volatile memory devices includes a respective corner value of a corresponding non-volatile memory device of the plurality of non-volatile memory devices, wherein each respective corner value is determined according to operation speed characteristics of transistors of a memory cell inside [[a]]the corresponding non-volatile memory device”.
Claim 20 recites, “wherein each of the characteristics is stored in the corresponding non-volatile memory device of the plurality of non-volatile memory devices”, which as best understood by the Examiner in light of the specification should be amended to recite, “wherein each of the characteristics of the respective characteristics of the plurality of non-volatile memory devices is stored in the corresponding non-volatile memory device of the plurality of non-volatile memory devices”.
Claim 20 recites, “based on comparison results of the power input and a current power consumption of each of the plurality of non-volatile memory devices”, which as best understood by the Examiner in light of the specification should be amended to recite, “based on comparison results of the power budget and a current power consumption of each of the plurality of non-volatile memory devices” as consistent with the specification in [0036] [0079].
Claims 5-6, 8-10, and 13-19 are objected to for failing to correct the deficiencies of a base claim from which they depend.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 13 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 13:
Claim 13 recites, “wherein each of the plurality of characteristic information includes a static value and a dynamic value, wherein the static value comprises the respective corner value, wherein creating the power consumption profile table comprises: monitoring changes in external factors of each of the plurality of memory devices with a predetermined period, and calculating the dynamic value of each of the plurality of characteristic information according to a predetermined calculation method based on the respective changes in the external factors of each of the plurality of memory devices, and correcting each of the plurality of power information based on the corresponding dynamic value.”
The specification does not support this requirement. Illustratively, the specification does not recite “static” or “dynamic” anywhere, and the Applicant does not provide a citation to written description support for the amendments. Furthermore, the specification does not ever disclose a requirement that a characteristic information include a static value and a dynamic value. Moreover, the specification does not disclose calculating a dynamic value characteristic information based on a monitored external factor and a predetermined calculation. Instead, the specification discloses correcting the power information of the power consumption profile table based on monitored external factors, such as temperature [0072-0073]. Accordingly, the limitation is regarded as new matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-11 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2020/0104062 A1 (Cho) in view of US Patent Application Publication No. US 2019/0212932 A1 (Lee) in further view of US Patent Application Publication No. US 2019/0051341 A1 (Li) as motivated by the paper by Jason Heidecker of JPL of NASA titled, “MRAM Technology Status” as published on 2 January 2013 (Heidecker).
Regarding claim 1 and analogous claims 11:
Cho discloses, a storage device (1000) comprising: a plurality of memory devices (see (1100) in [Fig. 2] with a plurality of memory devices (MD1-MDk) on each channel (CH1-CHi) [Fig. 2]), and a storage controller (1200) configured to receive, from an external host device (2000), a plurality of commands that operate the plurality of memory devices ([Fig. 9] shows the commands received from the CPU (200) of the host device (2000) [0086]. The power is supplied to the storage device (1000) from VCCE [Fig. 1] generate, based on a plurality of characteristic information respectively corresponding to the plurality of memory devices, a power consumption profile table including a plurality of power information respectively indicating expected power consumptions of the plurality of memory devices (by teaching that basic profile information (characteristic information) may be stored in memory systems during their manufacture, which may be formed through test operations. Since differences may occur in electrical characteristics when the plurality of memory devices are manufactured, the profile data storage may adjust the basic profile data in response to a power compensation signal P_COM to generate the profile data storage (PF_DATA) (i.e., expected power consumptions of each of the plurality of memory devices) according to electrical characteristics (characteristic information) of each memory device [0064-0066] [0072] [0077-0082] [Figs. 7-8]) determine an operation order of the plurality of memory devices according to the plurality of commands based on the power consumption profile table (by disclosing that the operation order of the commands for each of the memory devices MD1-MDk may get rearranged based on a modified power consumption information (MDF_IF) by the command manager (55) of the flash interface layer (250) of the controller (1200) based on the power consumption amount of each of the memory devices in the storage device [0056] [0068]. The modified power consumption information (MDP_IF) is based on profile data (53) (power consumption profile table) (PF_DATA) [0067] relating the power consumption of each command for each of the memory devices [0064-0065] [Fig. 6] [0077-0078]) wherein the storage controller is further configured to: determine the operation order of the plurality of memory devices based on the power consumption profile table; and perform the one or more commands of the plurality of the commands based on the determined order (by teaching that the power manager may adjust a power consumption of each of the memory devices in real time according to the power information P_IF, the power consumption profile data PF_Data, and the adjusted power information MDF_IF, so that a power limit may not be exceeded [0064-0067]. When the calculations indicate that a peak power level limit is going to be exceeded, one of the commands to one of the memory devices is delayed so that its peak power period occurs at a later time and the limit is not exceeded, otherwise, the command may be issued and performed [0068-0070] [0085-0094]).
Cho does not explicitly disclose, but Lee teaches wherein the controller is configured to determine a marginal power of the storage device, wherein the marginal power of the storage device is determined based on a current power consumption of each of the plurality of memory devices and a power budget of the storage device; such that determining the operation order is based on the marginal power and the power consumption profile table (by teaching to derive the total power consumption amount by summing up power consumption amounts generated from non-volatile memory devices (S901), and then determine a remaining value (marginal power) by subtracting the total power consumption amount from a maximum power budget (S902), and then to schedule either a read, program, or erase command depending on whether the peak power value of those commands is less than the power consumption remaining value (S903, S910, S911). Where the peak power value of those commands is stored in a table (power consumption profile table) (714) [Fig. 11] [Fig. 9] [0128-0146] [0181-0208]. Some commands are given priority over others, such as program commands over erase commands, or read commands over all other commands [0177-0178] [0182-0188]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a remaining power budget and a peak power consumption of those commands stored in a power consumption table, as well as the priority of those commands as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget, remaining power, and priority of the commands increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Cho in view of Lee do not explicitly disclose, but Li teaches, wherein each of the plurality of the characteristic information includes a respective corner value of each of the plurality of memory devices; wherein the respective corner value is determined according to operation speed characteristics of transistors of a memory cell inside the corresponding memory device, wherein the characteristic information of each of the plurality of memory devices is respectively stored in the corresponding memory device of the plurality of memory devices (by teaching that an MRAM memory array (404) includes a plurality of memory cells. The memory cells experience process variations during manufacturing. The process variations change the switching speed of the access transistor (104) in the MRAM bit cell (102) [0007]. As a result a number of MTJ circuits (438) and MTJ devices (442) are provided for an MRAM array that can measure the process variation of the MRAM IC (409), as they have the same or similar process variations to the access transistor (414) and MTJ device (412) of the MRAM bit cells (406) [0011] [0056-0058]. The measured process variation (corner value) may be stored in the storage space (448) of the power management circuit (434) [0060] [0074]. This enables the power management circuit to adapt the voltage of the MRAM IC (409) to adjust the power consumption and reduce errors [0038] [0047] [0052] [0060] [0074] [0088]. The process variation inherently cause differences in power consumption as discussed [0007] [0040] [0043]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory devices which each have their power consumption measured for each of a plurality of different memory operations as taught by Cho to each be the MRAM ICs with the MRAM arrays that control voltages using MTJ circuits and devices and that store the process variations of the MRAM access transistors in the power management circuit of the corresponding MRAM IC as taught by Li, where the process variations would necessarily influence the power consumption of the MRAM array as taught by Li and therefore the measured power consumption for each of the memory devices for each of the memory operations as taught by Cho.
One of ordinary skill in the art would have been motivated to make this modification because the paper by Jason Jeidecker et. al., from the JPL at NASA titled “MRAM Technology Status” (Jeidecker) teaches that MRAM is very attractive for its unlimited endurance, unlimited retention, radiation hardness, and low standby power as compared to NAND flash as taught by Jeidecker in [pg. 22, ¶1-2] [Table 5.0-1. NVM Comparison].
Regarding claim 8:
The storage device of claim 1 is made obvious by Cho in view of Lee in further view of Li in further view of Heidecker (Cho-Lee-Li-Heidecker).
Cho further discloses a first power information of a first memory device among the plurality of memory devices based on the power consumption profile table (by teaching that the power consumption stored in the power profile data storage (53) is for each type of command as it is performed on each of the memory devices. Accordingly, each memory device may have a different power consumption for the same command type [0064-0068]).
Cho does not explicitly disclose, but Lee teaches wherein: the storage controller is further configured to determine that the power information of a first memory device among the plurality of memory devices is less than the marginal power based on the marginal power and the power consumption profile table, and determine the operation order of the plurality of memory devices so that the first memory operates firstly among the plurality of memory devices (by teaching to derive the total power consumption amount by summing up power consumption amounts generated from non-volatile memory devices (S901), and then determine a remaining value (marginal power) by subtracting the total power consumption amount from a maximum power budget (S902), and then to schedule either a read, program, or erase command depending on whether the peak power value of those commands (corresponding to which memory device they would operate on as taught by Cho) is less than the power consumption remaining value (S903, S910, S911). Where the peak power value of those commands is stored in a table (power consumption profile table). (714) [Fig. 11] [Fig. 9]. If the power consumption is less, then the command is scheduled to be released next (so that the operation of the first memory device among the plurality of memory devices is performed first before the other queued commands) [0128-0146] [0181-0208]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a remaining power budget as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Regarding claim 9:
The storage device of claim 1 is made obvious by Cho-Lee-Li-Heidecker.
Cho further discloses to delay a peak power period if it is going to exceed the power limit [0067-0070]).
Cho does not explicitly disclose, but Lee teaches, wherein: the storage controller is further configured to: compare the plurality of power information with the marginal power of the storage device based on the power consumption profile table; determine that each of the plurality of memory devices are expected to consume more power than the marginal power; and wait until the marginal power exceeds at least one of the plurality of power information (by teaching that if each of the commands cannot be executed without exceeding the power consumption remaining value, the process will loop back to the beginning (wait), determine the power consumption and remaining power consumption value again, and then again determine if any of the commands can be executed without exceeded the power consumption remaining value before looping back to the beginning if none of the commands can be executed without exceeding the power consumption remaining value (wait until the marginal power exceeds at least one of the plurality of power information) [0179] [Fig. 11] [0128-0146] [0181-0208]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a remaining power budget as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Regarding claim 10:
The storage device of claim 1 is made obvious by Cho-Lee-Li-Heidecker.
Cho does not explicitly disclose, but Lee teaches, wherein: the storage controller is further configured to: compare the plurality of power with the marginal power of the storage device based on the power consumption profile table; determine that a first plurality of memory devices among the plurality of memory devices are consuming less power that the marginal power; and determine an operation order of the first plurality of memory devices with an order of a largest power information to a smallest power information (by teaching that the commands are released for execution in an order based upon power consumption, where the commands are tested in order of a highest peak power consumption to a lowest peak power consumption [Fig. 11] [0182], as the process continues, commands will continue to be released until the power budget would be [0128-0146] [0181-0208]. Multiple commands may be performed in parallel [0056] [0154]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a remaining power budget in order from highest power consumption to lowest power consumption as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Regarding claim 13:
The operation method of claim 11 is made obvious by Cho-Lee-Li-Heidecker.
Cho does not explicitly disclose, but Li teaches wherein each of the plurality of characteristic information includes a static value and a dynamic value, wherein the static value comprises the respective corner value, wherein creating the power consumption profile table comprises: monitoring changes in external factors of each of the plurality of memory devices with a predetermined period, and calculating the dynamic value of each of the plurality of characteristic information according to a predetermined calculation method based on the respective changes in the external factors of each of the plurality of memory devices, and correcting each of the plurality of power information based on the corresponding dynamic value (by teaching that the system may measure the MTJ process variation (static value) as well as the temperature from the MRAM bit cell PVMC [0074]. The power management circuit is configured to store the ambient temperature measurement in the power management circuit, and then dynamically adjust the supply voltage based on the ambient temperature, which is used to determine different temperature coefficients [0096-0097] (i.e., calculating the dynamic value of each of the plurality of characteristic information according to a predetermined calculation method based on the respective changes in the external factors of each of the plurality of memory devices) [0074]. These measured factors would have an affect on power consumption of the memory cells as they are used to adjust voltage, which changes the power consumption of the memory cells [0007]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory devices which each have their power consumption measured for each of a plurality of different memory operations as taught by Cho to each be the MRAM ICs with the MRAM arrays that control voltages using MTJ circuits and devices and that store the process variations of the MRAM access transistors and the ambient temperatures in the power management circuit of the corresponding MRAM IC as taught by Li, where the process variations and ambient temperatures are used to influence the selected voltages and would therefore necessarily influence the power consumption of the MRAM array as taught by Li and therefore the measured power consumption for each of the memory devices for each of the memory operations as taught by Cho.
One of ordinary skill in the art would have been motivated to make this modification because the paper by Jason Jeidecker et. al., from the JPL at NASA titled “MRAM Technology Status” (Jeidecker) teaches that MRAM is very attractive for its unlimited endurance, unlimited retention, radiation hardness, and low standby power as compared to NAND flash as taught by Jeidecker in [pg. 22, ¶1-2] [Table 5.0-1. NVM Comparison].
Regarding claim 14:
The operation method of claim 11 is made obvious by Cho-Lee-Li-Heidecker.
Cho further discloses, wherein the plurality of commands includes a first plurality of commands and a second plurality of commands (by teaching that the controller may receive a plurality of read and write commands, including read (first plurality of commands) and write (second plurality of commands) commands [0065-0069])
Cho does not explicitly disclose, but Lee teaches, wherein the determining of the priority comprises determining that a first priority of the first plurality of commands with higher than a second priority of the second plurality of commands (by teaching that the read commands are tested for whether or not they fit within a power consumption remaining value first and therefore released for execution first before a program/write command [Fig. 11], as the read commands are given higher priority [0182-0195]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a remaining power budget in order of priority from highest power consumption to lowest power consumption as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Regarding claim 15:
The operation method of claim 14 is made obvious by Cho-Lee-Li-Heidecker.
Cho-Lee-Li-Heidecker further make obvious wherein the determining the operation order comprises: obtaining, from the power consumption profile table, a power information of each of a first plurality of memory devices among the plurality of memory devices, wherein the first plurality of memory devices are configured to perform operations according to the first plurality of commands, and comparing the marginal power and the power information of each of the first plurality of memory devices (through the analysis performed for claim 14 – i.e., the memory devices for which there is a queued read command).
Regarding claim 16:
The operation method of claim 15 is made obvious by Cho-Lee-Li-Heidecker.
Cho-Lee-Li-Heidecker further make obvious, further comprising: determining that a first power information of a first memory device among the first plurality of memory devices is less than the marginal power, and determining the operation order of the plurality of commands so that an operation for a command corresponding to the first memory device among the first plurality of commands is performed first (through the analysis performed for claim 15).
Regarding claim 17:
The operation method of claim 15 is made obvious by Cho-Lee-Li-Heidecker.
Cho-Lee-Li-Heidecker further make obvious, further comprising: determining that there is no power information less than the marginal power among the each power information of the first plurality of memory devices, and determining that the operation order of the plurality of commands is to wait until the marginal power exceeds at least one power information of each of the first plurality of memory devices (through the analysis performed for claim 15).
Regarding claim 18:
The operation method of claim 15 is made obvious by Cho-Lee-Li-Heidecker.
Cho-Lee-Li-Heidecker further make obvious, further comprising: determining that there is no power information less than the marginal power among the each power information of the first plurality of memory devices, obtaining from the power consumption profile table, a power information of a second plurality of memory devices that operate according to the second plurality of commands, comparing the marginal power and the power information of the second plurality of memory devices, determining that a second power information of a second memory device among the second plurality of memory devices is less than the marginal power, and determining the operation order of the plurality of commands so that an operation for a command corresponding to the second memory device among the second plurality of commands is performed first (through the analysis performed for claim 15).
Regarding claim 19:
The operation method of claim 11 is made obvious by Cho-Lee-Li-Heidecker.
Cho does not explicitly disclose, but Lee teaches further comprising: checking whether the current power consumption of each of the plurality of memory devices exceeds the power budget of the storage device, performing a command according to the plurality of commands based on the determined operation order if the current power consumption of each of the plurality of memory devices does not exceed the power budget of the storage device, and updating the current power consumption of the plurality of memory devices (by teaching determining whether the power consumption value summed from all of the memory devices exceeds the power budget of the storage device, and if not, performing a command that fits within the power consumption remaining value. This method may be performed over and over (updating the current power consumption value). The value is current because it is used to control the power consumption instantaneously, and is derived from signals and measurements taken as the operations are performed [0063] [0163-0168] [0182-0193] [Fig. 11]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a live and updated reading of a total power consumption amount and a power budget in order from highest power consumption command to lowest power consumption command as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Regarding claim 20:
Cho discloses, a storage system ((1000) [Fig. 1]) comprising: a power supply that supplies a power input from an outside device ((VCCE) [Fig. 1]), a plurality of non-volatile memory devices (1100) including (MD1-MDk) on each channel (CH1-CHi) [Fig. 2]) configured to store a plurality of data input from the outside device (the host (2000) inputs write commands to the storage device), and a storage controller configured to: create, based on characteristics of the plurality of non-volatile memory devices, a power consumption profile table representing expected power consumptions respectively corresponding to the plurality of non-volatile memory (by teaching the profile data storage that may stores power related data. It starts with a basic profile data on power consumption (characteristic of the non-volatile memory devices) and then outputs adjusted power information MDP_IF which is corrected based on a power compensation signal P_COM, which is output as profile data PF_DATA to the power manager (i.e., create a power consumption profile table representing expected power consumptions of the plurality of non-volatile memory devices) [0064-0068]), determine an operation order of the plurality of non-volatile memory devices (by teaching that the command manager may receive the commands and change an execution order according to the adjusted power information MDP_IF [0068]) based on results of the power input and a current power consumption of each of the plurality of non-volatile memory devices (by teaching that the power monitor component may monitor the power supplied to the storage device (1100) and measure the total amount of current flowing on the power supply line (TCR) which the external voltage are applied to and may measure the total amount of current applied to each of the memory devices during an actual operation of the storage device in real-time [0063]) perform one or more commands of the plurality of commands according to the determined operation order (when the calculations indicate that a peak power level limit is going to be exceeded, one of the commands to one of the memory devices is delayed so that its peak power period occurs at a later time and the limit is not exceeded, otherwise, the command may be issued and performed [0068-0070] [0085-0094]
Cho does not explicitly disclose, but Lee teaches to perform a comparison of the power input and a current power consumption of each of the plurality of non-volatile memory devices, in response to receiving a plurality of commands from the outside device instructing to store the plurality of data (by teaching to determine a remaining value by subtracting the total power consumption amount from a maximum power budget (S902), and then to schedule either a read, program (a plurality of commands from the outside device instructing to save the plurality of data), or erase command depending on whether the peak power value of those commands is less than the power consumption remaining value (S903, S910, S911) (comparison of the power input and current power consumption). Where the peak power value of those commands is stored in a table (power consumption profile table) (714) [Fig. 11] [Fig. 9] [0128-0146] [0181-0208]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the command scheduling as taught by Cho to include scheduling commands based on a remaining power budget as taught by Lee.
One of ordinary skill in the art would have been motivated to make this modification because determining whether a queued commands should be held longer to manage the peak power generated by the non-volatile memory devices based on the power budget and remaining power increases the reliability of the system, and degradation of performance can be minimized as taught by Lee in [0224].
Cho in view of Lee do not explicitly disclose, but Li teaches, wherein each of the characteristics includes a respective corner value of each of the plurality of non-volatile memory devices, wherein the respective corner value is determined according to operation speed characteristics of transistors of a memory cell inside a corresponding non-volatile memory device, wherein each of the characteristics is stored in the corresponding non-volatile memory device of the plurality of non-volatile memory devices (by teaching that an MRAM memory array (404) includes a plurality of memory cells. The memory cells experience process variations during manufacturing. The process variations change the switching speed of the access transistor (104) in the MRAM bit cell (102) [0007]. As a result a number of MTJ circuits (438) and MTJ devices (442) are provided for an MRAM array that can measure the process variation of the MRAM IC (409), as they have the same or similar process variations to the access transistor (414) and MTJ device (412) of the MRAM bit cells (406) [0011] [0056-0058]. The measured process variation (corner value) may be stored in the storage space (448) of the power management circuit (434) [0060] [0074]. This enables the power management circuit to adapt the voltage of the MRAM IC (409) to adjust the power consumption and reduce errors [0038] [0047] [0052] [0060] [0074] [0088]. The process variation inherently cause differences in power consumption as discussed [0007] [0040] [0043]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory devices which each have their power consumption measured for each of a plurality of different memory operations as taught by Cho to each be the MRAM ICs with the MRAM arrays that control voltages using MTJ circuits and devices and that store the process variations of the MRAM access transistors in the power management circuit of the corresponding MRAM IC as taught by Li, where the process variations would necessarily influence the power consumption of the MRAM array as taught by Li and therefore the measured power consumption for each of the memory devices for each of the memory operations as taught by Cho.
One of ordinary skill in the art would have been motivated to make this modification because the paper by Jason Jeidecker et. al., from the JPL at NASA titled “MRAM Technology Status” (Jeidecker) teaches that MRAM is very attractive for its unlimited endurance, unlimited retention, radiation hardness, and low standby power as compared to NAND flash as taught by Jeidecker in [pg. 22, ¶1-2] [Table 5.0-1. NVM Comparison].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cho-Lee-Li-Heidecker in further view of US Patent Application Publication No. US 2022/0382466 A1 (Zhu).
Regarding claim 5:
The storage device of claim 1 is made obvious by Cho-Lee-Li-Heidecker.
Cho does not explicitly disclose, but Zhu teaches, wherein: the storage controller is further configured to correct the plurality of power information based on changes in external factors that affect the power consumptions of the plurality of memory devices (by teaching to correct individual power consumption values based on environmental conditions, such as temperature, to more accurately reflect the actual power consumption values [0051]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power consumption values determine for each command and for each memory device as taught by Cho with the temperature correction as taught by Zhu.
One of ordinary skill in the art would have been motivated to make this modification because it would more accurately reflect the actual power consumption as taught by Zhu in [0051].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cho-Lee-Li-Heidecker in further view of Zhu in further view of US Patent Application Publication No. US 2023/0019224 A1 (Palmer).
Regarding claim 6:
The storage device of claim 5 is made obvious by Cho-Lee-Li-Heidecker in further view of Zhu.
Cho does not explicitly disclose, but Zhu teaches, wherein: the external factors include a surrounding temperature of each of the plurality of memory devices (through the analysis performed for claim 5).
Cho in view of Zhu does not explicitly disclose, but Palmer teaches and an access frequency to each of the plurality of memory devices of the storage controller (by teaching that trim settings can affect power consumption, and include a clock setting (access frequency to each of the plurality of memory devices of the storage controller). Trim settings may be stored for each power identifier, and include settings such as clock rates, capacitor charge rates, etc. [0033]. The trim settings may be used to control a command to operate at a variety of power levels, with different latencies [0033-0041]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the power profile information as taught by Cho to additionally include multiple power profiles for each of a plurality of power levels including a plurality of trim settings for each power level, including clock rates and capacitor charge rates as taught by Palmer.
One of ordinary skill in the art would have been motivated to make this modification because it allows operations that could not previously have been operated concurrently within a power budget to operate concurrently, which results in increased performance as taught by Palmer in [0041].
Response to Arguments/Amendments
In response to the amendments to the claims, the previous objections to the claims are withdrawn. However, in response to the amendments to the claims, new objections to the claims have been made as seen in the corresponding objection section above.
In response to the amendments to the claims, the previous 35 USC §112(a) rejection has been withdrawn and a new 35 USC §112(a) rejection has been made to claim 13 as seen in the corresponding rejection section above.
In response to the amendments to the claims, the 35 USC §103 rejection has been updated to claims 1, 5-6, 8-11 and 13-20 to reflect the newly amended subject matter. Applicant’s arguments have been fully considered, but are not persuasive.
Applicant argues that the process variations discussed by Li and Heidecker are magnetic variations and are specific to MRAM technology and are therefore not operation speed characteristics of transistors of a memory cell. However, nothing about the recitation of “operation speed characteristics of a memory cell” specifically excludes MRAM memory cells. In fact, a review of Li indicates that the “process variations can vary the switching speed of the access transistor (104) of the MRAM bit cell” between speeds such as typical, fast, and slow [Li, 0007] – which therefore includes an operation speed of a transistor of a memory cell and is within the broadest reasonable interpretation of the claim. The disclosure in Li is analogous to Applicant’s description of a transistor being fast, slow, or nominal/general [Applicant’s Specification, 0060]. This process variation of the switching speed of the access transistor discussed by Li is part of the measured and recorded process variation [Li, 0055, 0057, 0074]. Accordingly, the process variations discussed by Li are representative of an “operation speed characteristics of a memory cell” and therefore meet the limitations of the claim. There is nothing in the claim restricting the interpretation to NAND memory cells with a “logic gate delay” as argued by Applicant and therefore Applicant’s argument is outside the scope of the claimed invention and therefore not persuasive.
Applicant argues that Li teaches storing process variations in a “centralized storage space (448) located within a power management circuit (434), not in a corresponding memory device”. However, Applicant’s argument is not persuasive as the teachings of Li, involving a single MRAM device, were applied to the teachings of Cho which included a plurality of memory devices. Therefore, as Li was applied to each memory device of Cho, each memory device of Cho would then include the power management circuit and stored parameters and Applicant’s argument against Li individually is not persuasive when the rejection was based upon the combination of the plurality of memory devices in Cho, each modified to be the MRAM device as taught by Li. Furthermore, Li does not teach away as argued because Li because “does not criticize, discredit, or otherwise discourage the solution claimed” [MPEP 2143.01(I)] and accordingly Applicant’s argument is not persuasive.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. US 2019/0138233 A1 (Mun) teaches a peak information memory (222) that is used to determine an operation order of a set of commands on a set of memory devices [see Fig. 9C] to stay within a power budget. It may choose to delay commands that do not fit within the power budget [Fig. 13] [0031].
US Patent Application Publication No. US 2020/0209944 A1 (Palmer_2) teaches that the memory controller can monitor and sum instantaneous power usage and compare it to a threshold [0076]. If there is spare capacity available, additional operations may be queued [0077] [see Fig. 9].
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/CURTIS JAMES KORTMAN/ Primary Examiner, Art Unit 2139
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