DETAILED ACTION
Case Status
This office action is in response to remarks and amendments of 17 August 2026. Claims 1-20 have been examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5, 8-10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Zeleniak et al., Pub. No.: US 20220107818, hereinafter Zeleniak, in view of Korotkoy-Adamenko et al., Pub. No.: US 20230305734, hereinafter Korotkoy-Adamenko, and further in view of Jang et al., Pub. No.: US 20230073239, hereinafter Jang
As per claim 1, Zeleniak discloses A method for machine learning firmware optimization, comprising:
iteratively producing, […], different versions of firmware for operating a physical memory device within a respective defined acceptable range of values for each of a plurality of operational parameters (pars. 68-69, 86-87, 93, 106 disclose iteratively producing modified firmware parameter sets by changing parameter values within respective ranges such as parameters p1 and p2);
wherein iteratively producing different versions of firmware (Zeleniak, pars. 86-87 discloses repeatedly generating and evaluating modified firmware parameter sets) comprises:
Zeleniak does not disclose, however Zeleniak in view of Korotkoy-Adamenko discloses deploying an initial version of firmware on a digital twin of the physical memory device (Zeleniak, pars. 86-88 disclose generating an initial firmware parameter set for performance evaluation by modeling and Korotkoy-Adamenko pars. 20, 27, 28, 65-68, 96 disclose simulating physical SSD hardware and firmware components (i.e. digital twin), testing execution of different firmware algorithm versions (i.e. deploy) and replacement of simulated hardware/firmware components with other versions, configuring the simulation using firmware parameters obtained from firmware code, changing firmware parameters before running other simulations, and calculating performance metrics, including latency and throughput, from operation of the simulated SSD (i.e. digital twin));
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Korotkoy-Adamenko' would have allowed the Zeleniak to implement a simulation platform to evaluate Zeleniak’s successive firmware configurations before deployment to a physical device to reduce development time and physical device testing (Zeleniak, par. 93, Korotkoy-Adamenko, pars. 23, 28).
determining an initial value of a performance parameter based on operation of the digital twin according to the initial version of firmware (Zeleniak, pars. 79-80, 87-88 disclose evaluating performance metrics, including throughput and latency, for an initial firmware parameter set and Korotkoy-Adamenko pars. 20, 27, 28, 65-68, 96, as discussed above, disclose determining based on operation of a simulation of a physical device (i.e. digital twin));
producing a modified version of firmware (see rejections above including Zeleniak, par. 87 discloses changing a firmware parameter);
deploying the modified version of firmware on the digital twin (see Zeleniak and Korotkoy-Adamenko as cited above); and
determining a next value of the performance parameter based on operation of the digital twin according to the modified version of firmware until the next value of the performance parameter meets a target value (Zeleniak, pars. 69, 87, 111-112 disclose repeatedly calculating performance metrics for modified parameter sets until performance restrictions are satisfied and Korotkoy-Adamenko pars. 20, 27, 28, 65-68, 96, as discussed above, disclose determining based on operation of a simulation of a physical device (i.e. digital twin)); and
deploying one of the different versions of firmware that meets the target value for the performance parameter on the physical memory device to operate the physical memory device (Zeleniak, pars. 61, 75, 95 disclose incorporating optimized development stage parameters into FTL firmware code for application and operation of a physical SSD (i.e. deploy)).
Zeleniak does not expressly disclose, however Jang discloses iteratively producing by a machine learning algorithm (Jang, pars. 31, 65, 69-72 discloses deriving new firmware parameters using machine learning and repeating the optimization).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Jang would have allowed Zeleniak to implement machine learning optimization to automate parameter selection and reduce trial and error tuning and developer effort (Jang, pars. 24, 61 and Zeleniak, par. 61).
As per claim 8, it includes the same or similar subject matter as claim 1 and is therefore likewise rejected.
As per claim 2, Zeleniak as modified discloses The method of claim 1, further comprising iteratively producing different versions of firmware until a threshold quantity of the different versions of firmware yield a next value of the performance parameter that meets the target value (Zeleniak pars. 69, 92, 112-113 and Jang, pars. 71-72).
As per claim 3, Zeleniak as modified discloses The method of claim 2, further comprising: storing a plurality of different versions of firmware (Zeleniak pars. 92, 95 disclose storing evaluated allowable parameter sets and incorporating selected parameter sets into firmware code) regardless of whether the plurality of different versions of firmware yield a next value of the performance parameter that meets the target value (Jang, pars. 63, 66, 71);
iteratively deploying the plurality of different versions of firmware on the digital twin (Korotkoy-Adamenko, pars. 20, 28, 65-68, 96);
iteratively determining a respective value of a different performance parameter (Zeleniak pars. 79-82, 87, 106) based on operation of the digital twin according to the plurality of different versions of firmware (Korotkoy-Adamenko, pars. 20, 28, 65-68, 96); and
providing one of the plurality of different versions of firmware that meets a different target value for the different performance parameter for deployment on the physical memory device (Zeleniak pars. 61-62, 75, 79, 95).
As per claim 4, Zeleniak as modified discloses The method of claim 1, wherein iteratively producing different versions of firmware comprises:
deploying the initial version of firmware on the digital twin of the physical memory device (Korotkoy-Adamenko pars. 20, 28, 67, 68, 96);
determining a respective initial value of each of a plurality of performance parameters based on operation of the digital twin according to the initial version of firmware (Zeleniak, pars. 79-82, 87-89 disclose determining initial values of performance metrics for an initial firmware parameter set and Korotkoy-Adamenko pars. 20, 28, 67, 68, 96 discloses determining based on a digital twin);
producing a modified version of firmware (Zeleniak, par. 87);
deploying the modified version of firmware on the digital twin (Korotkoy-Adamenko pars. 20, 28, 67, 68, 96); and
determining a respective next value of each of the plurality of performance parameters based on operation of the digital twin according to the modified version of firmware until the respective next values of each of the plurality of performance parameters meet respective target values (Zeleniak, pars. 69, 82-83, 87 disclose iterative evaluation of modified parameter sets until multiple metrics satisfy their restrictions and see Korotkoy-Adamenko as cited above for digital twin operation);
wherein deploying one of the different versions of firmware comprises deploying one of the different versions of firmware that achieves the respective target values for each of the plurality of performance parameters (Zeleniak, pars. 69, 83, 87, 95).
As per claim 5, Zeleniak as modified discloses The method of claim 1, further comprising providing the one of the different versions of firmware that meets the target value for deployment (Zeleniak, pars. 61, 75, 95 disclose incorporating optimized development stage parameters into FTL firmware code for application and operation of a physical SSD) any physical memory device having a same part number as a part number of the physical memory device (Korotkoy-Adamenko, pars. 28, 30, 68, 96).
As per claim 9, Zeleniak as modified discloses The apparatus of claim 8, wherein the instructions to produce modified version of firmware comprise instructions to modify values of one or more of the plurality of operational parameters (Zeleniak, pars., 86-87, 106 and Jang, pars. 31, 65, 69-72).
As per claim 10, Zeleniak as modified discloses The apparatus of claim 9, wherein the performance parameter comprises one or more of a group of performance parameters including random read performance, sequential write performance, and input/output operations per second (see rejection of claims 8 and 9 above including Zeleniak par. 79-81).
As per claim 13, Zeleniak as modified discloses The apparatus of claim 8, wherein the physical memory device comprises a managed NAND memory device or a DRAM memory device (Zeleniak, pars. 55-58).
Claims 6, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Zeleniak as modified further in view of Brock et al., Pub. No.: US 20170091357 A1, hereinafter Brock.
As per claim 6, Zeleniak as modified discloses The method of claim 1, further comprising:
providing a respective indication of power consumed by the digital twin as operated by each different version of firmware (Korotkoy-Adamenko, pars. 3, 28); and the combination does not disclose but Brock discloses providing a respective indication of a thermal response of the digital twin as operated by each different version of firmware (Brock, fig.’s 1-3, pars. 26, 47, 51, 67).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Brock would have allowed the combination to incorporate power and thermal models in simulated SSD to evaluate power consumption and thermal behavior for each firmware configuration which helps evaluate thermal constraints before deployment on a physical memory device.
As per claim 11, Zeleniak as modified discloses The apparatus of claim 8. The combination does not disclose but Brock discloses wherein the digital twin further includes a thermal model of the physical memory device; wherein the thermal model is configured to provide an indication of a thermal response of the digital twin as operated by the development firmware (Korotkoy-Adamenko, pars. 3, 28, Brock, fig.’s 1-3, pars. 26, 47, 51, 67).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Brock would have allowed the combination to incorporate power and thermal models in simulated SSD to evaluate power consumption and thermal behavior for each firmware configuration which helps evaluate thermal constraints before deployment on a physical memory device.
As per claim 12, Zeleniak as modified discloses The apparatus of claim 11, wherein the plurality of operational parameters include one or more of a group of operational parameters including (Zeleniak, pars. 86-87, 106) buffer depth, dynamic voltage frequency scaling, and thermal constraints (Korotkoy-Adamenko, pars. 3, 28, Brock, fig.’s 1-3, pars. 13, 16, 17, 26, 44, 47, 51, 57, 59, 67).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Brock would have allowed the combination to incorporate power and thermal models in simulated SSD to evaluate power consumption, DVFS, and thermal behavior for each firmware configuration which helps evaluate power consumption, DVFS, and thermal constraints before deployment on a physical memory device.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Zeleniak as modified further in view of Franceschini et al., Pub. No.: US 20140359197 A1, hereinafter Franceschini.
As per claim 7, Zeleniak as modified discloses The method of claim 1, wherein iteratively producing, by the machine learning algorithm, different versions of firmware comprises iteratively producing different versions of firmware (Zeleniak, pars. 68-69, 87, Jang, pars. 65, 69-72) and the combination does not disclose but Franceschini discloses by a reinforcement learning algorithm or a genetic algorithm (Franceschini, pars. 3, 24, 30, 35). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Franceschini would have allowed the combination to incorporate RL algorithms in order to optimize flash control parameters based on learned performance rewards, resulting in long term storage improvements.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Korotkoy-Adamenko in view of Zeleniak.
As per claim 14, Korotkoy-Adamenko discloses A non-transitory machine readable medium storing instructions executable to:
operate a digital twin of a physical memory device according to development firmware (pars. 20, 24, 27, 28, 68 disclose simulation platform modeling SSD hardware and firmware algorithms using configurable parameters obtained from firmware code). Korotkoy-Adamenko does not disclose however Zeleniak discloses within a respective acceptable range of values for each of a plurality of operational parameters defined in the development firmware (Zeleniak, pars. 68-69, 86-87, 93, 106, 111-112 disclose firmware parameters p1, p2 having respective ranges of permissible values, iteratively evaluating modified firmware parameter sets, and continuing the evaluation until performance restrictions are satisfied) ;
wherein the digital twin includes a model of hardware of the physical memory device (Korotkoy-Adamenko pars. 20, 27, 32-37);
wherein the model of hardware comprises abstractions of hardware components of the physical memory device (Korotkoy-Adamenko pars. 20, 65, 70, 75 disclose hardware components represented by algorithmic software simulation entities);
determine a value of a performance parameter of the digital twin based on operation thereof (see Korotkoy-Adamenko as cited above including par. 67-68, 93, 96 which disclose at least a simulation core engine that calculates multiple target metric values);
iteratively optimize the development firmware with respect to a target value for the performance parameter defined in the development firmware (Korotkoy-Adamenko pars. 24, 28, 96 disclose supporting testing of different firmware algorithm versions and reconfiguring firmware parameters for successive simulations; Zeleniak, pars. 68-69, 86-87, 93, 106, 111-112 disclose firmware parameters p1, p2 having respective ranges of permissible values, repeatedly generating and evaluating modified firmware parameter sets, and continuing the evaluation until performance restrictions are satisfied)); and
deploy operational firmware on the physical memory device to operate the physical memory device, wherein the operational firmware is based on the optimized development firmware (Zeleniak, pars. 61-63, 75, 95 disclose finding optimized firmware parameters during development, incorporating those parameters into FTL firmware code, and applying the firmware to operate the physical SSD (i.e. deploy)).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Zeleniak would have allowed Korotkoy-Adamenko to incorporate iterative parameter optimization in Korotkoy-Adamenko’s simulation platform to optimize firmware configurations within defined parameter ranges until target performance restrictions are satisfied, thereby reducing physical device testing and development time (Zeleniak, pars. 87, 93, Korotkoy-Adamenko, pars. 23, 28).
As per claim 15, Korotkoy-Adamenko as modified discloses The medium of claim 14, wherein the instructions to iteratively optimize the development firmware comprise instructions to iteratively:
produce a modified version of the development firmware (see rejections above including Zeleniak, par. 87 discloses changing a firmware parameter);
operate the digital twin according to the modified version of the development firmware (Zeleniak, pars. 86-88 disclose generating an initial firmware parameter set for performance evaluation by modeling and Korotkoy-Adamenko pars. 20, 27, 28, 65-68, 96 disclose simulating physical SSD hardware and firmware components (i.e. digital twin), testing execution of different firmware algorithm versions (i.e. deploy) and replacement of simulated hardware/firmware components with other versions, configuring the simulation using firmware parameters obtained from firmware code, changing firmware parameters before running other simulations, and calculating performance metrics, including latency and throughput, from operation of the simulated SSD (i.e. digital twin); and
determine a next value of the performance parameter based on operation of the digital twin according to the modified version of the development firmware until the next value of the performance parameter meets the target value (Zeleniak, pars. 69, 87, 111-112 disclose repeatedly calculating performance metrics for modified parameter sets until performance restrictions are satisfied and Korotkoy-Adamenko pars. 20, 27, 28, 65-68, 96, as discussed above, disclose determining based on operation of a simulation of a physical device (i.e. digital twin)).
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Korotkoy-Adamenko as modified further in view of Brock.
As per claim 16, Korotkoy-Adamenko as modified discloses The medium of claim 14, wherein the digital twin (par. 20, 27) and the combination does not disclose but Brock discloses further includes a power model of the physical memory device; wherein the power model is configured to provide an indication of power consumed by the digital twin as operated by the development firmware (Brock, pars. 36-39, 51).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Brock would have allowed the combination to incorporate power and thermal models in the simulation to evaluate power consumption and thermal behavior for each firmware configuration which helps evaluate power and thermal constraints before deployment on a physical memory device.
As per claim 17, Korotkoy-Adamenko as modified discloses The medium of claim 16, wherein the digital twin further includes a thermal model of the physical memory device; wherein the thermal model is configured to provide an indication of a thermal response of the digital twin as operated by the development firmware (see rejection of claim 16).
As per claim 18, Korotkoy-Adamenko as modified discloses The medium of claim 17, wherein the thermal model is further configured to provide the indication of the thermal response based on the indication of power consumed (Brock, pars. 36, 37, 47 disclose calculating simulated component temperatures based on modeled power consumption).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Korotkoy-Adamenko as modified further in view of Lo et al., Pub. No.: US 20220121798 A1, hereinafter Lo.
As per claim 19, Korotkoy-Adamenko as modified discloses The medium of claim 14. The combination does not disclose but Lo discloses wherein the model of hardware comprises a register transfer level (RTL) model of the physical memory device (Lo, pars. 15-16).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Lo would have allowed the combination to incorporate RTL hardware modeling into Korotkoy-Adamenko’s simulation platform to provide more detailed hardware abstractions to improve simulation.
As per claim 20, Korotkoy-Adamenko as modified discloses The medium of claim 14. The combination does not disclose but Lo discloses wherein the model of hardware comprises an embedded component model of the physical memory device that represents a physical layout of the hardware components (Lo, par. 16).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the cited references because Lo would have allowed the combination to incorporate physical layout modeling into Korotkoy-Adamenko’s simulation platform to provide more detailed hardware component placement information to improve simulation.
Response to Arguments
Applicant's arguments filed of 17 August 2026 have been considered.
The 35 USC 101 rejection is withdrawn in view of the argument that the claimed invention integrates the abstract idea into a practical application that provides an improvement to a technical field. It is noted that the claims themselves reflect the disclosed improvement. That is, the claims include the components or steps of the invention that provide the improvement described in the specification. MPEP § 2106.04(d)(1).
With respect to the prior art rejection, at least Zeleniak, Korotkoy-Adamenko and Jang, have been introduced as new reference to address claim amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SYED H HASAN/Primary Examiner, Art Unit 2154
