Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
This Office action is in response to Applicant's communication filed November 12, 2025 in response to the Office action dated August 12,2025.
Claims 1-5, 9, 11, 13, 18 and 20 have been amended. Claims 1-20 are pending in this application.
NOTE:
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art reference and any interpretations of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Specification
In view of Applicant’s amendment, objections to the specification are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et. al. U.S. Patent Pub No. 2008/0288711 (hereinafter Jung) in view of Hillel et. al. US Patent Pub.No. 20230244618 (hereinafter Hillel), further in view of Freyensee et al. US Patent Pub.No. 2019/0303003 (hereinafter Freyensee).
Regarding Claim 1, Jung teaches a method for processing data, comprising: at storage device having a chip, including a first processor and a second processor, and a non-volatile memory storing a first data block set (Fig.2, Para35-40 "the present invention provides a method for sharing a nonvolatile memory and a device having a one-chip multimedia platform" Para42-46 "a first volatile memory which is a temporary memory device of the main processor"): generating a first request for the first data block set by the second processor (Fig.1, Para20-27"the main processor core 148 reads the data for operating the portable terminal 100 that are stored in the NAND flash memory 162 through the NAND interface 142 and stores the data in the buffer memory 164 in the memory chip 115 accessed through the SD interface 150");
and in response to the first request, extracting the first data block set from the non-volatile memory by the first processor; and providing, by the first processor, the first data block set to the second processor (Fig.1,2; Para21-29 "The main processor core 148 delivers the read boot data to the multimedia processor core 174 through the host interface 152 and 172.").
However, Jung fails to teach but Hillel teaches sending the first request from the second processor to the first processor (Fig.32;Para12-13 "a processor-to-processor data transfer system may include a first processor programmed to: load data from a memory using a memory mapped Interface" Para308-310,463-469 "A processor-to-processor data transfer system, comprising: a first processor programmed to: load data from a memory using a memory mapped interface; generate a data packet for transferring processed data via a non-memory mapped stream interface; and send the generated data packet, including the processed data, to a second processor").
Jung and Hillel are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Jung, and incorporating the processing method, as taught by Hillel.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize more efficient approach of data management, as suggested by Hillel (Para2-7).
However, the combination of Jung and Hillel fails to teach but Freyensee teaches wherein the first processor includes a memory controller configured to access and manage data stored in the non-volatile memory (Fig.2,4; Para18-19; 26-27“As shown in FIG. 2, controller logic 282 includes one or more processor cores or processors 284 and memory controller logic 286, and is coupled to Random Access Memory (RAM) 288, firmware storage 290, and one or more memory modules or dies 292-1 to 292-n (which may include NAND flash, NOR flash, three dimensional cross point memory or other types of non-volatile memory)”).
Jung, Hillel, and Freyensee are analogous art because they are from the same field of endeavor. They all relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Jung and Hillel, and incorporating the controller, as taught by Freyensee.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize more efficient approach of data management, as suggested by Freyensee (Para2-7).
Regarding claim 2, the combination of Jung, Hillel, and Freyensee teaches all the limitations of the base claims as outlined above.
Further, Jung teaches wherein the storage device further includes a volatile memory shared by the first processor and second processor, the method further comprising: temporarily storing the first request and the first data block set internally in the volatile memory of the storage device(Fig.2, Para35-40, 21-29).
Regarding claim 3, the combination of Jung, Hillel, and Freyensee teaches all the limitations of the base claims as outlined above.
Further, Jung teaches wherein the storage device further includes a volatile memory, and sending the first request from the second processor to the first processor further comprises: storing by the second processor the first request in the volatile memory; and extracting by the first processor the first request from the volatile memory(Fig.1,2, Para 21-2, 42-45).
Regarding claim 4, the combination of Jung, Hillel, and Freyensee teaches all the limitations of the base claims as outlined above.
Further, Jung teaches wherein the storage device further includes a volatile memory, and providing, by the first processor, the first data block set to the second processor further comprises: storing by the first processor the first data block set in a portion of the volatile memory specified by the second processor; and extracting by the second processor the first data block set from the portion of the volatile memory(Fig.1,2, Para 21-2, 42-45).
Regarding claim 5, the combination of Jung, Hillel, and Freyensee teaches all the limitations of the base claims as outlined above.
Further, Hillel teaches wherein the storage device further includes a volatile memory shared by the first processor and second processor, the method further comprising: creating a submission queue and a completion queue for the volatile memory, wherein each of the submission queue and the completion queue is stored in a respective circular buffer(Fig.22 Para221-223).
Regarding claim 6, the combination of Jung, Hillel, and Freyensee teaches all the limitations of the base claims as outlined above.
Further, Hillel teaches further comprising, by the second processor: adding the first request into a tail of the submission queue, the first request including a first request identifier and a first logical address of the first data block set; updating a first tail pointer corresponding to the tail of the submission queue; reading the first data block set from a head of the completion queue; and updating a second head pointer corresponding to the head of the completion queue(Fig.22 Para221-223).
Regarding claim 7, the combination of Jung, Hillel, and Freyensee teaches all the limitations of the base claims as outlined above.
Further, Hillel teaches further comprising, by the first processor: reading the first request from a head of the submission queue; updating a first head pointer corresponding to the head of the submission queue; adding a first data packet including a first request identifier and a first destination address into a tail of the completion queue; and updating a second tail pointer corresponding to the tail of the completion queue(Fig.22 Para221-223).
Regarding claim 8, the combination of Jung, Hillel, and Freyensee teaches all the limitations of the base claims as outlined above.
Further, Hillel teaches wherein the second processor includes a plurality of processor cores, the method further comprising: creating a plurality of submission queues, a second number of the plurality of processor cores equal to a first number of the plurality of submission queues(Fig.22 Para221-223).
Regarding claim 9, the combination of Jung, Hillel, and Freyensee teaches all the limitations of the base claims as outlined above.
Further, Jung teaches wherein: the storage device further includes an external interface and an internal interface; the external interface is configured to couple the first processor to a host device distinct from the storage device; and the internal interface is configured to couple the first processor to the second processor internally (Fig.1,2; Para21-29 "The main processor core 148 delivers the read boot data to the multimedia processor core 174 through the host interface 152 and 172.").
Regarding claim 10, the combination of Jung, Hillel, and Freyensee teaches all the limitations of the base claims as outlined above.
Further, Hillel teaches further comprising, after by the first processor extracting the first data block set from the non-volatile memory, implementing by the first processor one or more of: decrypting the first data block set extracted from the non-volatile memory; checking a validity of the first data block set based on associated integrity data; and in accordance with detection of a data error, correcting the data error in the first data block set (Fig.29, 36; Para12-13 "In an embodiment, a data processing unit may include a data analysis unit configured to acquire a plurality of data elements from a memory, evaluate each of the plurality of data elements relative to at least one criteria, and generate an output that includes a plurality of validity indicators identifying a first plurality of data elements among the plurality of data elements that validly satisfy the at least one criteria and identifying a second plurality of data elements among the plurality of data elements that do not validly satisfy the criteria." Para272-273).
Regarding claims 11-20, the combination of Jung, Hillel, and Freyensee these claims according to the reasoning set forth in claim 1-10.
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new grounds of rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135