Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 25, 2026 has been entered.
Response to Amendment
Claims 1,5, 11, 18, and 19 have been amended. Claims 1-20 are pending in this application.
NOTE:
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art reference and any interpretations of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1, 11, and 18 states “the first processor includes a memory controller configured to access and manage data stored in the non-volatile memory.” However, the specification does not provide a written description in such a manner to reasonably convey to one skilled in the art before the effective filling date of claimed invention was made, that the Applicant had possession of the first processor including a memory controller. The specification teaches memory controller as an example of the first processor not a processor including a controller (Fig.5, Para48 “the first processor 504 (e.g., a memory controller 202) extracts…”). One of ordinary skill would not have known how this structure is designed.
Claims 2-10, 12-17, 19-20 inherit all the deficiencies of claim 1,11, 18 and are therefore rejected under the same
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et. al. U.S. Patent Pub No. 2024/0152392 (hereinafter Shin) in view of Bi et. al. US Patent Pub.No. 2024/0362169 (hereinafter Bi).
Regarding Claim 1, Shin teaches A method for processing data, comprising: at a storage device, including a first processor, a second processor (Fig.2,3, Para105-110 "The neural core SoC 10 may be a system on a chip device." SoC10 includes multiple processors, Para118-119), and a non-volatile memory storing a first data block set, wherein the first processor includes a memory controller configured to access and manage data stored in the non-volatile memory (Fig.2,3, 7; Para105-110, 118-121, 125-128 "The non-volatile memory controller 4000 may control tasks of reading from or writing onto the non-volatile memory 31."): and the first processor and the second processor are integrated on a chip Fig.2,3, 7; Para105-110, 118-121, 125-128): executing an embedded operating system by the second processor, including generating a first request for the first data block set by the second processor; sending the first request from the second processor to the first processor (Fig.3, 7; Para101-105 "The first neural processing device 1 and the second neural processing device 2 may be connected to each other via the external interface 3 and share data and control signals", Para163-165 "The neural processors 1000 may transmit data to each other via the global interconnection 6000."); and in response to the first request providing, by the first processor, the first data block set to the second processor; and processing the first data block set in the embedded operating system by the second processor (Fig.3,7, Para128-131 "The command processor 7000 may generate tasks via the control signals received from the CPU 20 and transmit the control signals to neural processors 1000" Para163-165 "The neural processors 1000 may transmit data to each other via the global interconnection 6000.").
However, Shin fails to teach but Bi teaches extracting the first data block set from the non- volatile memory by the first processor (Fig.8, 9,12; Para144-146, 251-254 “Operation 1, check whether the logical block address to be read overlaps with the logical block address in the write buffer by using the core processor (i .e., Corel); pack the logical block addresses that are not maintained in the write buffer to obtain the first submission queue” read operation corresponds to extracting).
Shin and Bi are analogous art because they are from the same field of endeavor. They both relate to data management in a storage system.
Therefore, before the effective filling date of claimed invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Shin, and incorporating the extracting method, as taught by Bi.
One of ordinary skill in the art would have been motivated to do this modification in order to utilize more efficient approach of data management, as suggested by Bi (Para2-3).
Regarding claim 2, the combination of Shin and Bi teaches all the limitations of the base claims as outlined above.
Further, Shin teaches wherein the storage device further includes a volatile memory shared by the first processor and second processor, the method further comprising: temporarily storing the first request and the first data block set internally in the volatile memory of the storage device(Fig.2,3 “shared memory 2000”, Para105-110, 118-119).
Regarding claim 3, the combination of Shin and Bi teaches all the limitations of the base claims as outlined above.
Further, Shin teaches wherein the storage device further includes a volatile memory, and sending the first request from the second processor to the first processor further comprises: storing by the second processor the first request in the volatile memory; and extracting by the first processor the first request from the volatile memory(Fig.2,3; Para105-110, 118-119).
Regarding claim 4, the combination of Shin and Bi teaches all the limitations of the base claims as outlined above.
Further, Shin teaches wherein the storage device further includes a volatile memory, and providing, by the first processor, the first data block set to the second processor further comprises: storing by the first processor the first data block set in a portion of the volatile memory specified by the second processor; and extracting by the second processor the first data block set from the portion of the volatile memory(Fig.2,3; Para105-110, 118-119, Para128-131 "The command processor 7000 may generate tasks via the control signals received from the CPU 20 and transmit the control signals to neural processors 1000" Para163-165 "The neural processors 1000 may transmit data to each other via the global interconnection 6000.").
Regarding claim 5, the combination of Shin and Bi teaches all the limitations of the base claims as outlined above.
Further, Bi teaches wherein the storage device further includes a volatile memory shared by the first processor and second processor, the method further comprising: creating a submission queue and a completion queue for the volatile memory, wherein each of the submission queue and the completion queue is stored in a respective circular buffer; and managing a plurality of memory access requests of the second processor for data stored in the first processor, the plurality of memory access requests including the first request (Fig.8,9; Para136-144 “the first processor 121 is configured to: check whether the logical block address corresponding to the host read command is maintained in a write buffer, and submit the logical block address to a first submission queue, if the logical block address is not maintained in the write buffer”).
Regarding claim 7, the combination of Shin and Bi teaches all the limitations of the base claims as outlined above.
Further, Bi teaches further comprising, by the first processor: reading the first request from a head of the submission queue; updating a first head pointer corresponding to the head of the submission queue; adding a first data packet including a first request identifier and a first destination address into a tail of the completion queue; and updating a second tail pointer corresponding to the tail of the completion queue(Fig.8,9; Para136-144).
Regarding claim 8, the combination of Shin and Bi teaches all the limitations of the base claims as outlined above.
Further, Shin teaches wherein the second processor includes a plurality of processor cores, the method further comprising: creating a plurality of submission queues, a second number of the plurality of processor cores equal to a first number of the plurality of submission queues(Fig.2,3, Para105-110 "The neural core SoC 10 may be a system on a chip device." SoC10 includes multiple neural cores, Para118-119).
Regarding claim 9, the combination of Shin and Bi teaches all the limitations of the base claims as outlined above.
Further, Shin teaches wherein: the storage device further includes an external interface and an internal interface; the external interface is configured to couple the first processor to a host device distinct from the storage device; and the internal interface is configured to couple the first processor to the second processor internally (Fig.2,3, Para105-110, 118-119).
Regarding claim 10, the combination of Shin and Bi teaches all the limitations of the base claims as outlined above.
Further, Shin teaches further comprising, after by the first processor extracting the first data block set from the non-volatile memory, implementing by the first processor one or more of: decrypting the first data block set extracted from the non-volatile memory; checking a validity of the first data block set based on associated integrity data; and in accordance with detection of a data error, correcting the data error in the first data block set (Fig.50; Para489-492 “The artificial neural network model 40000 may represent a machine learning model having an ability to solve problems by learning to reduce the error between an accurate output corresponding to a particular input and an inferred output by repeatedly adjusting the weight of the synapse by nodes”).
Regarding claims 11-20, the combination of Shin and Bi these claims according to the reasoning set forth in claim 1-5, 7-10.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, including the reference(s) cited below, neither anticipates, nor renders obvious the recited combination as a whole; including at least the limitations of : “further comprising, by the second processor: adding the first request into a tail of the submission queue, the first request including a first request identifier and a first logical address of the first data block set; updating a first tail pointer corresponding to the tail of the submission queue; reading the first data block set from a head of the completion queue; and updating a second head pointer corresponding to the head of the completion queue.”
Response to Arguments
Applicant's arguments with respect to claims 1-20 have been considered but are moot in view of the new grounds of rejection above.
Conclusion
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TASNIMA . MATIN
Primary Examiner
Art Unit 2135
/TASNIMA MATIN/Primary Examiner, Art Unit 2135
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