DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-13 are pending.
3. This office action is in response to the Applicant’s communication filed 12/26/2025 in response to PTO Office Action mailed 10/02/2025. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
Response to Arguments
4. Applicant’s arguments with respect to the amended independent claims have been considered but are moot in view of the new ground(s) of rejection in which the Examiner has cited newly presented prior art, Dierkhising et al. (US Pub. No. 2019/0228167 A1 hereinafter “Dierkhising”) in view of Natarajan et al. (US Pub. No. 2025/0306666 A1 hereinafter “Natarajan”), as necessitated by the amended independent claims disclosing wherein the at least one output device comprises a solid-state disk (SSD) device using a non-volatile memory express (NVMe) protocol; and wherein the connection state indicates that an operation of a first mode corresponding to the first mode integrating circuit fails, or an operation of a second mode corresponding to the second mode integrating circuit fails.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yun-Tien, Liu (NPL: English Translation of TWM634558 (U) 2022-11-21 hereinafter “Yun-Tien”) in view of Dierkhising et al. (US Pub. No. 2019/0228167 A1 hereinafter “Dierkhising”), and further in view of Natarajan et al. (US Pub. No. 2025/0306666 A1 hereinafter “Natarajan”).
Referring to claim 1, Yun-Tien discloses a universal serial bus (USB) circuit (Yun-Tien – Par. [0013] discloses a USB integrated circuit 100.), comprising:
an upstream port interface circuit configured to be connected to a USB host (Yun-Tien – Par. [0013] discloses an upstream connector (not shown in FIG. 1 ) to couple to a USB host. Par. [0021] discloses an upstream port interface circuit 240.);
a routing circuit connected to the upstream port interface circuit (Yun-Tien – Par. [0023] discloses a routing circuit 220 connected to the upstream port interface circuit 240 via a display port interface circuit 260.);
a first mode integrating circuit (Yun-Tien – Par. [0034-0036, 0051-0054]);
a second mode integrating circuit (Yun-Tien – Par. [0034-0036, 0051-0054]);
a downstream port interface circuit connected to at least one of the first mode integrating circuit and the second mode integrating circuit, and configured to be connected to at least one output device (Yun-Tien – See par. [0019-0021] disclosing the USB-C connector CND_1 and the USB port physical layer circuit 280_1 and the USB-C connector CND_2 and the USB port physical layer circuit 280_2 are respectively used as downstream ports (Downstream Facing Port, DFP). The DP port physical layer circuit 280_3 and the DP connector CND_3 serve as the downlink port. The electronic device 20 can be coupled to a USB device through a downstream port.); and
a controlling circuit connected to the routing circuit, and configured to determine whether to connect the routing circuit to the first mode integrating circuit or the second mode integrating circuit according to a connection state between the USB circuit and the USB host (Yun-Tien – See par. [0031, 0034-0039].).
Yun-Tien fails to explicitly disclose wherein the at least one output device comprises a solid-state disk (SSD) device using a non-volatile memory express (NVMe) protocol; and wherein the connection state indicates that an operation of a first mode corresponding to the first mode integrating circuit fails, or an operation of a second mode corresponding to the second mode integrating circuit fails.
Dierkhising discloses wherein the at least one output device comprises a solid-state disk (SSD) device using a non-volatile memory express (NVMe) protocol (Dierkhising – Par. [0019] discloses the NVM device 170 is included in one of a solid-state drive (SSD) configured to communicate using NVMe.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Dierkhising’s teachings with Yun-Tien’s techniques for the benefit of the use of a NVM device may be associated with an instruction file that specifies one or more restrictions for accessing data stored in the NVM device (Dierkhising – Par. [0012]).
Yun-Tien and Dierkhising fail to explicitly disclose wherein the connection state indicates that an operation of a first mode corresponding to the first mode integrating circuit fails, or an operation of a second mode corresponding to the second mode integrating circuit fails.
Natarajan discloses wherein the connection state indicates that an operation of a first mode corresponding to the first mode integrating circuit fails, or an operation of a second mode corresponding to the second mode integrating circuit fails (Natarajan – Par. [0028] discloses the When a USB 2 device is connected to a connector of the USB interface that supports USB 3 (e.g., in the example of FIG. 1, connector 110-3 or connector 110-4), the USB 3 port (e.g., in the example of FIG. 1, Port 5 or Port 6 of ports 120) begins the negotiation of the data transfer protocol and triggers the LTSSM Rx.Detect circuit and controller. Because the device is a USB 2 device, the LTSSM Rx.Detect of the USB 3 port will fail.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Natarajan’s teachings with Yun-Tien and Dierkhising’s techniques for the benefit of the use of Universal Serial Bus (USB) systems, and in particular, to power savings in USB systems that may support multiple modes of operation and data transfer rates according to different generations and versions of the USB standards (Natarajan – Par. [0001]).
Referring to claim 2, Yun-Tien, Dierkhising and Natarajan disclose the USB circuit according to claim 1, wherein when the connection state indicates that an operation of a first mode corresponding to the first mode integrating circuit fails, the controlling circuit switches the routing circuit from being connected to the first mode integrating circuit to being connected to the second mode integrating circuit according to the connection state (Yun-Tien – See par. [0043, 0046].).
Referring to claim 3, Yun-Tien, Dierkhising and Natarajan disclose the USB circuit according to claim 2, wherein when the routing circuit switches from being connected to the first mode integrating circuit to being connected to the second mode integrating circuit, the upstream port interface circuit re-establishes a connection relationship with the USB host according to a plurality of reconnection commands, so that the second mode integrating circuit transmits data from the USB host according to the connection relationship (Yun-Tien – See par. [0024-0025].).
Referring to claim 4, Yun-Tien, Dierkhising and Natarajan disclose the USB circuit according to claim 1, wherein the first mode integrating circuit comprises a plurality of tunnel routers, wherein the tunnel routers respectively correspond to different tunnel protocols and comply with a USB4 specification (Yun-Tien – See par. [0035].).
Referring to claim 5, Yun-Tien, Dierkhising and Natarajan disclose the circuit according to claim 1, wherein the second mode integrating circuit has a plurality of connection protocols, wherein the connection protocols respectively correspond to different transmission speeds (Yun-Tien – See par. [0034-0036, 0051-0054].).
Referring to claim 6, Yun-Tien, Dierkhising and Natarajan disclose the USB circuit according to claim 5, wherein when the connection state indicates that an operation of a second mode corresponding to the second mode integrating circuit fails, the controlling circuit connects the routing circuit to the second mode integrating circuit based on the connection protocols sequentially according to the connection state and the transmission speeds (Yun-Tien – See par. [0034-0036, 0051-0054].).
Referring to claim 7, Yun-Tien, Dierkhising and Natarajan disclose a USB circuit according to claim 1, wherein the routing circuit comprises: a first multiplexer connected to the upstream port interface circuit and the controlling circuit (Yun-Tien – See par. [0031-0040].); a second multiplexer connected to the controlling circuit and the second mode integrating circuit, and configured to be connected to the first multiplexer (Yun-Tien – See par. [0031].); and a third multiplexer connected to the controlling circuit and the first mode integrating circuit, and configured to be connected to the first multiplexer (Yun-Tien – See par. [0037].).
Referring to claim 8, Yun-Tien, Dierkhising and Natarajan disclose the USB circuit according to claim 7, wherein the first multiplexer chooses to be connected to the second multiplexer or the third multiplexer according to a first controlling signal from the controlling circuit, wherein the second multiplexer selects one of a plurality of connection protocols to be connected to the second mode integrating circuit according to a second controlling signal from the controlling circuit, wherein the third multiplexer selects one of a plurality of tunnel protocols to be connected to the first mode integrating circuit according to a third controlling signal from the controlling circuit (Yun-Tien – See par. [0032-0035].).
Referring to claim 9, Yun-Tien, Dierkhising and Natarajan disclose the USB circuit according to claim 1, further comprising: a power delivery controller connected to the controlling circuit, and configured to perform a communication operation with the USB host, wherein the controlling circuit determines the connection state based on a success or a failure of the communication operation (Yun-Tien – See par. [0032-0035].).
Referring to claim 10, Yun-Tien, Dierkhising and Natarajan disclose the USB circuit according to claim 1, further comprising: a buffer connected to the first mode integrating circuit, the second mode integrating circuit, and the downstream port interface circuit (Yun-Tien – See par. [0012-0016].).
Referring to claim 11, Yun-Tien, Dierkhising and Natarajan disclose the USB circuit according to claim 1, further comprising: a retimer connected to the upstream port interface circuit and the downstream port interface circuit (Yun-Tien – See par. [0024].).
Referring to claim 12, note the rejections of claim 1 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 13, Yun-Tien discloses a USB device (Yun-Tien – Par. [0021] discloses a USB electronic device 20.), comprising:
at least one upstream connection port (Yun-Tien – Par. [0018] discloses the USB-C connector CNU can be coupled to the USB integrated circuit 200 through the channel physical layer circuit 270_1 and/or the channel physical layer circuit 270_2. In this embodiment, the USB-C connector CNU and the channel physical layer circuits 270_1 and 270_2 serve as the upstream Facing Port (UFP).);
at least downstream connection port (Yun-Tien – Par. [0019] discloses the USB-C connector CND_1 and the USB port physical layer circuit 280_1 and the USB-C connector CND_2 and the USB port physical layer circuit 280_2 are respectively used as downstream ports (Downstream Facing Port, DFP).); and
a USB circuit (Yun-Tien – Par. [0013] discloses a USB integrated circuit 100.), comprising:
an upstream port interface circuit configured to be connected to a USB host (Yun-Tien – Par. [0013] discloses an upstream connector (not shown in FIG. 1 ) to couple to a USB host. Par. [0021] discloses an upstream port interface circuit 240.) through the at least one upstream connection port;
a routing circuit connected to the upstream port interface circuit (Yun-Tien – Par. [0023] discloses a routing circuit 220 connected to the upstream port interface circuit 240 via a display port interface circuit 260.);
a first mode integrating circuit (Yun-Tien – Par. [0034-0036, 0051-0054]);
a second mode integrating circuit (Yun-Tien – Par. [0034-0036, 0051-0054]);
a downstream port interface circuit connected to at least one of the first mode integrating circuit and the second mode integrating circuit, and configured to be connected to at least one output device through the at least one downstream connection port (Yun-Tien – See par. [0019-0021] disclosing the USB-C connector CND_1 and the USB port physical layer circuit 280_1 and the USB-C connector CND_2 and the USB port physical layer circuit 280_2 are respectively used as downstream ports (Downstream Facing Port, DFP). The DP port physical layer circuit 280_3 and the DP connector CND_3 serve as the downlink port. The electronic device 20 can be coupled to a USB device through a downstream port.); and
a controlling circuit connected to the routing circuit, and configured to determine whether to connect the routing circuit to the first mode integrating circuit or the second mode integrating circuit according to a connection state between the USB circuit and the USB host (Yun-Tien – See par. [0031, 0034-0039].).
Yun-Tien fails to explicitly disclose wherein the at least one output device comprises a solid-state disk (SSD) device using a non-volatile memory express (NVMe) protocol; and wherein the connection state indicates that an operation of a first mode corresponding to the first mode integrating circuit fails, or an operation of a second mode corresponding to the second mode integrating circuit fails.
Dierkhising discloses wherein the at least one output device comprises a solid-state disk (SSD) device using a non-volatile memory express (NVMe) protocol (Dierkhising – Par. [0019] discloses the NVM device 170 is included in one of a solid-state drive (SSD) configured to communicate using NVMe.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Dierkhising’s teachings with Yun-Tien’s techniques for the benefit of the use of a NVM device may be associated with an instruction file that specifies one or more restrictions for accessing data stored in the NVM device (Dierkhising – Par. [0012]).
Yun-Tien and Dierkhising fail to explicitly disclose wherein the connection state indicates that an operation of a first mode corresponding to the first mode integrating circuit fails, or an operation of a second mode corresponding to the second mode integrating circuit fails.
Natarajan discloses wherein the connection state indicates that an operation of a first mode corresponding to the first mode integrating circuit fails, or an operation of a second mode corresponding to the second mode integrating circuit fails (Natarajan – Par. [0028] discloses the When a USB 2 device is connected to a connector of the USB interface that supports USB 3 (e.g., in the example of FIG. 1, connector 110-3 or connector 110-4), the USB 3 port (e.g., in the example of FIG. 1, Port 5 or Port 6 of ports 120) begins the negotiation of the data transfer protocol and triggers the LTSSM Rx.Detect circuit and controller. Because the device is a USB 2 device, the LTSSM Rx.Detect of the USB 3 port will fail.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Natarajan’s teachings with Yun-Tien and Dierkhising’s techniques for the benefit of the use of Universal Serial Bus (USB) systems, and in particular, to power savings in USB systems that may support multiple modes of operation and data transfer rates according to different generations and versions of the USB standards (Natarajan – Par. [0001]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571) 270-7754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Dayton Lewis-Taylor/
Examiner, Art Unit 2181
/Farley Abad/Primary Examiner, Art Unit 2181