DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 02/17/2026. Claims 1-21 and 24-26 are pending. Claims 1, 2, 8, and 25-26 are amended. Claims 22-23 are canceled.
Response to Arguments
On pages 12-13 of the Remarks, Applicant argues, with respect to the 112(f) claim interpretation, that sufficient structure is included in the claims. Upon further consideration, claim 25 has been determined to not invoke 112(f) and the previous 112(a)/(b) rejections corresponding to the previous 112(f) interpretation have been withdrawn accordingly.
Applicant's arguments filed 02/17/2026 have been fully considered but they are not persuasive.
On page 11 of the Remarks, Applicant argues, with respect to the drawing objection regarding showing a PON count in addition to a PON, that “As is obvious to one of ordinary skill in the art, the value of the "Positive or Negative value (PON)" can be called its count, referring to the fact that the PON value is being incremented or decremented per disclosed techniques.”
However, this argument is not persuasive because the claims distinctly recite a PON and a PON count. The drawings should show both or the claims should be clarified to show that they are the same.
On pages 13-14 of the Remarks, Applicant argues “It should be noted that the act of revising, of necessity, requires at starting point from which to revise. The starting point in this case is the initial stride. The revising process includes the initial stride as the starting point and then modifies it. The term "include" makes perfect sense in its plain English usage, and it certainly makes the cited claim limitation to be distinctly claimed for a person having ordinary skill in the art.”
However, this argument is not persuasive because the claim does not say that the revising includes starting at the initial stride, which would make grammatical sense. Instead, the claim still recites “wherein the revising includes an initial stride”, which does not make grammatical sense, because revising is a verb and an initial stride is a noun. It does not make grammatical sense to say that a verb includes a noun. Similar arguments are presented on page 15, which are not persuasive for the same reasons.
On page 14 of the Remarks, Applicant argues “It should be noted that the act of updating, of necessity, requires at starting point from which to update. The starting point in this case is the revised stride mentioned above. The updating process includes the revised stride as its starting point and then modifies it. The term "include" makes perfect sense in its plain English usage, and it certainly makes the cited claim limitation to be distinctly claimed for a person having ordinary skill in the art.”
However, this argument is not persuasive because the claim does not say that the updating includes updating a starting point, would make grammatical sense. Instead, the claim still recites “wherein the updating includes a second stride”, which does not make grammatical sense, because updating is a verb and a second stride is a noun. It does not make grammatical sense to say that a verb includes a noun. Similar arguments are presented on page 16, which are not persuasive for the same reasons.
On page 14 of the Remarks, Applicant argues that “It must be noted that claim 5 is dependent on claim 4, which is dependent on claim 3, which is dependent on claim 1. It must also be noted that the claimed method involves steps of "revising" and "updating." Revising and updating necessarily involve at least the possibility of values changing. Thus, it is perfectly legitimate, understandable, and definite that a value in a table that is compared in a first step can be different from a value in the table in a subsequent step, and therefore, be above a threshold at one point and below the threshold at a second point.”
However, this argument is not persuasive because the claim does not describe the saturation count being revised or updated from being above the first threshold to being below it.
On page 15 of the Remarks, Applicant argues “It must also be noted that the claimed method involves steps of "revising" and "updating." Revising and updating necessarily involve at least the possibility of values changing. Thus, it is perfectly legitimate, understandable, and definite that a value in a table that is compared in a first step can be different from a value in the table in a subsequent step, and therefore, be above a threshold at one point and below the threshold at a second point.”
However, this argument is not persuasive because the claim does not describe the saturation count being revised or updated from being above the first threshold to being below it.
On page 17 of the Remarks, Applicant argues, with respect to Luttrell, that “Clearly, a match count is not the same as a Positive or Negative value, and it is certainly not a Positive or Negative value that is assigned a neutral value.”
However, this argument is not persuasive because the match count of Luttrell is relied on to teach the claimed saturation count, not the PON count.
On page 18 of the Remarks, Applicant further argues, with respect to Luttrell, that “In fact, at no time does the cited Luttrell art describe "initializing an entry of the prefetch table with information pertaining to the first load instruction, wherein the information includes a last address, a maximum address, a minimum address, a Positive or Negative value (PON), a stride, and a saturation count, and wherein the PON is assigned a neutral value" and certainly doesn't describe "prefetching data from the last address plus an offset, wherein a polarity of the offset is based on the PON, and wherein the saturation count is above a first threshold"”
However, this argument is not persuasive because one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Luttrell is relied on in combination with Sander and Hooker to teach this claim 1 limitation.
On page 18 of the Remarks, Applicant argues, with respect to Sander, that “In fact, at no time does the cited Sander art describe "initializing an entry of the prefetch table with information pertaining to the first load instruction, wherein the information includes a last address, a maximum address, a minimum address, a Positive or Negative value (PON), a stride, and a saturation count, and wherein the PON is assigned a neutral value" and certainly doesn't describe "prefetching data from the last address plus an offset, wherein a polarity of the offset is based on the PON, and wherein the saturation count is above a first threshold" (Amended independent claim 1).”
However, this argument is not persuasive because one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Luttrell is relied on in combination with Sander and Hooker to teach this claim 1 limitation.
On page 19 of the Remarks, Applicant argues, with respect to Hooker, that “It must be noted that a counter is different from a Positive or Negative value (PON). The PON is not a pointer, nor does it count anything, such as a change to a minimum, a change to a maximum, a total, or a match. But rather, "when a new maximum address is seen, the PON value is incremented" and "when a new minimum address is seen, the PON value is decremented" (Specification as filed, paragraph [0041]). Nothing is counted, per se, but a difference between a last address and a current address is considered. No control logic "clears to zero" the PON.”
However, this argument is not persuasive because the broadest reasonable interpretation of a Positive of Negative value would include any value that is positive or negative, which would include the min change counter and the max change counter of Hooker which the office action maps as the claimed PON value. Examiner notes that the argument that the cited disclosure of incrementing the PON value when a new maximum address is seen effectively counts the number of times a new maximum address is seen, which indicative of the PON value being a counter value.
On page 19 of the Remarks, Applicant argues that “Furthermore, the PON is assigned a neutral value during initialization. A neutral value is not a zero value, and it can require simpler tracking logic than a counter that starts at zero and goes positive or negative.”
However, this argument is not persuasive because the broadest reasonable interpretation of a neutral value would include zero.
On page 19 of the Remarks, Applicant argues “Thus, at no time does the cited Sander art describe "initializing an entry of the prefetch table with information pertaining to the first load instruction, wherein the information includes a last address, a maximum address, a minimum address, a Positive or Negative value (PON), a stride, and a saturation count, and wherein the PON is assigned a neutral value" and certainly doesn't describe "prefetching data from the last address plus an offset, wherein a polarity of the offset is based on the PON, and wherein the saturation count is above a first threshold"”
However, this argument is not persuasive because one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Luttrell is relied on in combination with Sander and Hooker to teach this claim 1 limitation.
On page 20 of the Remarks, Applicant argues “In fact, at no time does Hayenga describe where "the second stride is not an integer multiple of the initial stride" (Dependent claim 18)”.
However, this argument is not persuasive because the office action does not rely on Hayenga for teaching claim 18. The office action relies on the combination of Luttrell, Sander, and Hooker to teach claim 18.
On page 20 of the Remarks, Applicant argues “In fact, at no time does Hayenga describe […] "resetting the information within the entry of the prefetch table, wherein the resetting includes zeroing the maximum address, the minimum address, the saturation count, and the stride, and wherein the resetting sets the PON to a neutral value" (Dependent claim 19, which depends on claim 18). And, the cited Hayenga art at no time describes "initializing an entry of the prefetch table with information pertaining to the first load instruction, wherein the information includes a last address, a maximum address, a minimum address, a Positive or Negative value (PON), a stride, and a saturation count, and wherein the PON is assigned a neutral value" and certainly doesn't describe "prefetching data from the last address plus an offset, wherein a polarity of the offset is based on the PON, and wherein the saturation count is above a first threshold"”
However, this argument is not persuasive because one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The combination of Luttrell, Sander and Hooker is relied on to teach to teach the limitations of claim 1, and the combination of Luttrell, Sander, Hooker, and Hayenga is relied on to teach the limitations of claim 19. Applicant’s argument does not consider how Luttrell, Sander, Hooker, and Hayenga are combined in the rejection to teach claim 19.
On pages 20-21 of the Remarks, Applicant argues “there is no motivation to combine a tracker with a generic counter used for a different logic function in a different logic block.”
However, this argument is not persuasive because it does not consider that the motivation for modifying the min and max change counters to be 3-bit counters (offered in the rejection of claim 24) is that it would allow for counting up to 8 changes to the min or max address, which may allow for detecting larger patterns.
On page 21 of the Remarks, Applicant argues “Furthermore, at no time does the cited Luick art describe "initializing an entry of the prefetch table with information pertaining to the first load instruction, wherein the information includes a last address, a maximum address, a minimum address, a Positive or Negative value (PON), a stride, and a saturation count, and wherein the PON is assigned a neutral value" and certainly doesn't describe "prefetching data from the last address plus an offset, wherein a polarity of the offset is based on the PON, and wherein the saturation count is above a first threshold"”
However, this argument is not persuasive because one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Luttrell is relied on in combination with Sander and Hooker to teach this claim 1 limitation.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s):
a PON count, as described in claims 15, 17, and 24, that is stored in an entry in the prefetch table in addition to the PON that claim 1 describes. While the drawings show the prefetch table storing a PON count value (Fig. 5) and the prefetch table storing a PON (Fig. 6), the drawings do not show the prefetch table storing a PON and a PON count.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-21 and 24-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “wherein the revising includes an initial stride” in line 14. It is unclear how the verb “revising” can “include” the noun “an initial stride”. For purposes of examination, this limitation will be interpreted as the revising being based on an initial stride.
Claim 1 recites “wherein the updating includes a second stride” in line 18. It is unclear how the verb “updating” can “include” the noun “a second stride”. For purposes of examination, this limitation will be interpreted as the updating being based on a second stride.
Claim 5 recites “incrementing…wherein the saturation count is less than the first threshold”, however, the last line of claim 1 recites “wherein the saturation count is above a first threshold”. It is unclear how the saturation count can be both above and less than the first threshold. For purposes of examination, these limitations will be interpreted as contingent limitations, i.e., the incrementing is interpreted as being contingent on the saturation count being less than the first threshold, and the prefetching of claim 1 will be interpreted as being contingent on the saturation count being above the first threshold.
Claim 13 recites “if the saturation count is below the first threshold”, however, the last line of claim 1 recites “wherein the saturation count is above a first threshold”. It is unclear how the saturation count can be both above and below the first threshold. For purposes of examination, the claim 1 limitation will be interpreted as a contingent limitation, i.e., the prefetching is contingent on the saturation count being above a first threshold.
Claim 25 recites “wherein the revising includes an initial stride” in line 16. It is unclear how the verb “revising” can “include” the noun “an initial stride”. For purposes of examination, this limitation will be interpreted as the revising being based on an initial stride.
Claim 25 recites “wherein the updating includes a second stride” in line 20. It is unclear how the verb “updating” can “include” the noun “a second stride”. For purposes of examination, this limitation will be interpreted as the updating being based on a second stride.
Claim 26 recites “wherein the revising includes an initial stride” in line 18. It is unclear how the verb “revising” can “include” the noun “an initial stride”. For purposes of examination, this limitation will be interpreted as the revising being based on an initial stride.
Claim 26 recites “wherein the updating includes a second stride” in line 22. It is unclear how the verb “updating” can “include” the noun “a second stride”. For purposes of examination, this limitation will be interpreted as the updating being based on a second stride.
Claims dependent on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10-18, 20, 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Luttrell US 2010/0268893 in view of Sander US 6,571,318 and Hooker US 2011/0238922.
Regarding claim 1, Luttrell teaches:
1. A processor-implemented method for data prefetching comprising:
accessing a processor core (Fig. 2, core 100), wherein the processor core executes instructions out of order (OOO) ([0035]: the core executes instructions out of order), wherein the processor core includes a local cache hierarchy (data cache 250 and L2 cache 105/L3 cache 120 are a local cache hierarchy), prefetch logic (Fig. 3 PLT control 302), and a prefetch table (Fig. 3 Prefetch Learning Table (PLT) 304), and wherein the processor core is coupled to an external memory system (Fig. 1, system memory);
detecting a data stream ([0063]: the decode unit detects instructions, i.e., a data stream), wherein the data stream includes at least a first load instruction with a first data address, a second load instruction with a second data address, and a third load instruction with a third data address ([0091] and [0119] describes confirming a prefetch stream for which at least three loads/demand accesses (with respective data addresses, see [0024]) have been detected, where the first load initializes an entry in the PLT, the second load is used to calculate the stride, and the third load is used to compare the stride), wherein the first load instruction causes a data miss in the local cache hierarchy ([0086] describes that the data address may miss in the data cache 250, this miss corresponds to the first load for which an entry in the PLT would be allocated/initialized at blocks 342/344 of Fig. 6), and wherein index a same entry in the prefetch table ([0115] describes writing a tag in an allocated entry and Fig. 6 shows calculating a stride at step 346 and comparing a stride at step 352 if there is a tag match at 340; this indicates that the first load that allocates/initializes the entry at step 342, the second load that calculates the stride at step 346, and the third load that compares the stride at step 352 index a same entry in the PLT);
initializing an entry of the prefetch table with information pertaining to the first load instruction, wherein the information includes a last address, a stride, and a saturation count ([0115] describes allocating the entry at step 342 and writing the last miss address and setting the stride field to zero at step 344, which initializes the entry with information pertaining to the first load including a last address and a stride; further, [0118] describes that the PLT includes a match count field (which is a saturation count in the sense that it would saturate at its highest value) which counts the matches to the stride, which is zero when the entry is allocated);
revising the information in the entry of the prefetch table, wherein the revising is based on the second load instruction, wherein the revising includes an initial stride, wherein the initial stride comprises an absolute value of a difference between the last address and the second data address (Fig. 6 and [0117]: the second load that is used to compute the stride at step 346 (i.e., an initial stride comprising the absolute value of the difference between the last address and the miss address/second data address) and writing the stride to the stride field at step 350 revises the information in the entry with the initial stride);
updating the information in the entry of the prefetch table, wherein the updating is based on the third load instruction, wherein the updating includes a second stride, wherein the second stride comprises an absolute value of a difference between the last address and the third data address (Fig. 6 and [0117]: the third load that is used to compare the currently calculated stride (i.e., a second stride comprising an absolute value of a different between the last address and the miss address/third data address) with the stride in the PLT will update the information in the entry of the PLT when they are equal (step 352 “Yes” and step 354) by invalidating it or by recording an indication in the entry that the stream has been confirmed (see [0092]));
discovering an underlying stride of the data stream, wherein the discovering is based on the updating (by recording that the stream has been confirmed, see [0092], the stride of the entry is discovered/learned as an underlying stride of the data stream); and
prefetching data from the last address plus an offset ([0097] describes setting the P Ptr to the miss address that confirmed the stream plus the stride (i.e., the last address plus an offset) and [0123] describes prefetching from the address stored as the P Ptr), and wherein the saturation count is above a first threshold ([0118] describes comparing the match count (i.e., the saturation count) to a desired count to confirm a prefetch stream, which indicates that the prefetch stream is confirmed when the match count reaches the desired count (i.e., when it is above a first threshold)).
Luttrell does not teach:
wherein the first data address, the second data address, and the third data address index a same entry in the prefetch table (although Luttrell [0087] implies there may be another embodiment in which the data address is used to index the PLT);
the information including a maximum address, a minimum address, a Positive or Negative value (PON), and wherein the PON is assigned a neutral value;
wherein a polarity of the offset is based on the PON.
However, Sander teaches data addresses indexing entries in a prefetch table (col 10 lines 48-59: the miss address/load data address is compared to the stride detect table/prefetch table to determine if it matches any of the record patterns (i.e., to index the table)).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the PLT of Luttrell to be indexed by data addresses as taught by Sander such that the combination would teach the first, second, and third data addresses indexing a same entry in the PLT. One of ordinary skill in the art would have been motivated to make this modification to ensure that the entries in the PLT correspond to the same data address (as opposed to indexing by the load PC, which only ensures that the entry correspondence to the load PC).
The combination of Luttrell and Sander does not teach:
the information including a maximum address, a minimum address, a Positive or Negative value (PON), and wherein the PON is assigned a neutral value;
wherein a polarity of the offset is based on the PON.
However, Hooker teaches:
a prefetch unit that includes information pertaining to a load including a maximum address, a minimum address, a Positive or Negative value (PON) ([0039]: the prefetch unit includes a min pointer register (i.e., a minimum address), a max pointer register (i.e., a maximum address) that points to the lowest and highest cache line index, respectively, that has been accessed since the prefetch unit began tracking accesses, and the prefetch unit also include a min change counter and a max change counter (i.e., a positive or negative value PON) that counts the number of changes to the min pointer and the max pointer, respectively), and wherein the PON is assigned a neutral value ([0048] describes clearing the max/min change counts (i.e., the PON) to zero, which is a neutral value);
wherein a polarity is based on the PON (the direction register indicates a direction/polarity based on the min change counter and max change counter (i.e., based on the PON), see [0051] and [0053]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the prefetch learning table of Luttrell to include the min pointer, max point, min change count, max change count, and direct taught by Hooker such that the combination would initialize an entry in the PLT with information include a maximum address, a minimum address, and a PON, and the offset/stride of the combination would have a polarity/direction based on the PON. One of ordinary skill in the art would have been motivated to make this modification to determine whether a pattern of accesses is trending upward, downward, or neither, which would improve the prefetcher’s ability to detect general access patterns and increase the likelihood that it prefetches effectively (Hooker [0005]-[0007] and [0034]-[0035]).
Regarding claim 2, Luttrell in view of Sander and Hooker teaches:
2. The method of claim 1 wherein the initializing further comprises assigning the last address, the maximum address, and the minimum address to the first data address (Luttrell [0117] describes writing the miss address (i.e., the first data address) to the last miss address field of the entry, this assigns the last address to the first data address; in the combination, the write address would also be written to the maximum address and the minimum address since the miss address is also the maximum address and minimum address when the entry is first allocated/initialized), and assigning the saturation count and the stride to 0 (Luttrell [0115]: the stride is set to zero at step 344; further, since the match count (i.e., the saturation count) counts the number of matches to the stride, see Luttrell [0118], the match count would also be 0 since there are no matches to the stride when the entry is first allocated/initialized).
Regarding claim 3, Luttrell in view of Sander and Hooker teaches:
3. The method of claim 1 wherein the revising further comprises replacing the last address with the second data address (Luttrell [0117]: step 350 updates/replaces the last address in the last miss address field with the second data address/miss address of the second load (the load that is used to calculate the stride at step 346 when the PLT stride is equal to 0 at step 348)).
Regarding claim 4, Luttrell in view of Sander and Hooker teaches:
4. The method of claim 3 further comprising replacing, in the entry of the prefetch table, the stride with the initial stride (Luttrell Fig. 6 and [0117]: the initial stride of the second load (the load that is used to calculate the stride at step 346 when the PLT stride is equal to 0 at step 348) replaces the stride in the PLT entry at step 350 when it is written to the entry).
Regarding claim 5, Luttrell in view of Sander and Hooker teaches:
5. The method of claim 4 further comprising incrementing the saturation count, wherein the saturation count is less than the first threshold (Luttrell [0118] describes that the match count (i.e., the saturation count) counts matches and compares the match count to a desired count, which indicates that the match count increments when it is less than the desired count).
Regarding claim 6, Luttrell in view of Sander and Hooker teaches:
6. The method of claim 5 further comprising replacing, in the entry of the prefetch table, the maximum address with the second data address, if the second data address is greater than the maximum address (Hooker [0057]-[0058]: if the current index is greater than the max pointer, then the max pointer is updated with the index; in the combination, the maximum address in the PLT entry will be replaced by the second data address if the second data address is greater).
Regarding claim 10, Luttrell in view of Sander and Hooker teaches:
10. The method of claim 1 wherein the updating further comprises evaluating the second stride (Luttrell Fig. 6: the updating of the entry at step 354 (either invalidating the entry or updating the entry as confirmed, see [0092]), includes evaluating the second stride at step 352).
Regarding claim 11, Luttrell in view of Sander and Hooker teaches:
11. The method of claim 10 wherein the second stride is greater or equal to the initial stride (Luttrell Fig. 6: the second stride may be determined to be equal to the initial stride at step 352).
Regarding claim 12, Luttrell in view of Sander and Hooker teaches:
12. The method of claim 11 wherein the second stride is an integer multiple of the initial stride (Luttrell Fig. 6 and [0117]: describes that the stride (i.e., the second stride) may be equal to the PLT stride (i.e., the initial stride) at step 352, in which case the second stride would be an integer multiple of 1 of the initial stride).
Regarding claim 13, Luttrell in view of Sander and Hooker teaches:
13. The method of claim 12 wherein the updating further comprises incrementing the saturation count if the saturation count is below the first threshold (Luttrell [0118] describes counting the matches (i.e., incrementing the match/saturation count) and comparing the match count to a desired count to confirm a prefetch stream, this indicates that the updating to confirm a stream (Fig. 6 step 354 and [0092]) includes incrementing the match count if the count is below the first threshold (below the desired count)).
Regarding claim 14, Luttrell in view of Sander and Hooker teaches:
14. The method of claim 13 further comprising replacing, in the entry of the prefetch table, the maximum address with the third data address, if the third data address is higher than the maximum address (Hooker [0057]-[0058]: if the current index is greater than the max pointer, then the max pointer is updated with the index; in the combination, the maximum address in the PLT entry will be replaced by the third data address if the third data address is greater).
Regarding claim 15, Luttrell in view of Sander and Hooker teaches:
15. The method of claim 14 further comprising incrementing, in the entry of the prefetch table, a PON count, if the PON count is below a second threshold (since this limitation is contingent on the PON count being below a second threshold, it is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04 (II)).
Regarding claim 16, Luttrell in view of Sander and Hooker teaches:
16. The method of claim 13 further comprising replacing, in the entry of the prefetch table, the minimum address with the third data address, if the third data address is lower than the minimum address (Hooker [0059]-[0060]: if the current index is less than the min pointer, then the min pointer is updated with the index; in the combination, the minimum address in the PLT entry will be replaced by the third data address if the third data address is less).
Regarding claim 17, Luttrell in view of Sander and Hooker teaches:
17. The method of claim 16 further comprising decrementing, in the entry of the prefetch table, a PON count, if the PON count is above a third threshold (since this limitation is contingent on the PON count being above a third threshold, it is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04 (II)).
Regarding claim 18, Luttrell in view of Sander and Hooker teaches:
18. The method of claim 11 wherein the second stride is not an integer multiple of the initial stride (Luttrell Fig. 6 and [0117]: describes that the stride (i.e., the second stride) may not be equal to the PLT stride (i.e., the initial stride) at step 352, in which case the second stride would not be an integer multiple of 1 of the initial stride).
Regarding claim 20, Luttrell in view of Sander and Hooker teaches:
20. The method of claim 10 wherein the second stride is less than the initial stride (Luttrell Fig. 6 and [0117]: describes that the stride (i.e., the second stride) may not be equal to the PLT stride (i.e., the initial stride) at step 352, which would include instances in which the second stride is less than the initial stride).
Regarding claim 25, Luttrell teaches:
25. A computer program product embodied in a non-transitory computer readable medium for instruction execution, the computer program product comprising code which causes one or more processors to generate semiconductor logic (Fig. 1, processor 10, processors inherently generate logic to perform functions according code stored in memory) for:
accessing a processor core (Fig. 2, core 100), wherein the processor core executes instructions out of order (OOO) ([0035]: the core executes instructions out of order), wherein the processor core includes a local cache hierarchy (data cache 250 and L2 cache 105/L3 cache 120 are a local cache hierarchy), prefetch logic (Fig. 3 PLT control 302), and a prefetch table (Fig. 3 Prefetch Learning Table (PLT) 304), and wherein the processor core is coupled to an external memory system (Fig. 1, system memory);
detecting a data stream ([0063]: the decode unit detects instructions, i.e., a data stream), wherein the data stream includes at least a first load instruction with a first data address, a second load instruction with a second data address, and a third load instruction with a third data address ([0091] and [0119] describes confirming a prefetch stream for which at least three loads/demand accesses (with respective data addresses, see [0024]) have been detected, where the first load initializes an entry in the PLT, the second load is used to calculate the stride, and the third load is used to compare the stride), wherein the first load instruction causes a data miss in the local cache hierarchy ([0086] describes that the data address may miss in the data cache 250, this miss corresponds to the first load for which an entry in the PLT would be allocated/initialized at blocks 342/344 of Fig. 6), and wherein index a same entry in the prefetch table ([0115] describes writing a tag in an allocated entry and Fig. 6 shows calculating a stride at step 346 and comparing a stride at step 352 if there is a tag match at 340; this indicates that the first load that allocates/initializes the entry at step 342, the second load that calculates the stride at step 346, and the third load that compares the stride at step 352 index a same entry in the PLT);
initializing an entry of the prefetch table with information pertaining to the first load instruction, wherein the information includes a last address, a stride, and a saturation count ([0115] describes allocating the entry at step 342 and writing the last miss address and setting the stride field to zero at step 344, which initializes the entry with information pertaining to the first load including a last address and a stride; further, [0118] describes that the PLT includes a match count field (which is a saturation count in the sense that it would saturate at its highest value) which counts the matches to the stride, which is zero when the entry is allocated);
revising the information in the entry of the prefetch table, wherein the revising is based on the second load instruction, wherein the revising includes an initial stride, wherein the initial stride comprises an absolute value of a difference between the last address and the second data address (Fig. 6 and [0117]: the second load that is used to compute the stride at step 346 (i.e., an initial stride comprising the absolute value of the difference between the last address and the miss address/second data address) and writing the stride to the stride field at step 350 revises the information in the entry with the initial stride);
updating the information in the entry of the prefetch table, wherein the updating is based on the third load instruction, wherein the updating includes a second stride, wherein the second stride comprises an absolute value of a difference between the last address and the third data address (Fig. 6 and [0117]: the third load that is used to compare the currently calculated stride (i.e., a second stride comprising an absolute value of a different between the last address and the miss address/third data address) with the stride in the PLT will update the information in the entry of the PLT when they are equal (step 352 “Yes” and step 354) by invalidating it or by recording an indication in the entry that the stream has been confirmed (see [0092]));
discovering an underlying stride of the data stream, wherein the discovering is based on the updating (by recording that the stream has been confirmed, see [0092], the stride of the entry is discovered/learned as an underlying stride of the data stream); and
prefetching data from the last address plus an offset ([0097] describes setting the P Ptr to the miss address that confirmed the stream plus the stride (i.e., the last address plus an offset) and [0123] describes prefetching from the address stored as the P Ptr), and wherein the saturation count is above a first threshold ([0118] describes comparing the match count (i.e., the saturation count) to a desired count to confirm a prefetch stream, which indicates that the prefetch stream is confirmed when the match count reaches the desired count (i.e., when it is above a first threshold)).
Luttrell does not teach:
wherein the first data address, the second data address, and the third data address index a same entry in the prefetch table (although Luttrell [0087] implies there may be another embodiment in which the data address is used to index the PLT);
the information including a maximum address, a minimum address, a Positive or Negative value (PON), and wherein the PON is assigned a neutral value;
wherein a polarity of the offset is based on the PON.
However, Sander teaches data addresses indexing entries in a prefetch table (col 10 lines 48-59: the miss address/load data address is compared to the stride detect table/prefetch table to determine if it matches any of the record patterns (i.e., to index the table)).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the PLT of Luttrell to be indexed by data addresses as taught by Sander such that the combination would teach the first, second, and third data addresses indexing a same entry in the PLT. One of ordinary skill in the art would have been motivated to make this modification to ensure that the entries in the PLT correspond to the same data address (as opposed to indexing by the load PC, which only ensures that the entry correspondence to the load PC).
The combination of Luttrell and Sander does not teach:
the information including a maximum address, a minimum address, a Positive or Negative value (PON), and wherein the PON is assigned a neutral value;
wherein a polarity of the offset is based on the PON.
However, Hooker teaches:
a prefetch unit that includes information pertaining to a load including a maximum address, a minimum address, a Positive or Negative value (PON) ([0039]: the prefetch unit includes a min pointer register (i.e., a minimum address), a max pointer register (i.e., a maximum address) that points to the lowest and highest cache line index, respectively, that has been accessed since the prefetch unit began tracking accesses, and the prefetch unit also include a min change counter and a max change counter (i.e., a positive or negative value PON) that counts the number of changes to the min pointer and the max pointer, respectively), and wherein the PON is assigned a neutral value ([0048] describes clearing the max/min change counts (i.e., the PON) to zero, which is a neutral value);
wherein a polarity is based on the PON (the direction register indicates a direction/polarity based on the min change counter and max change counter (i.e., based on the PON), see [0051] and [0053]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the prefetch learning table of Luttrell to include the min pointer, max point, min change count, max change count, and direct taught by Hooker such that the combination would initialize an entry in the PLT with information include a maximum address, a minimum address, and a PON, and the offset/stride of the combination would have a polarity/direction based on the PON. One of ordinary skill in the art would have been motivated to make this modification to determine whether a pattern of accesses is trending upward, downward, or neither, which would improve the prefetcher’s ability to detect general access patterns and increase the likelihood that it prefetches effectively (Hooker [0005]-[0007] and [0034]-[0035]).
Regarding claim 26, Luttrell teaches:
26. A computer system for instruction execution comprising:
a memory (a processor inherently executes instructions stored on a memory);
one or more processors coupled to the memory wherein the one or more processors are configured to:
access a processor core (Fig. 2, core 100), wherein the processor core executes instructions out of order (OOO) ([0035]: the core executes instructions out of order), wherein the processor core includes a local cache hierarchy (data cache 250 and L2 cache 105/L3 cache 120 are a local cache hierarchy), prefetch logic (Fig. 3 PLT control 302), and a prefetch table (Fig. 3 Prefetch Learning Table (PLT) 304), and wherein the processor core is coupled to an external memory system (Fig. 1, system memory);
detect a data stream ([0063]: the decode unit detects instructions, i.e., a data stream), wherein the data stream includes at least a first load instruction with a first data address, a second load instruction with a second data address, and a third load instruction with a third data address ([0091] and [0119] describes confirming a prefetch stream for which at least three loads/demand accesses (with respective data addresses, see [0024]) have been detected, where the first load initializes an entry in the PLT, the second load is used to calculate the stride, and the third load is used to compare the stride), wherein the first load instruction causes a data miss in the local cache hierarchy ([0086] describes that the data address may miss in the data cache 250, this miss corresponds to the first load for which an entry in the PLT would be allocated/initialized at blocks 342/344 of Fig. 6), and wherein index a same entry in the prefetch table ([0115] describes writing a tag in an allocated entry and Fig. 6 shows calculating a stride at step 346 and comparing a stride at step 352 if there is a tag match at 340; this indicates that the first load that allocates/initializes the entry at step 342, the second load that calculates the stride at step 346, and the third load that compares the stride at step 352 index a same entry in the PLT);
initialize an entry of the prefetch table with information pertaining to the first load instruction, wherein the information includes a last address, a stride, and a saturation count ([0115] describes allocating the entry at step 342 and writing the last miss address and setting the stride field to zero at step 344, which initializes the entry with information pertaining to the first load including a last address and a stride; further, [0118] describes that the PLT includes a match count field (which is a saturation count in the sense that it would saturate at its highest value) which counts the matches to the stride, which is zero when the entry is allocated);
revise the information in the entry of the prefetch table, wherein the revising is based on the second load instruction, wherein the revising includes an initial stride, wherein the initial stride comprises an absolute value of a difference between the last address and the second data address (Fig. 6 and [0117]: the second load that is used to compute the stride at step 346 (i.e., an initial stride comprising the absolute value of the difference between the last address and the miss address/second data address) and writing the stride to the stride field at step 350 revises the information in the entry with the initial stride);
update the information in the entry of the prefetch table, wherein the updating is based on the third load instruction, wherein the updating includes a second stride, wherein the second stride comprises an absolute value of a difference between the last address and the third data address (Fig. 6 and [0117]: the third load that is used to compare the currently calculated stride (i.e., a second stride comprising an absolute value of a different between the last address and the miss address/third data address) with the stride in the PLT will update the information in the entry of the PLT when they are equal (step 352 “Yes” and step 354) by invalidating it or by recording an indication in the entry that the stream has been confirmed (see [0092]));
discover an underlying stride of the data stream, wherein the discovering is based on the updating (by recording that the stream has been confirmed, see [0092], the stride of the entry is discovered/learned as an underlying stride of the data stream); and
prefetch data from the last address plus an offset ([0097] describes setting the P Ptr to the miss address that confirmed the stream plus the stride (i.e., the last address plus an offset) and [0123] describes prefetching from the address stored as the P Ptr), and wherein the saturation count is above a first threshold ([0118] describes comparing the match count (i.e., the saturation count) to a desired count to confirm a prefetch stream, which indicates that the prefetch stream is confirmed when the match count reaches the desired count (i.e., when it is above a first threshold)).
Luttrell does not teach:
wherein the first data address, the second data address, and the third data address index a same entry in the prefetch table (although Luttrell [0087] implies there may be another embodiment in which the data address is used to index the PLT);
the information including a maximum address, a minimum address, a Positive or Negative value (PON), and wherein the PON is assigned a neutral value;
wherein a polarity of the offset is based on the PON.
However, Sander teaches data addresses indexing entries in a prefetch table (col 10 lines 48-59: the miss address/load data address is compared to the stride detect table/prefetch table to determine if it matches any of the record patterns (i.e., to index the table)).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the PLT of Luttrell to be indexed by data addresses as taught by Sander such that the combination would teach the first, second, and third data addresses indexing a same entry in the PLT. One of ordinary skill in the art would have been motivated to make this modification to ensure that the entries in the PLT correspond to the same data address (as opposed to indexing by the load PC, which only ensures that the entry correspondence to the load PC).
The combination of Luttrell and Sander does not teach:
the information including a maximum address, a minimum address, a Positive or Negative value (PON), and wherein the PON is assigned a neutral value;
wherein a polarity of the offset is based on the PON.
However, Hooker teaches:
a prefetch unit that includes information pertaining to a load including a maximum address, a minimum address, a Positive or Negative value (PON) ([0039]: the prefetch unit includes a min pointer register (i.e., a minimum address), a max pointer register (i.e., a maximum address) that points to the lowest and highest cache line index, respectively, that has been accessed since the prefetch unit began tracking accesses, and the prefetch unit also include a min change counter and a max change counter (i.e., a positive or negative value PON) that counts the number of changes to the min pointer and the max pointer, respectively), and wherein the PON is assigned a neutral value ([0048] describes clearing the max/min change counts (i.e., the PON) to zero, which is a neutral value);
wherein a polarity is based on the PON (the direction register indicates a direction/polarity based on the min change counter and max change counter (i.e., based on the PON), see [0051] and [0053]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the prefetch learning table of Luttrell to include the min pointer, max point, min change count, max change count, and direct taught by Hooker such that the combination would initialize an entry in the PLT with information include a maximum address, a minimum address, and a PON, and the offset/stride of the combination would have a polarity/direction based on the PON. One of ordinary skill in the art would have been motivated to make this modification to determine whether a pattern of accesses is trending upward, downward, or neither, which would improve the prefetcher’s ability to detect general access patterns and increase the likelihood that it prefetches effectively (Hooker [0005]-[0007] and [0034]-[0035]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Luttrell US 2010/0268893 in view of Sander US 6,571,318, Hooker US 2011/0238922 and Hayenga US 2016/0019065.
Regarding claim 19, Luttrell in view of Sander and Hooker teaches:
19. The method of claim 18
Luttrell in view of Sander and Hooker does not teach:
resetting the information within the entry of the prefetch table, wherein the resetting includes zeroing the maximum address, the minimum address, the saturation count, and the stride, and wherein the resetting sets the PON to a neutral value.
However, Hayenga teaches clearing a training entry in a training table (analogous to the Prefetch Learning Table of Luttrell) so that the processor can start tracking accesses for a new page using the same entry, see [0019].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Luttrell in view of Sander and Hooker to clear the entry of the prefetch table as taught by Hayenga such that the combination would zero the maximum address, minimum address, saturation count, stride, and PON (which sets the PON to a neutral value). One of ordinary skill in the art would have been motivated to make this modification to more efficiently use entries in the PLT when the processor is expected to remain within the same region for a time (Hayenga [0019]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Luttrell US 2010/0268893 in view of Sander US 6,571,318, Hooker US 2011/0238922 and Luick US 2009/0006818.
Regarding claim 24, Luttrell in view of Sander and Hooker teaches:
24. The method of claim 1
Luttrell in view of Sander and Hooker does not explicitly teach:
wherein a PON count comprises a 3-bit counter.
However, Luick teaches a 3-bit counter, see [0078].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the min change counter and max change counter of Luttrell in view of Sander and Hooker to each be a 3-bit counter as taught by Luick such that the min or max change counter of the combination is a PON count that comprises a 3-bit counter. One of ordinary skill in the art would have been motivated to make this modification to count up to 8 changes to the min or max address, which would allow for higher counting for detecting larger patterns than implementations that use 1- or 2-bit counters.
Prior Art Considerations
While no prior art rejection is given for claims 7-9, and 21-23, these claims are currently rejected under 112(b) and are thus not allowable at the current point. The prior art considerations are the same as those given on pages 33-35 of the Non-Final Rejection dated 09/17/2025.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/KASIM ALLI/Examiner, Art Unit 2182
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183