DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to a claim of priority to Japanese application filed on July 11th, 2023. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) filed on July 10th, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election without traverse of Species A, shown in figures 1-6B, 22-23 directed to the first and fifth embodiments, with claims 1-2, and 7-19 being readable thereon in the reply filed on August 11th, 2026, is acknowledged.
The requirement is made FINAL, claims 1-2, and 7-19 are being examined on their merits and all non-elected claims (i.e. claims 3-6) are withdrawn from consideration at
this time.
Specification
The following guidelines illustrate the preferred layout for the specification of a utility application. These guidelines are suggested for the applicant’s use.
Arrangement of the Specification
As provided in 37 CFR 1.77(b), the specification of a utility application should include the following sections in order. Each of the lettered items should appear in upper case, without underlining or bold type, as a section heading. If no text follows the section heading, the phrase “Not Applicable” should follow the section heading:
(a) TITLE OF THE INVENTION.
(b) CROSS-REFERENCE TO RELATED APPLICATIONS.
(c) STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT.
(d) THE NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT.
(e) INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A READ-ONLY OPTICAL DISC, AS A TEXT FILE OR AN XML FILE VIA THE PATENT ELECTRONIC SYSTEM.
(f) STATEMENT REGARDING PRIOR DISCLOSURES BY THE INVENTOR OR A JOINT INVENTOR.
(g) BACKGROUND OF THE INVENTION.
(1) Field of the Invention.
(2) Description of Related Art including information disclosed under 37 CFR 1.97 and 1.98.
(h) BRIEF SUMMARY OF THE INVENTION.
(i) BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S).
(j) DETAILED DESCRIPTION OF THE INVENTION.
(k) CLAIM OR CLAIMS (commencing on a separate sheet).
(l) ABSTRACT OF THE DISCLOSURE (commencing on a separate sheet).
(m) SEQUENCE LISTING. (See MPEP § 2422.03 and 37 CFR 1.821 - 1.825). A “Sequence Listing” is required on paper if the application discloses a nucleotide or amino acid sequence as defined in 37 CFR 1.821(a) and if the required “Sequence Listing” is not submitted as an electronic document either on read-only optical disc or as a text file via the patent electronic system.
Content of Specification
(a) TITLE OF THE INVENTION: See 37 CFR 1.72(a) and MPEP § 606. The title of the invention should be placed at the top of the first page of the specification unless the title is provided in an application data sheet. The title of the invention should be brief but technically accurate and descriptive, preferably from two to seven words. It may not contain more than 500 characters.
(b) CROSS-REFERENCES TO RELATED APPLICATIONS: See 37 CFR 1.78 and MPEP § 211 et seq.
(c) STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT: See MPEP § 310.
(d) THE NAMES OF THE PARTIES TO A JOINT RESEARCH AGREEMENT. See 37 CFR 1.71(g).
(e) INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A READ-ONLY OPTICAL DISC, AS A TEXT FILE OR AN XML FILE VIA THE PATENT ELECTRONIC SYSTEM: The specification is required to include an incorporation-by-reference of electronic documents that are to become part of the permanent United States Patent and Trademark Office records in the file of a patent application. See 37 CFR 1.77(b)(5) and MPEP § 608.05. See also the Legal Framework for Patent Electronic System posted on the USPTO website (https://www.uspto.gov/sites/default/files/documents/2019LegalFrameworkPES.pdf) and MPEP § 502.05
(f) STATEMENT REGARDING PRIOR DISCLOSURES BY THE INVENTOR OR A JOINT INVENTOR. See 35 U.S.C. 102(b) and 37 CFR 1.77.
(g) BACKGROUND OF THE INVENTION: See MPEP § 608.01(c). The specification should set forth the Background of the Invention in two parts:
(1) Field of the Invention: A statement of the field of art to which the invention pertains. This statement may include a paraphrasing of the applicable U.S. patent classification definitions of the subject matter of the claimed invention. This item may also be titled “Technical Field.”
(2) Description of the Related Art including information disclosed under 37 CFR 1.97 and 37 CFR 1.98: A description of the related art known to the applicant and including, if applicable, references to specific related art and problems involved in the prior art which are solved by the applicant’s invention. This item may also be titled “Background Art.”
(h) BRIEF SUMMARY OF THE INVENTION: See MPEP § 608.01(d). A brief summary or general statement of the invention as set forth in 37 CFR 1.73. The summary is separate and distinct from the abstract and is directed toward the invention rather than the disclosure as a whole. The summary may point out the advantages of the invention or how it solves problems previously existent in the prior art (and preferably indicated in the Background of the Invention). In chemical cases it should point out in general terms the utility of the invention. If possible, the nature and gist of the invention or the inventive concept should be set forth. Objects of the invention should be treated briefly and only to the extent that they contribute to an understanding of the invention.
(i) BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S): See MPEP § 608.01(f). A reference to and brief description of the drawing(s) as set forth in 37 CFR 1.74.
(j) DETAILED DESCRIPTION OF THE INVENTION: See MPEP § 608.01(g). A description of the preferred embodiment(s) of the invention as required in 37 CFR 1.71. The description should be as short and specific as is necessary to describe the invention adequately and accurately. Where elements or groups of elements, compounds, and processes, which are conventional and generally widely known in the field of the invention described, and their exact nature or type is not necessary for an understanding and use of the invention by a person skilled in the art, they should not be described in detail. However, where particularly complicated subject matter is involved or where the elements, compounds, or processes may not be commonly or widely known in the field, the specification should refer to another patent or readily available publication which adequately describes the subject matter.
(k) CLAIM OR CLAIMS: See 37 CFR 1.75 and MPEP § 608.01(m). The claim or claims must commence on a separate sheet or electronic page (37 CFR 1.52(b)(3)). Where a claim sets forth a plurality of elements or steps, each element or step of the claim should be separated by a line indentation. There may be plural indentations to further segregate subcombinations or related steps. See 37 CFR 1.75 and MPEP 608.01(i) - (p).
(l) ABSTRACT OF THE DISCLOSURE: See 37 CFR 1.72 (b) and MPEP § 608.01(b). The abstract is a brief narrative of the disclosure as a whole, as concise as the disclosure permits, in a single paragraph preferably not exceeding 150 words, commencing on a separate sheet following the claims. In an international application which has entered the national stage (37 CFR 1.491(b)), the applicant need not submit an abstract commencing on a separate sheet if an abstract was published with the international application under PCT Article 21. The abstract that appears on the cover page of the pamphlet published by the International Bureau (IB) of the World Intellectual Property Organization (WIPO) is the abstract that will be used by the USPTO. See MPEP § 1893.03(e).
(m) SEQUENCE LISTING: See 37 CFR 1.821 - 1.825 and MPEP §§ 2421 - 2431. The requirement for a sequence listing applies to all sequences disclosed in a given application, whether the sequences are claimed or not. See MPEP § 2422.01.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 15 is objected to because of the following informalities:
Claim 15, lines 4-5, recite “a/the plurality of second via plugs”. This limitation lacks explicit antecedent basis in the preceding claims from which it depends but does not render the claim indefinite. The claim should be amended to recite “a/the plurality of first via plugs” or “a/the plurality of via plugs” instead of “a/the plurality of second via plugs”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7, and 18-19 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Osada et al. (US20230124986A1).
Regarding claim 1;
Osada et al. teaches a semiconductor device (e.g. Fig. 4 ref 5, Detailed description [0045] “The electronic component 5 is a transformer chip that boosts and outputs an electric signal that has been input.”) comprising: a semiconductor substrate (Fig. 4-9 ref 41); a first coil (e.g. Fig. 7 ref 21C, 23), a second coil (e.g. Fig. 7 ref 21B, 23), a third coil(e.g. Fig. 6 ref 21C, 22), and a fourth coil (e.g. Fig. 7 ref 21B, 22); an insulating layer (e.g. Fig. 4 ref 51); and a first shield (e.g. Fig 7-9 ref 86) wherein the semiconductor substrate has a device region (e.g. Fig. 5-7 ref 62) and a peripheral region (e.g. Fig. 5-7 ref 63), wherein the peripheral region is present around the device region in a plan view (e.g. see examiner markup below), wherein the first coil and the second coil are arranged on the device region and are arranged in a first direction in a plan view (e.g. see examiner markup below), wherein the third coil and the fourth coil are respectively opposed to the first coil and the second coil via the insulating layer (e.g. see examiner markup below), wherein the first shield is arranged between the semiconductor substrate and the first and second coils and overlaps with the first coil and the second coil in a plan view (e.g. see examiner markup below), wherein a width of the first shield in a second direction orthogonal to the first direction is larger than a width of the first coil in the second direction and a width of the second coil in the second direction (e.g. see examiner markup below), and wherein the first shield is electrically connected to a reference potential (e.g. Detailed description [0211] “ the high voltage dummy pattern 86 is preferably made equipotential to the high voltage coils 23. The voltage drops between the high voltage coils 23 and the high voltage dummy pattern 86 can thereby be suppressed reliably and therefore, the electric field concentration with respect to the high voltage coils 23 can be suppressed appropriately.”).
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Regarding claim 2;
Osada et al. further teaches that the first shield is continuously formed so as to span between the first coil and the second coil in a plan view (e.g. see examiner markup in claim 1 rejection).
Regarding claim 7;
Osada et al. teaches that the semiconductor device further comprises a second shield arranged between the first coil and the second coil in a plan view (e.g. Fig. 7 ref 85), wherein a width of the second shield in the second direction is larger than the width of the first coil in the second direction and the width of the second coil in the second direction, and wherein the second shield is electrically connected to the reference potential (e.g. the first shield 86 is in electrical and physical contact with the high voltage coil 23, the reference potential, and the second shield 85 is in electrical and physical contact with the first shield which is in contact with the reference potential, therefore the second shield is electrically connected to the reference potential).
Regarding claim 18;
Osada et al. teaches A semiconductor device (e.g. Fig. 4 ref 5, Detailed description [0045] “The electronic component 5 is a transformer chip that boosts and outputs an electric signal that has been input.”) comprising: a semiconductor substrate (Fig. 4-9 ref 41); a first coil (e.g. Fig. 7 ref 21C, 23), a second coil (e.g. Fig. 7 ref 21B, 23), a third coil(e.g. Fig. 6 ref 21C, 22), and a fourth coil (e.g. Fig. 7 ref 21B, 22), a fifth coil (e.g. Fig. 7 ref 21D, 23), a sixth coil (e.g. Fig. 7 ref 21A, 23), a seventh coil (e.g. Fig. 6 ref 21D, 22), and an eighth coil (e.g. Fig. 6 ref 21A, 22); an insulating layer (e.g. Fig. 4 ref 51); and a first shield (e.g. Fig 7-9 ref 86), wherein the semiconductor substrate has a device region (e.g. Fig. 5-7 ref 62) and a peripheral region (e.g. Fig. 5-7 ref 63), wherein the peripheral region is present around the device region in a plan view (e.g. see examiner markup in claim 1 rejection), wherein the first coil, the second coil, the fifth coil, and the sixth coil are arranged on the device region and are arranged in a first direction in a plan view (e.g. see examiner markup in claim 1 rejection), wherein the first coil and the second coil are adjacent to each other (e.g. see examiner markup in claim 1 rejection), wherein the fifth coil is adjacent to the first coil from an opposite side of the second coil, and is electrically connected in series to the first coil (e.g. see examiner markup in claim 1 rejection), wherein the sixth coil is adjacent to the second coil from an opposite side of the first coil, and is electrically connected in series to the second coil (e.g. see examiner markup in claim 1 rejection), wherein the third coil, the fourth coil, the seventh coil, and the eighth coil are respectively opposed to the first coil, the second coil, the fifth coil, and the sixth coil via the insulating layer (e.g. see examiner markup in claim 1 rejection), wherein the seventh coil is electrically connected in series to the third coil (e.g. see examiner markup in claim 1 rejection), wherein the eighth coil is electrically connected in series to the fourth coil (e.g. see examiner markup in claim 1 rejection), wherein the first shield is arranged between the semiconductor substrate and the first, second, fifth, and sixth coils, and overlaps with the first coil, the second coil, the fifth coil, and the sixth coil in a plan view (e.g. see examiner markup in claim 1 rejection), wherein a width of the first shield in a second direction orthogonal to the first direction is larger than a width of the first coil in the second direction, a width of the second coil in the second direction, a width of the fifth coil in the second direction, and a width of the sixth coil in the second direction (e.g. see examiner markup in claim 1 rejection), and wherein the first shield is electrically connected to a reference potential (e.g. Detailed description [0211] “ the high voltage dummy pattern 86 is preferably made equipotential to the high voltage coils 23. The voltage drops between the high voltage coils 23 and the high voltage dummy pattern 86 can thereby be suppressed reliably and therefore, the electric field concentration with respect to the high voltage coils 23 can be suppressed appropriately.”).
Regarding claim 19;
Osada et al. teaches that the semiconductor device further comprises a second shield arranged between the first coil and the second coil in a plan view (e.g. Fig. 7 ref 85), wherein a width of the second shield in the second direction is larger than the width of the first coil in the second direction, the width of the second coil in the second direction, the width of the fifth coil in the second direction, and the width of the sixth coil in the second direction (e.g. see examiner markup in claim 1 rejection), and wherein the second shield is electrically connected to the reference potential (e.g. the first shield 86 is in electrical and physical contact with the high voltage coil 23, the reference potential, and the second shield 85 is in electrical and physical contact with the first shield which is in contact with the reference potential, therefore the second shield is electrically connected to the reference potential).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 10 and 13 are rejected under 35 U.S.C. 103 103 as being unpatentable over Osada et al. (US20230124986A1) in view of Stecher et al. (US20130278372A1) for the following reasons:
Regarding claim 10;
Osada et al. is silent to the second shield having a plurality of first via plugs and a first wiring and a second wiring stacked via the plurality of first via plugs, and wherein an interval between two adjacent first via plugs of the plurality of first via plugs is 0.3 μm or more and 2 μm or less. as claimed.
However, Stecher et al. teaches a shield having a plurality of first via plugs and a first wiring and a second wiring stacked via the plurality of first via plugs (e.g. Fig. 1-2, ref 30,39; Detailed description [0029] “In order to further improve the shielding effect of the first ring 30, a number of optional, electrically conductive columns 39 are spaced distant from one another along the first ring 30.”).
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At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to substitute the second shield taught in Osada et al. for the shield structure taught in Stecher et al. since it would perform the predictable result of providing improved electrical isolation/shielding to the resulting device with a reasonable expectation of success (see MPEP 2143(I)(B)). Further, it would have been obvious to someone having ordinary skill in the art to form an interval between two adjacent first via plugs of the plurality of first via plugs to be in the range of 0.3 μm - 2 μm with routine experimentation and optimization since doing so would allow for the electrical isolation provided by the shielding to be tuned resulting in a device with an increased range of operability with a reasonable expectation of success. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 13;
Osada et al. is silent to a constituent material of the first shield is a conductive material containing aluminum or copper as a main component as claimed.
However, Stecher et al. teaches a shield ring made with any electrically conductive material (e.g. Detailed description [0031] “the second ring 70 may be made not only of metal like copper or aluminum but…In general, any electrically conductive material or combination of materials may be used for the second ring 70.”).
At the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the first shield taught in Osada et al. from Copper or Aluminum as taught in Stecher et al., since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Claims 8-9 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Osada et al. (US20230124986A1) for the following reasons:
Regarding claim 8;
Osada et al. is silent to the first shield being electrically connected to the second shield and being electrically connected to the reference potential via the second shield as claimed.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to connect the first shield and the second shield taught in Osada et al. electrically and connecting the reference potential to the second shield instead of the first shield, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. Further, the specification contains no disclosure of either the critical nature of the claimed arrangement or any unexpected results arising therefrom so it would be obvious that the rearrangement of parts would still provide the predictable result of reducing cross-talk between components in the resulting device.
Regarding claim 9;
Osada et al. further teaches the second shield is spaced apart from the first coil and the second coil in a plan view (e.g. see examiner markup in claim 1 rejection).
Osada et al. is silent to a distance between the first coil and the second shield and a distance between the second coil and the second shield are 12 μm or more and 100 μm or less in a plan view as claimed.
However, at the effective time of filing, it would have been obvious to someone having ordinary skill in the art to form a distance between the first coil and the second shield and a distance between the second coil and the second shield taught in Osada et al. to be within the range of 12 μm - 100 μm in a plan view with routine experimentation and optimization since such a modification would have involved a mere change in sizes of components. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04. See also In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990), In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 15;
Osada et al. teaches that the semiconductor device comprising a guard ring arranged on the peripheral region (e.g. Fig. 5-9 ref 61,64,65; Detailed description [0096] “the field electrode 61 includes a plurality of field plug electrodes 64 and a field plug electrode 65”), wherein the guard ring has a plurality of wirings and a plurality of second via plugs (e.g. see examiner markup below), wherein the wirings and the second via plugs are alternately stacked (e.g. see examiner markup below), wherein the plurality of wirings include a third wiring in a bottommost layer and a fourth wiring located in an upper layer of the third wiring, wherein the first shield is formed in the same layer as the third wiring.
Osada et al. is silent to the second shield being formed in the same layer as the third wiring, the fourth wiring, and the second via plug located between the third wiring and the fourth wiring as claimed.
However, Osada et al. teaches that the thickness of the second shield can be arbitrarily deep within the insulating layers according to the salient operating parameters (e.g. Detailed description [0191] “A depth position of the shield conductor layer 85 in an interior of the insulating laminated structure 51 is arbitrary and is adjusted in accordance with electric field strengths to be relaxed.”).
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to form the second shield taught in Osada et al. in the same layer as the third wiring, the fourth wiring, and the second via plug located between the third wiring and the fourth wiring with routine experimentation and optimization since doing so would allow the resulting device to be tuned to function in different operational regimes and suppress any undesired electric field strength with a reasonable expectation of success. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 14;
Osada et al. is silent to a lead wire formed in the same layer as the first shield and connected to the first shield as claimed.
However, Osada et al. implicitly teaches that the first shield is electrically connected to a reference potential (e.g. Detailed description [0211] “the high voltage dummy pattern 86 is preferably made equipotential to the high voltage coils 23. The voltage drops between the high voltage coils 23 and the high voltage dummy pattern 86 can thereby be suppressed reliably and therefore, the electric field concentration with respect to the high voltage coils 23 can be suppressed appropriately.”) where the reference potential and the first shield exist in the same layer with each other (e.g. see examiner markup below).
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to form a lead wire between the reference potential and the first shield taught in Osada et al. since doing so is within the finite number of ways to provide electrical contact between adjacent elements and would have provided the predictable result of a first shield electrically connected to a reference potential by a lead wire in the resulting device. (see MPEP 2143(I)(B),(E)).
Regarding claim 16;
Osada et al. further teaches that a distance between the first coil and the third coil or a distance between the second coil and the fourth coil is 6 μm or more and 14 μm or less (e.g. Fig. 8 ref D2, Detailed description [0186] “The distance D2 may be not less than 1 µm and not more than 50 µm. The distance D2 is preferably not less than 5 µm and not more than 25 µm.”).
Osada et al. is silent to a distance between the first coil and the third coil or a distance between the second coil and the fourth coil is 6 μm or more and 14 μm or less in a plan view as claimed.
However, at the effective time of filing it would have been obvious to one having ordinary skill in the art that the relative arrangement of the low and high voltage coils taught in figure 8 of Osada et al. represents a corresponding spatial configuration of the disclosed invention when viewed along the VIII direction of figures 6-7, resulting in the claimed relative arrangement. Implementing the low and high voltage coils in this corresponding arrangement would therefore have been a predictable application of the structure disclosed by Osada et al. with a reasonable expectation of success.
Regarding claim 17;
Osada et al. is silent to the first coil and the third coil are magnetically coupled to each other, and wherein the second coil and the fourth coil are magnetically coupled to each other as claimed.
However, Osada et al. implicitly teaches that the high voltage coils 23 form transformers with the low voltage coils 22 (e.g. see examiner below), which necessarily requires that the low voltage coils and high voltage coils are magnetically coupled to one another respectively because in order for a transformer element to be formed the inductive coils present must share a mutual inductance and that is only possible when magnetic coupling occurs therebetween.
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Thus, it is inherent that the low voltage coils and high voltage coils taught in Osada et al. are respectively magnetically coupled to one another.
Allowable Subject Matter
Claims 11-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
