Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims [ 1-20 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Park (Pub No. US 20100195402), hereinafter "Park", in view of Missiroli et al. (Pub No. US 20170140823), hereinafter "Missiroli"].
As per claim 1, Park significantly teaches a memory device, comprising (FIG. 2A is a block diagram of a nonvolatile memory device according to an embodiment of this disclosure. [Park PP 0037]):
a peripheral circuit (the nonvolatile memory device 200 includes a memory cell array 210 , a page buffer unit 220 [Park PP 0038])
that comprises a set of page buffers (The page buffer unit 220 includes a plurality of the page buffers. Each of the page buffers is coupled with one or more bit lines. [Park PP 0040]),
wherein the set of page buffers comprises N page buffers (The page buffer unit 220 includes a plurality of the page buffers. [Park PP 0040])
with N being an integer larger than 1 (an N number of latch units coupled in common to the second sense node, wherein N is a natural number greater than two. [Park PP 0024])
Park does not explicitly teach “an error bit signal generating circuit and a plurality of first transistors” and “the error bit signal generating circuit is connected with sensing nodes of the page buffers, and respective sensing nodes of every two adjacent page buffers in the set of page buffers are connected with one of the first transistors”
However, Missiroli, in an analogous art, teaches an error bit signal generating circuit (The page buffer circuit … comprises a sensing node SEN … and a sense latch configured to latch a voltage [Missiroli PP 0062-0069]) and a plurality of first transistors (a second switching circuit M2 arranged between the first node CSO and the sensing node SEN [Missiroli PP 0062-65]); the error bit signal generating circuit is connected with sensing nodes of the page buffers (A sensing node SEN … electrically coupled to switching circuits and a sense latch [Missiroli PP 0062-0069]), and respective sensing nodes of every two adjacent page buffers in the set of page buffers are connected with one of the first transistors (switching circuits arranged between the first node CSO and the sensing node SEN [Missiroli PP 0062-0065]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective
filing data of the claimed invention to have modified the page buffer circuit disclosed by Park to incorporate Missiroli’s teaching of page buffer sensing control, in order to improve sensing precision and overall read performance (capable of controlling sensing current more precisely and tightly. [Missiroli PP 0003], a sensing method and circuitry which ensures a reliable reading without increasing the latency time. [Missiroli PP 0031], allows performing more precise sensing with a tighter control of analog voltages. [Missiroli PP 0093]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Park’s invention.
As per claim 2, Park significantly teaches wherein the N page buffers in the set of page buffers are arranged in a first direction (The page buffer unit 220 includes a plurality of the page buffers. Each of the page buffers is coupled with one or more bit lines. [Park PP 0040]), the error bit signal generating circuit is connected with a sensing node of a first of the page buffers in the set of page buffers (The data conversion unit 224 includes a sensing component (for example, MN 2 and MN 3 ) and a transmission component (for example, MN 4 ). The sensing component is configured to sense a voltage level of the first sense node SO 1 and change a voltage level of a second sense node SO 2 accordingly. [Park PP 0046]), a distance between a first page buffer in the set of page buffers and the error bit signal generating circuit is smaller than a distance between any other page buffer in the set of page buffers and the error bit signal generating circuit (Referring to FIG. 2B, a page buffer 221 (i.e., one of the page buffers included in the page buffer unit 220 ) includes a first sensing unit 222 , a precharge unit 223 , a data conversion unit 224 , a first latch unit 225 , and a second latch unit 226 . [Park PP 0044]).
As per claim 3, Park significantly teaches generate a second voltage at the sensing node of the page buffer based on an information stored in the page buffer (a voltage level of the first sense node SO 1 is changed according to a voltage level of the node MQ, the data output control signal PBDO is changed into a low level voltage [Park PP 0075]); and
the error bit signal generating circuit is configured to, at the stage of error bit counting operation, receive the second voltage (The sensing component is configured to sense a voltage level of the first sense node SO 1 and change a voltage level of a second sense node SO 2 accordingly. [Park PP 0046]) and
generate a current signal based on the second voltage being smaller than the first voltage (The second and third NMOS transistors MN 2 , MN 3 are coupled in series between the second sense node SO 2 and a ground node. [Park PP 0052]).
Park does not explicitly teach “wherein the set of page buffers is configured to, at a stage of error bit counting operation, receive a first voltage at a sensing node of a page buffer to be counted”
However, Missiroli, in an analogous art, teaches wherein the set of page buffers is configured to, at a stage of error bit counting operation, receive a first voltage at a sensing node of a page buffer to be counted (the sensing node SEN is charged to the voltage of the second voltage source VDC_PB. [Missiroli PP 0070])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective
filing data of the claimed invention to have modified the page buffer circuit disclosed by Park to incorporate Missiroli’s teaching of page buffer sensing control, in order to improve sensing precision and overall read performance (capable of controlling sensing current more precisely and tightly. [Missiroli PP 0003], a sensing method and circuitry which ensures a reliable reading without increasing the latency time. [Missiroli PP 0031], allows performing more precise sensing with a tighter control of analog voltages. [Missiroli PP 0093]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Park’s invention.
As per claim 4, Park significantly teaches wherein at the stage of error bit counting operation, the first transistors between the page buffer to be counted and the error bit signal generating circuit are all in an on state (The latch selection circuit is configured to select a node of the latch circuit and couple the selected node with the second sense node SO 2 . [Park PP 0048], When the third data transmission signal MTRAN is in a high level voltage, the seventh NMOS transistor MN 7 is turned on so that the node MQ is coupled with the second sense node SO 2 [Park PP 0061]); and
at the stage of error bit counting operation, the first transistors between the page buffer to be counted and the Nth page buffer are all in an off state (the first, second, and fourth data transmission signals CTRAN, CTRAN_N, and MTRAN_N of a low level voltage are applied. [Park PP 0061).
As per claim 5, Park significantly teaches wherein at a stage of non-error bit counting operation, the plurality of first transistors are all in an off state (The latch selection circuit is configured to select a node of the latch circuit and couple the selected node with the second sense node SO 2. [Park PP 0048], When the third data transmission signal MTRAN is in a high level voltage, the seventh NMOS transistor MN 7 is turned on [Park PP 0061]).
As per claim 6, Park significantly teaches wherein the page buffer to be counted comprises a first latch (The first and second latch units 225 , 226 each include a latch circuit (for example, latch L 1 ) [Park PP 0048]), a second transistor and a third transistor (Each of the first and second latch units comprises a latch circuit coupled between first and second nodes, a first switching element coupled between the first node and the second sense node, and a second switching element coupled between the second node and the second sense node. [Park PP 0020]), a first terminal of the second transistor is connected to the sensing node (The fifth NMOS transistor MN 5 is coupled between the second sense node SO 2 and node CQ [Park PP 0054]), a second terminal of the second transistor is connected to a first terminal of the third transistor (The latch selection circuit is configured to select a node of the latch circuit and couple the selected node with the second sense node SO 2 . [Park PP 0048]) and a second terminal of the third transistor is connected to a second power source voltage (The first and second inverters IN 1 , IN 2 are coupled together to form a first latch L 1 [Park PP 0056]); and
the page buffer to be counted is configured to turn on the second transistor at the stage of error bit counting operation (When the third data transmission signal MTRAN is in a high level voltage, the seventh NMOS transistor MN 7 is turned on [Park PP 0061]), and receive an information stored in the first latch at a gate terminal of the third transistor (latch data in response to the operation of the data conversion unit 224 or transfer latched data. [Park PP 0047], after a voltage level of the first sense node SO 1 is changed according to a voltage level of the node MQ, the data output control signal PBDO is changed into a low level voltage, and the data input control signal PBDI is changed into a high level voltage. [Park PP 0075]).
As per claim 7, Park significantly teaches wherein the error bit signal generating circuit comprises a first branch and a second branch (The data conversion unit 224 includes a sensing component (for example, MN 2 and MN 3 ) and a transmission component [Park PP 0046]), wherein at the stage of error bit counting operation, the first branch is configured to receive the second voltage (The sensing component is configured to sense a voltage level of the first sense node SO 1 and change a voltage level of a second sense node SO 2 accordingly. [Park PP 0046]) and generate a first control signal at a first level (When the first sense node SO 1 has a high level voltage at the same time that the third NMOS transistor MN 3 is turned on [Park PP 0060]) for turning on the second branch based on the second voltage being smaller than the first voltage (Thus, the second sense node SO 2 is coupled with the ground node to thus obtain a low level voltage [Park PP 0061]); and
the second branch is configured to receive the first control signal at the first level (When the third data transmission signal MTRAN is in a high level voltage, the seventh NMOS transistor MN 7 is turned on so that the node MQ is coupled with the second sense node SO 2 . [Park PP 0061]) and generate the current signal (the second sense node SO 2 is coupled with the ground node [Park PP 0061]).
As per claim 8, Park significantly teaches wherein the first branch comprises a fourth transistor, a fifth transistor and a sixth transistor (The data conversion unit 224 includes second and third NMOS transistors MN 2 , MN 3 , constituting the sensing component, and a fourth NMOS transistor MN 4 [Park PP 0049] multiple transistors forming one sensing path), a first terminal of the fourth transistor is configured to receive a first power source voltage (The second and third NMOS transistors MN 2 , MN 3 are coupled in series between the second sense node SO 2 and a ground node. [Park PP 0052] transistor terminal tied to supply node), a second terminal of the fourth transistor is connected to a first terminal of the fifth transistor (The fourth NMOS transistor MN 4 is coupled between the first sense node SO 1 and the second sense node SO 2 [Park PP 0053] series connection between transistors), a second terminal of the fifth transistor and a first terminal of the sixth transistor are connected to a first node (The first and second latch units 225 , 226 are commonly coupled with the second sense node SO 2 [Park PP 0047]) and a second terminal of the sixth transistor is configured to receive a second power source voltage (the second sense node SO 2 is coupled with the ground node [Park PP 0061]); and
at the stage of error bit counting operation, the fifth transistor is in an on state (the second sense node SO 2 is coupled with the ground node [Park PP 0060]), a gate terminal of the fourth transistor and a gate terminal of the sixth transistor are configured to receive the second voltage (The gate of the second NMOS transistor MN 2 is coupled with the first sense node SO 1 [Park PP 0052]), and if the second voltage is smaller than the first voltage, the first control signal at the first level is generated at the first node (When the first sense node SO 1 has a high level voltage at the same time that the third NMOS transistor MN 3 is turned on, the second NMOS transistor MN 2 is also turned on … Thus, the second sense node SO 2 is coupled with the ground node to thus obtain a low level voltage. [Park PP 0060-0061]).
As per claim 9, Park significantly teaches wherein the second branch comprises a seventh transistor and an eighth transistor, a first terminal of the seventh transistor is connected to a first terminal of the eighth transistor and a second terminal of the eighth transistor is connected to the second power source voltage (The second and third NMOS transistors MN 2 , MN 3 are coupled in series between the second sense node SO 2 and a ground node. [Park PP 0052]); and
at the stage of error bit counting operation, the seventh transistor is in an on state (When the first sense node SO 1 has a high level voltage at the same time that the third NMOS transistor MN 3 is turned on, the second NMOS transistor MN 2 is also turned on. [Park PP 0060] transistor is on during sensing state), a gate terminal of the eighth transistor is configured to receive the first control signal (A data input control signal PBDI is inputted to the gate of the third NMOS transistor MN 3 . [Park PP 0052] gate driven conduction by a control signal) and the current signal is generated when the first control signal is at the first level (When the second and third NMOS transistors MN2,MN3 are turned onm the second sense node SO2 is coupled with the ground node [Park PP 0061-0062]).
As per claim 10, Park does not explicitly teach “wherein the peripheral circuit further comprises: a reference signal output circuit configured to output a plurality of reference signals; a current-voltage conversion circuit connected with the error bit signal generating circuit and configured to receive the current signal and output a voltage signal based on the current signal; and a comparator circuit connected to the current-voltage conversion circuit and the reference signal output circuit and configured to receive and compare the voltage signal and at least one of the plurality of reference signals and output comparison results”
However, Missiroli, in an analogous art, teaches wherein the peripheral circuit further comprises: a reference signal output circuit configured to output a plurality of reference signals (the page buffer control voltages such as PB_SENSE, CSO_PRECH, SA_SENSE, SA_CSOC, and SA_CSOC 2 are raised of the same amount of the source voltage [Missiroli PP 0101]);
a current-voltage conversion circuit connected with the error bit signal generating circuit and configured to receive the current signal and output a voltage signal based on the current signal (the input QS of the sense latch 31 goes high. [Missiroli PP 0090], the condition to flip the sense latch 31 is satisfied when the sensing node SEN is discharged to the first node CSO. [Missiroli PP 0094]); and
a comparator circuit connected to the current-voltage conversion circuit and the reference signal output circuit and configured to receive and compare the voltage signal and at least one of the plurality of reference signals and output comparison results (the condition to flip the sense latch 31 is satisfied when the sensing node SEN is discharged to the first node CSO. [Missiroli PP 0094], The second NMOS transistor M 2 is configured to discharge the sensing node SEN when the voltage value of the first node CSO is lower than the gate voltage SA_SENSE [Missiroli PP 0065]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective
filing data of the claimed invention to have modified the page buffer circuit disclosed by Park to incorporate Missiroli’s teaching of page buffer sensing control, in order to improve sensing precision and overall read performance (capable of controlling sensing current more precisely and tightly. [Missiroli PP 0003], a sensing method and circuitry which ensures a reliable reading without increasing the latency time. [Missiroli PP 0031], allows performing more precise sensing with a tighter control of analog voltages. [Missiroli PP 0093]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Park’s invention.
As per claim 11, Park does not explicitly teach “wherein the page buffer to be counted further comprises: a pre-charging and pre-discharging circuit connected with a power source terminal and the sensing node and configured to charge the sensing node of the page buffer to be counted to the first voltage at the stage of error bit counting operation.”
However, Missiroli, in an analogous art, teaches wherein the page buffer to be counted further comprises: a pre-charging and pre-discharging circuit (a fourth switching circuit M 4 configured to provide a pre-charging path to the bit-line BL [Missiroli PP 0062], a ninth switching circuit M 9 configured to switch current path from the second voltage source VDC_PB to the sensing node SEN [Missiroli PP 0071]) connected with a power source terminal and the sensing node (The sensing node SEN is electrically coupled to the gate of the first PMOS transistor M 6 . [Missiroli PP 0069]) and configured to charge the sensing node of the page buffer to be counted to the first voltage (the sensing node SEN is charged to the voltage of the second voltage source VDC_PB. [Missiroli PP 0070]) at the stage of error bit counting operation.
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing data of the claimed invention to have modified the page buffer circuit disclosed by Park to incorporate Missiroli’s teaching of page buffer sensing control, in order to improve sensing precision and overall read performance (capable of controlling sensing current more precisely and tightly. [Missiroli PP 0003], a sensing method and circuitry which ensures a reliable reading without increasing the latency time. [Missiroli PP 0031], allows performing more precise sensing with a tighter control of analog voltages. [Missiroli PP 0093]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Park’s invention.
As per claim 12, Park significantly teaches the page buffer to be counted further comprises a second latch (The first and second latch units 225 , 226 [Park PP 0047]), a ninth transistor and a tenth transistor (The seventh NMOS transistor MN 7 … and the eighth NMOS transistor MN 8 [Park PP 0055]), wherein a first terminal of the ninth transistor is connected to the sensing node of the page buffer to be counted (The seventh NMOS transistor MN 7 is coupled between the second sense node SO 2 and node MQ [Park PP 0055]), a second terminal of the ninth transistor is connected to a first terminal of the tenth transistor (The seventh NMOS transistor MN 7 is coupled between the second sense node SO 2 and node MQ, and the eighth NMOS transistor MN 8 is coupled between the second sense node SO 2 and node MQ_N. [Park PP 0055]), a second terminal of the tenth transistor is connected to a second power source voltage (the second sense node SO 2 is coupled with the ground node [Park PP 0061]), and a gate terminal of the tenth transistor is connected to the second latch (the node MQ_N … data is latched [Park PP 0061-0064]);
the second latch is configured to store a programming information or a verification information (Each of the latches is configured to latch data for a program or to read data stored in a memory cell [Park PP 0010]); and
a gate terminal of the ninth transistor is configured to receive a read signal (A third data transmission signal MTRAN is inputted to the gate of the seventh NMOS transistor MN 7 [Park PP 0055]).
As per claim 13, Park significantly teaches A memory system comprising: a memory device comprising (FIG. 2A is a block diagram of a nonvolatile memory device according to an embodiment of this disclosure. [Park PP 0037]) a peripheral circuit (the nonvolatile memory device 200 includes a memory cell array 210 , a page buffer unit 220 [Park PP 0038])
that comprises a set of page buffers (The page buffer unit 220 includes a plurality of the page buffers. Each of the page buffers is coupled with one or more bit lines. [Park PP 0040]),
wherein the set of page buffers comprises N page buffers (The page buffer unit 220 includes a plurality of the page buffers. [Park PP 0040])
with N being an integer larger than 1 (an N number of latch units coupled in common to the second sense node, wherein N is a natural number greater than two. [Park PP 0024]); and
a memory controller coupled to the memory device (The control unit 260 is configured to control program, read, and erase operations for data by controlling the page buffer unit 220 [Park PP 0042]), wherein the memory controller is configured to control the memory device (The control unit 260 is configured to control program, read, and erase operations [Park PP 0042]).
Park does not explicitly teach “an error bit signal generating circuit and a plurality of first transistors” and “the error bit signal generating circuit is connected with sensing nodes of the page buffers, and respective sensing nodes of every two adjacent page buffers in the set of page buffers are connected with one of the first transistors”
However, Missiroli, in an analogous art, teaches an error bit signal generating circuit (The page buffer circuit … comprises a sensing node SEN … and a sense latch configured to latch a voltage [Missiroli PP 0062-0069]) and a plurality of first transistors (a second switching circuit M2 arranged between the first node CSO and the sensing node SEN [Missiroli PP 0062-65])
the error bit signal generating circuit is connected with sensing nodes of the page buffers (A sensing node SEN … electrically coupled to switching circuits and a sense latch [Missiroli PP 0062-0069]), and respective sensing nodes of every two adjacent page buffers in the set of page buffers are connected with one of the first transistors (switching circuits arranged between the first node CSO and the sensing node SEN [Missiroli PP 0062-0065])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective
filing data of the claimed invention to have modified the page buffer circuit disclosed by Park to incorporate Missiroli’s teaching of page buffer sensing control, in order to improve sensing precision and overall read performance (capable of controlling sensing current more precisely and tightly. [Missiroli PP 0003], a sensing method and circuitry which ensures a reliable reading without increasing the latency time. [Missiroli PP 0031], allows performing more precise sensing with a tighter control of analog voltages. [Missiroli PP 0093]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Park’s invention.
As per claim 14, Park significantly teaches after the first voltage is received at the sensing node, generating a second voltage at the sensing node of the page buffer to be counted based on an information stored in the page buffer (a voltage level of the first sense node SO 1 is changed according to a voltage level of the node MQ [Park PP 0075]); and
receiving a second voltage by an error bit signal generating circuit and generating a current signal based on the second voltage being smaller than the first voltage (The sensing component is configured to sense a voltage level of the first sense node SO 1 [Park PP 0046], The second and third NMOS transistors MN 2 , MN 3 are coupled in series between the second sense node SO 2 and a ground node. [Park PP 0052]).
Park does not explicitly teach “at a stage of error bit counting operation, receiving a first voltage at a sensing node of a page buffer to be counted”
However, Missiroli, in an analogous art, teaches at a stage of error bit counting operation, receiving a first voltage at a sensing node of a page buffer to be counted (the sensing node SEN is charged to the voltage of the second voltage source VDC_PB [Missiroli PP 0070])
Therefore, it would have been obvious for one of ordinary skill in the art before the effective
filing data of the claimed invention to have modified the page buffer circuit disclosed by Park to incorporate Missiroli’s teaching of page buffer sensing control, in order to improve sensing precision and overall read performance (capable of controlling sensing current more precisely and tightly. [Missiroli PP 0003], a sensing method and circuitry which ensures a reliable reading without increasing the latency time. [Missiroli PP 0031], allows performing more precise sensing with a tighter control of analog voltages. [Missiroli PP 0093]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Park’s invention.
As per claim 15, Park significantly teaches wherein a plurality of page buffers constitutes a set of page buffers, and the respective sensing nodes of two adjacent page buffers in the set of page buffers are connected through a first transistor (The latch selection circuit is configured to select a node of the latch circuit and couple the selected node with the second sense node SO 2. [Park PP 0048]); and
the method further comprises: at the stage of error bit counting operation, turning on the first transistors between the page buffer to be counted and the error bit signal generating circuit (When the third data transmission signal MTRAN is in a high level voltage, the seventh NMOS transistor MN 7 is turned on so that the node MQ is coupled with the second sense node SO 2 [Park PP 0061]); and
at the stage of error bit counting operation, turning off the first transistors between the page buffer to be counted and the Nth page buffer (the first, second, and fourth data transmission signals CTRAN, CTRAN_N, and MTRAN_N of a low level voltage are applied. [Park PP 0061).
As per claim 16, Park significantly teaches further comprising: at a stage of non-error bit counting operations, turning off the first transistors (The latch selection circuit is configured to select a node of the latch circuit and couple the selected node with the second sense node SO 2 . [Park PP 0048], When the third data transmission signal MTRAN is in a high level voltage, the seventh NMOS transistor MN 7 is turned on [Park PP 0061]).
As per claim 17, Park significantly teaches wherein the page buffer comprises a first latch (The first and second latch units 225 , 226 each include a latch circuit (for example, latch L 1 ) [Park PP 0048]), a second transistor and a third transistor (The first and second latch units 225 , 226 include fifth to eighth NMOS transistors MN 5 to MN 8 [Park PP 0050]), a first terminal of the second transistor is connected to the sensing node (The fifth NMOS transistor MN 5 is coupled between the second sense node SO 2 and node CQ [Park PP 0054]), a second terminal of the second transistor is connected to a first terminal of the third transistor (The first and second inverters IN 1 , IN 2 are coupled together to form a first latch L 1 between the node CQ and the node CQ_N [Park PP 0056]) and a second terminal of the third transistor is connected to a second power source voltage (The second and third NMOS transistors MN 2 , MN 3 are coupled in series between the second sense node SO 2 and a ground node. [Park PP 0052]); and
the generating the second voltage at the sensing node of the page buffer based on the information stored in the page buffer comprises: at the stage of error bit counting operation, turning on the second transistor in the page buffer to be counted (When the third data transmission signal MTRAN is in a high level voltage, the seventh NMOS transistor MN 7 is turned on [Park PP 0061]), receiving the information stored in the first latch at a gate terminal of the third transistor (The first and second latch units 225 , 226 are commonly coupled with the second sense node SO 2 and are configured to latch data in response to the operation of the data conversion unit 224 or transfer latched data. [Park PP 0047]) and generating the second voltage at the sensing node of the page buffer (thus, the second sense node SO 2 is coupled with the ground node to thus obtain a low level voltage. [Park PP 0061]).
As per claim 18, Park significantly teaches wherein the receiving the second voltage and the generating the current signal based on the second voltage being smaller than the first voltage comprises: receiving the second voltage by a first branch of the error bit signal generating circuit and generating a first control signal at a first level for turning on a second branch of the error bit signal generating circuit based on the second voltage being smaller than the first voltage (When the first sense node SO 1 has a high level voltage at the same time that the third NMOS transistor MN 3 is turned on, the second NMOS transistor MN 2 is also turned on … Thus, the second sense node SO 2 is coupled with the ground node to thus obtain a low level voltage. [Park PP 0060-0061]); and
receiving the first control signal at the first level by the second branch of the error bit signal generating circuit and generating the current signal (The second and third NMOS transistors MN 2 , MN 3 are coupled in series between the second sense node SO 2 and a ground node. [Park PP 0052]).
As per claim 19, Park significantly teaches wherein the receiving the second voltage by the first branch of the error bit signal generating circuit and generating a first control signal at a first level for turning on the second branch based on the second voltage being smaller than the first voltage comprises: at the stage of error bit counting operation, turning on a fifth transistor (When the first sense node SO 1 has a high level voltage at the same time that the third NMOS transistor MN 3 is turned on [Park PP 0060]), receiving the second voltage at a gate terminal of a fourth transistor and a gate terminal of a sixth transistor (The gate of the second NMOS transistor MN 2 is coupled with the first sense node SO 1 [Park PP 0052]) and generating the first control signal at the first level based on the second voltage being smaller than the first voltage (Thus, the second sense node SO 2 is coupled with the ground node to thus obtain a low level voltage [Park PP 0061]).
As per claim 20, Park significantly teaches wherein the receiving the first control signal at the first level by the second branch of the error bit signal generating circuit and generating the current signal comprises: at the stage of error bit counting operation, turning on a seventh transistor (When the third data transmission signal MTRAN is in a high level voltage, the seventh NMOS transistor MN 7 is turned on [Park PP 0061]), receiving the first control signal at the first level by a gate terminal of an eighth transistor (a fourth data transmission signal MTRAN_N is inputted to the gate of the eighth NMOS transistor MN 8 .[Park PP 0055]) and generating the current signal (Thus, the second sense node SO 2 is coupled with the ground node to thus obtain a low level voltage. [Park PP 0061]).
Conclusion
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ESAW T ABRAHAM/Primary Examiner, Art Unit 2112