DETAILED ACTION
This Office action is a response to the application filed on 10 July 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings were received on 10 July 2024 and are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over McJimsey et al. (US 8710810 B1; hereinafter “McJimsey”) and in view of Priego (US 8618850 B2; hereinafter “Priego”).
In re claim 1, McJimsey discloses power supply controller (Figs. 10, 11A-B, 14A-B, 17, 19-23, 34) provided in a switching power supply (Figs. 3, 10, 29, 32, ) configured to generate an output voltage (VO) from an input voltage (VIN), comprising: a synchronous input terminal (318); a synchronous output terminal (322); an output stage configured to power-convert the input voltage (Vin) to the output voltage ; a switching control circuit (306(1-3)) configured to power-convert the input voltage to the output voltage by performing switching control of the output stage in synchronization with a clock (Col 13 Lines 28-29: Each ramp signal 1020 and clock signal 1022 of a given modulator 1012 are synchronized with each other) and a reference clock (Col 35 Line 4-6: the switching clock frequency is provided from a fixed-frequency reference clock by a programmable counter); a synchronous output circuit (2904) configured to set a state of the synchronous output terminal to any one of a plurality of output states including first, second, and third output states (Col 23 Lines 46-50: In the example of FIG. 29, master unit 2902 has three outputs 2906(1)-(3), each connected to a circuitry 2908(1)-(3), respectively, that operate to drive each output to one of three states: high, low, and high-impedance (known as high-Z and tri-state)); and a synchronous input circuit (Figs. 10, 11A, 11B, 14A, 14B, 22A; 22B) configured to set a state of the synchronous input terminal to any one of a plurality of input states including first and second input states (Col 14 Lines 53-55: Switch 1130 opens at the beginning of each clock cycle and closes when comparator output 1134 changes state to indicate an end of a PWM pulse.), wherein the synchronous output circuit outputs a signal of a first level from the synchronous output terminal in the first output state, outputs a signal of a second level higher than the first level from the synchronous output terminal in the second output state, and sets an output impedance of the synchronous output circuit to be higher in the third output state than in the first output state and the second output state (shown in Figs. 30, 31, and explained in Col 26 Lines 25-29: In particular, graph 3000 shows a tri-state window 3008 based upon a tri-state low threshold Vth.sub.L and a tri-state high threshold Vth.sub.H. Graph 3000 also shows tri-state voltage Vtri, which is substantially midway between power source VDD rail 2924 and ground rail 2922), and wherein the synchronous input circuit (1602 in Fig. 16) is capable of pulling down the synchronous input terminal to the first level or pulling up the synchronous input terminal to the second level via a resistor (Col 2 Lines 54-58: the resistor between a first supply rail and a control line, activating a current source to provide a small current on each control line, the current acting to pull the control line towards a second supply rail, and measuring a voltage of each control line), pulls down the synchronous input terminal in the first input state, and pulls up the synchronous input terminal in the second input state (Col 25 Lines 1-7: current source 2912 is able to pull the voltage at that output close to rail 2924, and the voltage at that output approaches the potential of power source 2924. Where output 2906 is connected to ground 2922, current source 2912 cannot pull the voltage at that output high, and it remains substantially near potential of a ground rail 2922).
McJimsey does not disclose a switching control circuit (306(1-3)) configured to power-convert the input voltage to the output voltage by performing switching control of the output stage in synchronization with a reference clock signal.
Whereas, Priego discloses a power supply controller (Fig. 3) comprising a switching control circuit (PFD) configured to power-convert the input voltage to the output voltage by performing switching control of the output stage in synchronization with a reference clock signal (Col 2 Lines 26-28: the PLL is enabled to synchronize the internal DC-DC converter clock to an external reference clock).
Therefore, it would have been obvious before the effective filing date to have combined the power supply controller of McJimsey to be configured to perform the switching control in synchronization with the reference clock signal based, as taught by Priego, to have better control and better synchronization of the apparatus.
In re claim 2, McJimsey discloses a power supply controller (see above rejection), further comprising a mode setting circuit configured to set an operation mode of the power supply controller to a first mode (Col 36 Lines 52-56: In an alternative embodiment, reference clock 4302 is a narrow pulse and directly closes switch 4308 and sets RS latch 4312. RS latch 4312 is designed such that its reset input overrides its set input, thereby permitting pulse skipping.) or a second mode (Col 36 Lines 49-52: edge detector 4304 generates a pulse that briefly closes switch 4308 to discharge capacitor 4310 and sets pulse width modulator RS latch 4312 to begin a pulsewidth modulator pulse) based on given mode setting information, wherein the switching control circuit is configured to: perform the switching control in synchronization with the reference clock signal (Col Lines : reference clock 4302 is a narrow pulse and directly closes switch 4308 and sets RS latch 4312. RS latch 4312 is designed such that its reset input overrides its set input, thereby permitting pulse skipping).
McJimsey does not disclose an internal clock or a switching control circuit configured to perform the switching control in synchronization with the reference clock signal based on an internal clock signal or an input clock signal, which is supplied to the synchronous input terminal from an outside of the power supply controller, in the first mode; stop the switching control when the input clock signal is not supplied to the synchronous input terminal in the second mode; and perform the switching control in synchronization with the reference clock signal based on the input clock signal when the input clock signal is supplied to the synchronous input terminal in the second mode.
Whereas Priego discloses a power supply controller (Fig. 3) comprising a mode setting circuit (PLL) configured to set an operation mode of the power supply controller to a first mode or a second mode based on given mode setting information, wherein the switching control circuit is configured to: perform the switching control (PFD) in synchronization with the reference clock signal based on an internal clock signal or an input clock signal (Col 2 Lines 26-28: the PLL is enabled to synchronize the internal DC-DC converter clock to an external reference clock), which is supplied to the synchronous input terminal from an outside of the power supply controller, in the first mode; stop the switching control when the input clock signal is not supplied to the synchronous input terminal in the second mode (Col 6 Lines 34-36: a first configuration (master configuration), where the PFD is switched off or at least the functionality relating to the PLL of the PFD is switched off); and perform the switching control in synchronization with the reference clock signal based on the input clock signal when the input clock signal is supplied to the synchronous input terminal in the second mode (Col 2 Lines 32-36: This internal clock, that is accessible at an output pin (often referred to as "switch pin") of the DC-DC converter (or electronic device), can be used as master clock (or reference clock) to synchronize additional switch converters present in the system.).
Therefore, it would have been obvious before the effective filing date to have combined the power supply controller of McJimsey to be configured to perform the switching control in synchronization with the reference clock signal based on an internal clock signal or an input clock signal in a first mode or a second mode, as taught by Priego, to have better control and better synchronization of the apparatus.
In re claim 3, McJimsey discloses a power supply controller (see above rejection), wherein the synchronous output circuit from the synchronous output terminal in response to establishment of a predetermined clock output condition during an execution period of the switching control in the first mode or the second mode (Col 35 Lines 4-10: the switching clock frequency is provided from a fixed-frequency reference clock by a programmable counter. In this embodiment, the programmable counter divides the reference clock by a first constant during normal operation, and by a second constant smaller than the first constant when the switching clock frequency is increased.), and wherein the synchronous output circuit includes a first period in which the state of the synchronous output terminal is set to the first output state, a second period in which the state of the synchronous output terminal is set to the second output state, and a third period in which the state of the synchronous output terminal is set to the third output state (shown in Fig. 38 and further explained in Col 23 Lines 46-50: In the example of FIG. 29, master unit 2902 has three outputs 2906(1)-(3), each connected to a circuitry 2908(1)-(3), respectively, that operate to drive each output to one of three states: high, low, and high-impedance (known as high-Z and tri-state)).
McJimsey does not disclose a power supply controller, wherein the synchronous output circuit outputs an output clock signal, which is based on the reference clock signal, from the synchronous output terminal in response to establishment of a predetermined clock output condition during an execution period of the switching control in the first mode or the second mode.
Priego discloses a power supply controller (see above rejection), wherein the synchronous output circuit outputs an output clock signal (VCOUT), which is based on the reference clock signal, from the synchronous output terminal in response to establishment of a predetermined clock output condition during an execution period of the switching control (Col 3 Lines: 58-61: the first control loop in the master DC-DC converter performs the spread spectrum modulation of the frequency of the first clock signal and the slave devices synchronize to the first clock frequency in the first mode or the second mode, and wherein the synchronous output circuit includes a first period in which the state of the synchronous output terminal is set to the first output state, a second period in which the state of the synchronous output terminal is set to the second output state, and a third period in which the state of the synchronous output terminal is set to the third output state, in each cycle of the output clock signal during an output period of the output clock signal (Col 3 Lines 34-36: way to generate a clock (comparator output) and at the same time a ramp or sawtooth waveform).
Therefore, it would have been obvious before the effective filing date to have combined the power supply controller of McJimsey to configure synchronous output circuit outputs an output clock signal, which is based on the reference clock signal, from the synchronous output terminal in response to establishment of a predetermined clock output condition during an execution period of the switching control in the first mode or the second mode, as taught by Priego, to have better control, better synchronization, and a better output of the apparatus.
In re claim 4, McJimsey discloses a power supply controller, wherein the synchronous input circuit sets the state of the synchronous input terminal to one of the first and second input states.
McJimsey does not disclose a power supply controller, wherein the synchronous input circuit sets the state of the synchronous input terminal to one of the first and second input states during the output period of the output clock signal and sets the state of the synchronous input terminal to the other of the first and second input states during a non-output period of the output clock signal.
Whereas, Priego discloses a power supply controller, wherein the synchronous input circuit sets the state of the synchronous input terminal to one of the first and second input states during the output period of the output clock signal and sets the state of the synchronous input terminal to the other of the first and second input states during a non-output period of the output clock signal (Col 5 Lines : The output clock signal VCOOUT of the voltage controlled oscillator VCO is coupled in a feedback loop to an input of the phase frequency detector PFD).
Therefore, it would have been obvious before the effective filing date to have combined the power supply controller of McJimsey to have the synchronous input circuit sets the state of the synchronous input terminal to one of the first and second input states during the output period of the output clock signal and sets the state of the synchronous input terminal to the other of the first and second input states during a non-output period of the output clock signal, as taught by Priego, to have better control, better synchronization, and an improved output of the apparatus.
In re claim 5, McJimsey (see the above rejection) discloses a power supply controller (Figs. 29 and 31), further comprising a level detection circuit connected to the synchronous output terminal (2906), the level detection circuit (3104) detects which one of the first level and the second level a voltage of the synchronous output terminal in the third period belongs to (Col 26 Lines 25-29: In particular, graph 3000 shows a tri-state window 3008 based upon a tri-state low threshold Vth.sub.L and a tri-state high threshold Vth.sub.H. Graph 3000 also shows tri-state voltage Vtri, which is substantially midway between power source VDD rail 2924 and ground rail 2922).
McJimsey does not disclose a power supply controller, wherein when the output clock signal is output by the synchronous output circuit.
Whereas, Priego discloses a power supply controller (Fig. 4), further comprising a level detection circuit (CMP2) connected to the synchronous output terminal, wherein when the output clock signal is output by the synchronous output circuit (Col 7 Lines 62-64: At the output of comparator CMP2 a clock signal VCLK is provided that can be used as the rectangular pulse signal of the PLL, i.e. the PLL feedback signal.), the level detection circuit detects which one of the first level and the second level a voltage of the synchronous output terminal (Col 7 Lines 52-59: Comparator CMP2 monitors the voltage level of output voltage VMOD at node NOSC and compares it to a reference voltage VREFOSC)
Priego does not disclose the level detection circuit detects which one of the first level and the second level a voltage of the synchronous output terminal in the third period belongs to.
Therefore, it would have been obvious before the effective filing date to have combined the power supply controller further comprising a level detection circuit connected to the synchronous output terminal, the level detection circuit detects which one of the first level and the second level a voltage of the synchronous output terminal in the third period belongs to as taught by McJimsey, and wherein when the output clock signal is output by the synchronous output circuit as taught by Priego, to have better control, better synchronization, and an improved output of the apparatus.
In re claim 16, McJimsey discloses a power supply controller (Fig. 3), wherein the output stage includes an output element constituted by a switching element (314), and a rectifying element connected to the output element, and wherein a coil (310(1-N) ) is connected to a connection node between the output element and the rectifying element (316), and the output voltage is generated based on a current flowing through the coil when the output element is switched between turn-on and turn-off in the switching control of the output stage (Col 5 Lines 51-52: Thus, low side switch couples energy stored in inductor 310 to output Vout).
Therefore, it would have been obvious before the effective filing date to have combined the power supply controller taught by McJimsey and methods as taught by Priego, to have better control, better synchronization, and an improved output of the apparatus.
In re claim 17, McJimsey discloses a power supply controller (Fig. 3), wherein the synchronous output terminal in the power supply controller (308) is configured to be connected (CONTROL(1-N)) to a synchronous input terminal of another power supply controller (306(1-N) ) provided in the switching power supply.
Additionally, Priego discloses a similar power supply controller (Fig. 3), wherein the synchronous output terminal in the power supply controller (MASTER) is configured to be connected (SW) to a synchronous input terminal of another power supply controller (SLAVE1 or SLAVE2) provided in the switching power supply.
Therefore, it would have been obvious before the effective filing date to have combined the power supply controller taught by McJimsey and methods as taught by Priego, to have better control, better synchronization, and an improved output of the apparatus.
In re claim 18, McJimsey discloses a power supply controller (Fig. 5), wherein the synchronous input terminal in the power supply controller is configured to be connected to a synchronous output terminal of another power supply controller provided in the switching power supply. (Col. 6 Lines 15-19: A controller 326 in master 308 generates a respective CONTROL signal (e.g., a PWM signal) for each slave 306 in response to at least current sense signals I_sense and the value of Vout).
Additionally, Priego discloses a similar power supply controller (Fig. 3), wherein the synchronous output terminal in the power supply controller (MASTER) is configured to be connected (SW) to a synchronous input terminal of another power supply controller (SLAVE1 or SLAVE2) provided in the switching power supply. (Col 8 Lines 42-44: The output signal OUT (e.g. a voltage level) is sensed and fed back through a sensor gain stage SENSOR GAIN and feedback pin FB.)
Therefore, it would have been obvious before the effective filing date to have combined the power supply controller taught by McJimsey and methods as taught by Priego, to have better control, better synchronization, and an improved output of the apparatus.
Allowable Subject Matter
Claims 6-15 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all the limitations of the base claim and intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to dependent claim 6, McJimsey is considered the closest prior art. McJimsey discloses a power supply controller (see above rejections), wherein the synchronous input circuit (Figs. 10, 11A, 11B, 14A, 14B, 22A; 22B) sets the state of the synchronous input terminal (318) to the first input state during the output period of the output signal and sets the state of the synchronous input terminal to the second input state during the signal (Col 14 Lines 53-55: Switch 1130 opens at the beginning of each clock cycle and closes when comparator output 1134 changes state to indicate an end of a PWM pulse.), wherein the synchronous output circuit stops the output of the output clock signal in response to establishment of a predetermined clock stop condition (Col 13 Lines 46-47: the modulator's PWM output does not transition high during the clock cycle, resulting in pulse skipping).
Despite the similarity of the reference with the Applicant’s invention, McJimsey does not teach a power supply controller, wherein the synchronous input circuit sets the state of the synchronous input terminal to the first input state during the output period of the output clock signal and sets the state of the synchronous input terminal to the second input state during the non-output period of the output clock signal, and wherein the synchronous output circuit stops the output of the output clock signal in response to establishment of a predetermined clock stop condition after starting the output of the output clock signal, and wherein the clock stop condition includes a condition in which the voltage of the synchronous output terminal in the third period is detected by the level detection circuit as belonging to the second level. The other prior art on record does not provide the suggestion to modify McJimsey or Priego.
With respect to dependent claim 7, McJimsey is considered the closest prior art. McJimsey discloses a power supply controller (see above rejections), wherein the synchronous input circuit (Figs. 10, 11A, 11B, 14A, 14B, 22A; 22B) sets the state of the synchronous input terminal (318) to the second input state during the output period of the output signal and sets the state of the synchronous input terminal to the first input state during the signal (Col 14 Lines 53-55: Switch 1130 opens at the beginning of each clock cycle and closes when comparator output 1134 changes state to indicate an end of a PWM pulse.), wherein the synchronous output circuit stops the output of the output clock signal in response to establishment of a predetermined clock stop condition (Col 13 Lines 46-47: the modulator's PWM output does not transition high during the clock cycle, resulting in pulse skipping).
Despite the similarity of the reference with the Applicant’s invention, McJimsey does not teach a power supply controller, wherein the synchronous input circuit sets the state of the synchronous input terminal to the second input state during the output period of the output clock signal and sets the state of the synchronous input terminal to the first input state during the non-output period of the output clock signal, wherein the synchronous output circuit stops the output of the output clock signal in response to establishment of a predetermined clock stop condition after starting the output of the output clock signal, and wherein the clock stop condition includes a condition in which the voltage of the synchronous output terminal in the third period is detected by the level detection circuit as belonging to the first level. The other prior art on record does not provide the suggestion to modify McJimsey or Priego.
With respect to dependent claim 9, McJimsey is considered the closest prior art. McJimsey discloses a power supply controller (see above rejections). Additionally, Priego is considered a close prior art with a similar power supply controller, wherein the synchronous output circuit outputs an output clock signal from the synchronous output terminal, and wherein the synchronous output circuit is configured to: output an output clock signal, which is based on the reference clock signal.
Despite the similarity of the reference with the Applicant’s invention, McJimsey does not teach a power supply controller, wherein the synchronous output circuit outputs or does not output an output clock signal from the synchronous output terminal, and wherein the synchronous output circuit is configured to: output an output clock signal of a first pattern, which is based on the reference clock signal. Priego is also not found to teach a power supply controller, wherein the synchronous output circuit outputs or does not output an output clock signal from the synchronous output terminal, and wherein the synchronous output circuit is configured to: output an output clock signal of a first pattern, which is based on the reference clock signal, from the synchronous output terminal in response to establishment of a predetermined clock output condition during an execution period of the switching control when a predetermined forced output condition is not satisfied in the first mode; output an output clock signal of a second pattern, which is based on the reference clock signal, from the synchronous output terminal regardless of whether or not the clock output condition is satisfied during the execution period of the switching control when the forced output condition is satisfied in the first mode; output neither the output clock signal of the first pattern nor the output clock signal of the second pattern from the synchronous output terminal when the input clock signal is not supplied to the synchronous input terminal in the second mode; output the output clock signal of the first pattern, which is based on the input clock signal, from the synchronous output terminal in response to the establishment of the clock output condition during the execution period of the switching control when the input clock signal is supplied to the synchronous input terminal in the second mode and the input clock signal has the first pattern; and output the output clock signal of the second pattern, which is based on the input clock signal, from the synchronous output terminal regardless of whether or not the clock output condition is satisfied during the execution period of the switching control when the input clock signal is supplied to the synchronous input terminal in the second mode and the input clock signal has the second pattern. The other prior art on record does not provide the suggestion to modify McJimsey or Priego.
Claims 10-15 and 19 each depend, either directly or indirectly, from claim 9 and therefore contain allowable subject matter for the same reason explained above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure: Chakraborty, S. et al. US 9106201 B1 “Systems And Methods For DC-to-DC Converter Control,” Burnstein, A. et al. US 9407145 B1 “Systems And Methods For DC-to-DC Converter Control,” Hayashi, K. US 10778115 B2 “Control Systems,” Ahmad, F. et al. US 8233299 B2 “Dynamic Phase Timing Control For Multiple Regulators Or Phases;” Nagasawa, T. US 20110169471 A1 “SEMICONDUCTOR DEVICE AND POWER SOURCE DEVICE.“
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas A Chapa Mills whose telephone number is (571)272-3683. The examiner can normally be reached Mon-Fri 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NICOLAS ALDEN CHAPA MILLS/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838