Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This is the initial office action based on the application filed on July 10th, 2024, which claims 1-20 are presented for examination.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Claims 1-20 are pending in the application and have been examined below, of which, claims 1 and 11 are presented in independent form.
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Information Disclosure Statement
The information disclosure statement, filed on January 6th, 2025, complies with the provisions of 37 CFR 1.97, 1.98. The complied IDS has been placed in the application file and the information referred to therein has been considered as to the merits.
Claim Objections
Claims 1-10, 12, 15, and 20 are objected to because of the following informalities:
Claim 1 recites the limitation “a processing device” in line 6. It should be -- the [[a]] processing device --.
Claims 2-10: are dependent on claim 1 but not cure the deficiencies of that claim. Accordingly, they also are objected for the same reasons.
Claims 2 and 12 recite the limitations “have values” and “the values of non-loop-carried dependency variables” in lines 7 and 11, respectively. It should be -- have the values -- and -- the values of the non-loop-carried dependency variables --, respectively.
Claims 3-5 and 13-15: are dependent on claims 2 and 12, respectively, but not cure the deficiencies of those claims. Accordingly, they also are objected for the same reasons.
Claims 5 and 15 recite the limitation “calculating values of the loop-carried dependency variable for multiple iterations of the loop” in lines 1-2. It should be -- calculating the values of the loop-carried dependency variable for the multiple iterations of the loop --.
Claims 10 and 20 recite the limitations “the dispatch controller” and “set of operations in the order” in lines 2 and 4, respectively. They should be -- the dispatch interface controller – and “set of operations in [[the]] order”, respectively.
Appropriate correction is required.
Allowable Subject Matter
Claims 2-5 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 6-11 and 16-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 1-10 are directed to systems and fall within the statutory category of machines; Claims 11-20 are directed to methods and fall within the statutory category of processes. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Claims 1 and 11: recite the limitations of “
accessing, by a compiler executing on a processing device, a computer code listing;
determining that the computer code listing includes a loop with a loop-carried dependency variable;
optimizing the loop for parallel execution by removing the loop-carried dependency variable; and
compiling the computer code listing into executable software code with the loop executable in parallel in hardware.”
Step 2A Prong 1:
Steps (a) and (b) as drafted, can be done in human mind with the aid of pen and paper (mental process).
Step 2A Prong 2:
Claims 1 and 11: The judicial exception is not integrated into a practical application. In particular, the claims recite the following additional elements – “system,” “processing device,” “memory device,” “a compiler executing on a processing device,” “parallel execution,” “executable software code,” “loop executable in parallel,” and “hardware,” which are merely recitations of generic computing components and functions merely applying the abstract idea using (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Furthermore, steps (c) and (d) are merely applying the abstract idea and field of use/technological environment.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 1 and 11 not only recite a judicial exception but that the claim is directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claims 1 and 11: The additional elements, considering them both individually and in combination, do not amount to significantly more than the judicial exception.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, claims 1 and 11 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claims 6 and 16, the claims recite additional element recitations of “compiling the computer code listing to be executable in parallel, at least in part, on a coarse-grained reconfigurable array (CGRA) processor” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 6 and 16 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 6 and 16 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as they have not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, claims 6 and 16 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claims 7 and 17, the claims recite additional element recitations of “a hardware dispatch interface controller and a plurality of hardware processing elements that are arranged into a synchronous flow” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 7 and 17 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 7 and 17 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as they have not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, claims 7 and 17 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claims 8 and 18, the claims recite additional element recitations of “a processing circuitry for managing synchronous flow” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 8 and 18 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 8 and 18 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as they have not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, claims 8 and 18 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claims 9 and 19, the claims recite additional element recitations of “a compute pipeline for processing data” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 9 and 19 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 9 and 19 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as they have not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, claims 9 and 19 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Regarding claims 10 and 20, the claims recite additional element recitations of “wherein the synchronous flow is used to execute a plurality of work threads in parallel, and wherein the dispatch controller and the plurality of hardware processing elements pass messages to execute a predetermined set of operations in the order of the synchronous flow” which is merely a field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate the judicial exception into practical application. Moreover, claims 10 and 20 do not recite any other additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claims 10 and 20 also fail both Step 2A prong 2, thus the claims are directed to the judicial exception as they have not been integrated into practical application, and fail Step 2B as not amounting to significantly more. Therefore, claims 10 and 20 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 U.S.C § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 11 are rejected under 35 U.S.C. § 103 as being unpatentable over Michimoto et al. (Pub. No.: US 2006/0277529 – IDS filed 1/6/2025 – hereinafter, Michimoto) in view of Lin et al. (Pub. No.: US 2012/0167069– IDS filed 1/6/2025 – hereinafter, Lin).
Regarding claim 1:
Michimoto discloses a system comprising:
a processing device (FIG. 4A and associated text, such as, “As shown in FIG. 4 (a), a compiler apparatus 202 converts a source program 201 described in a high-level language, such as the C language, into a machine language program 203 which is executable by a processor…In the present embodiment, the target processor of the compiler apparatus 202 is a processor that is capable of executing a plurality of instructions in parallel.” (See para [0067])); and a memory device configured to store instructions, which when executed by the processing device (FIG. 3A and associated text, such as, “Here, ‘ld r0, (r1+)’ is an instruction to load data at an address stored in a register r1 from a main memory ” (See para [0018]). FIG. 4A and associated text, such as, “As shown in FIG. 4A, a compiler apparatus 202 converts a source program 201 described in a high-level language, such as the C language, into a machine language program 203 which is executable by a processor. The compiler apparatus 202 is composed of a parsing unit 204, an optimization unit 205, and an output unit 206. In the present embodiment, the target processor of the compiler apparatus 202 is a processor that is capable of executing a plurality of instructions in parallel.” (See para [0067])), cause the processing device to perform operations comprising:
accessing, by a compiler executing on a processing device, a computer code listing (“the compiler apparatus according to an aspect of the present invention converts a source program into a machine language program for a processor which is capable of parallel processing, and is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language;” (See para [0024]));
determining that the computer code listing includes a loop with a loop-carried dependency variable (“a data dependence that exists between iterations is particularly referred to as a ‘loop-carried dependence’. This loop-carried dependence does not exist between the instructions of the body. To be more specific, a loop-carried dependence is a dependence relation that arises to allow a value obtained by an execution of an arithmetic expression within an iteration to be used in the iterations that follow. When this dependence relation exists, an arithmetic expression of the referencing side is prohibited from preceding an arithmetic expression of the defining side in execution. Moreover, in the present specification, a dependence relation that includes both a loop-carried dependence and one of the above-mentioned three dependences is referred to as follows. When a loop-carried dependence and a true dependence exist between two instructions, this relation is referred to as a ‘loop-carried true dependence’. When a loop-carried dependence and an antidependence exist between two instructions, this relation is referred to as a ‘loop-carried antidependence’. When a loop-carried dependence and an output dependence exist between two instructions, this relation is referred to as a ‘loop-carried output dependence’” (See para [0016]));
optimizing the loop for parallel execution by removing the loop-carried dependency variable (FIGS. 17 A-C and associated text, such as, “FIG. 17A shows a cyclic path that includes 5 longest paths, with each path length being 6 cycles…FIG. 17B shows a cyclic path obtained after the instruction mov has been inserted into the leaf node b so that the loop-carried dependence cut is executed between the instructions b and a…FIG. 17C shows a cyclic path obtained after the instruction mov has been inserted into the leaf node c so that the loop-carried dependence cut is executed between the instructions c and b…As can be understood, the number of the longest paths is reduced more in the case of FIG. 17B than the case of FIG; 17C. That is, for the case where the transfer instruction is inserted into a leaf node, the number of cyclic paths with longer path lengths can be reduced by the loop-carried dependence cut performed by the insertion of the transfer instruction into the leaf node that has more, longer cyclic paths” (See paras [0130] – [0133]). FIG. 19A-B and associated text, such as, “FIG. 19A shows a cyclic path that includes 2 loop-carried dependences, which exist respectively between the instructions c and b and between the instructions b and a. The path length of this cyclic path is 16 cycles as shown…FIG. 19B shows a cycle path obtained after the instruction mov has been inserted into the root node a of the cyclic path shown in FIG. 19A…In this way, the path length is shortened, thereby easing the instruction placement constraint imposed during software pipelining…Meanwhile, FIG. 19C shows a cycle path obtained after the instruction mov has been inserted into the leaf node c of the cyclic path shown in FIG. 19A As shown, the cyclic path whose path length is 16 cycles with a dependence distance of 2 is eliminated” (See paras [0184] – [0143])); and
But Michimoto does not explicitly teach:
compiling the computer code listing into executable software code with the loop executable in parallel in hardware.
However, Lin discloses:
compiling the computer code listing into executable software code with the loop executable in parallel in hardware (“Some embodiments discussed herein may provide loop parallelization based on loop splitting and/or index array. As discussed above, the issue on how to effectively enable both control and data speculation for general loop optimizations such as parallelization, vectorization, loop distribution, and fusion remains open. To this end, loop parallelization may be achieved based on loop splitting in an embodiment. In some embodiments, the compiler framework may be extended to unify control and data speculation that enables more loop optimizations, especially parallelization. Also, loop splitting techniques (e.g., based on mis-speculation driven loop splitting) may allow for more loops being speculatively optimized.” (See para [0009])).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin into the teachings of Michimoto because that would have provided a generic technique to break control/data flow dependences and enable more loop optimizations, such as parallelization as suggested by Lin (See para [0011]).
Regarding claim 11:
This is a method version of the rejected system claim 1 above, wherein all the limitations of this claim have been noted in the rejection of claim 1 and is therefore rejected under similar rationale.
Claims 6-10 and 16-20 are rejected under 35 U.S.C. § 103 as being unpatentable over Michimoto in view of Lin as applied to claims 1 and 11 above, and further in view of Choi et al. (Patent No.: US 9,727,460 – IDS filed 1/6/2025 – hereinafter, Choi).
Regarding claim 6:
The rejection of claim 1 is incorporated, but Michimoto and Lin do not explicitly teach:
wherein compiling the computer code listing comprises compiling the computer code listing to be executable in parallel, at least in part, on a coarse-grained reconfigurable array (CGRA) processor.
However, Choi discloses:
wherein compiling the computer code listing comprises compiling the computer code listing to be executable in parallel, at least in part, on a coarse-grained reconfigurable array (CGRA) processor (“The processor core 110 may process a loop operation in parallel by using several FUs 113 of the processor core 110 in the CGRA mode.” (See Col. 4, line 64 – Col. 5, line 20)).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Choi into the teachings of Michimoto and Lin because that would have scheduled of optimized FUs may be compiled in a given loop based on an architecture of a reconfigurable processor. Therefore, various types of memory mapping methods of a configuration memory may be flexibly determined, and a memory space of the configuration memory may be used efficiently as suggested by Choi (See Col. 11, lines 59-65).
Regarding claim 7:
The rejection of claim 6 is incorporated, but Michimoto and Lin do not explicitly teach:
wherein the CGRA processor comprises a hardware dispatch interface controller and a plurality of hardware processing elements that are arranged into a synchronous flow.
However, Choi discloses:
wherein the CGRA processor comprises a hardware dispatch interface controller and a plurality of hardware processing elements that are arranged into a synchronous flow (“The apparatuses and units described herein may be implemented using hardware components. The hardware components may include, for example, controllers, sensors, processors, generators, drivers, and other equivalent electronic components.” (See Col. 12, lines 28-51). Also, see claim 18 “A reconfigurable processor comprising: a processor core comprising a plurality of function units (FUs) configured to process a loop in a coarse-grained reconfigurable array (CGRA) mode; and a configuration memory configured to store configuration data generated by the FUs based on a memory mapping scheme determined by a compiler, wherein the compiler is configured to: analyze parallelism of a loop of a program code based on architecture information regarding an architecture of the reconfigurable processor and information regarding the configuration memory, the analysis including determining a number of FUs to be activated in each cycle of the loop, schedule groups of the FUs to be activated in each cycle of the loop based on the analyzed parallelism, generate configuration data of each cycle, select the memory mapping scheme from among a plurality of memory mapping schemes based on the scheduling result, and store the generated configuration data in the configuration memory based on the selected memory mapping scheme, wherein the generated configuration data of a plurality of cycles of the loop is mapped together on a row of the configuration memory when some of the FUs are activated according to the scheduling result.”).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Choi into the teachings of Michimoto and Lin because that would have scheduled of optimized FUs may be compiled in a given loop based on an architecture of a reconfigurable processor. Therefore, various types of memory mapping methods of a configuration memory may be flexibly determined, and a memory space of the configuration memory may be used efficiently as suggested by Choi (See Col. 11, lines 59-65).
Regarding claim 8:
The rejection of claim 7 is incorporated, but Michimoto and Lin do not explicitly teach:
wherein the dispatch interface controller includes a processing circuitry for managing synchronous flow.
However, Choi discloses:
wherein the dispatch interface controller includes a processing circuitry for managing synchronous flow (See claim 18 “A reconfigurable processor comprising: a processor core comprising a plurality of function units (FUs) configured to process a loop in a coarse-grained reconfigurable array (CGRA) mode; and a configuration memory configured to store configuration data generated by the FUs based on a memory mapping scheme determined by a compiler, wherein the compiler is configured to: analyze parallelism of a loop of a program code based on architecture information regarding an architecture of the reconfigurable processor and information regarding the configuration memory, the analysis including determining a number of FUs to be activated in each cycle of the loop, schedule groups of the FUs to be activated in each cycle of the loop based on the analyzed parallelism, generate configuration data of each cycle, select the memory mapping scheme from among a plurality of memory mapping schemes based on the scheduling result, and store the generated configuration data in the configuration memory based on the selected memory mapping scheme, wherein the generated configuration data of a plurality of cycles of the loop is mapped together on a row of the configuration memory when some of the FUs are activated according to the scheduling result.”).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Choi into the teachings of Michimoto and Lin because that would have scheduled of optimized FUs may be compiled in a given loop based on an architecture of a reconfigurable processor. Therefore, various types of memory mapping methods of a configuration memory may be flexibly determined, and a memory space of the configuration memory may be used efficiently as suggested by Choi (See Col. 11, lines 59-65).
Regarding claim 9:
The rejection of claim 7 is incorporated, Michimoto further discloses:
wherein a hardware processing element comprises a compute pipeline for processing data (“Software pipelining is an optimization technique whereby the complier converts the loop body into machine language instructions in a manner that parallels a pipeline so as to improve performance in the instruction execution.” (See para [0007]). “The present invention was conceived in view of the problems described above, and has an object of providing a compiler apparatus which can perform software pipelining optimization so that the number of execution cycles taken to complete a loop process can be significantly reduced.” (See para [0023])).
Regarding claim 10:
The rejection of claim 7 is incorporated, Michimoto further discloses:
wherein the synchronous flow is used to execute a plurality of work threads in parallel, and wherein the dispatch controller and the plurality of hardware processing elements pass messages to execute a predetermined set of operations in the order of the synchronous flow (“Software pipelining is an optimization technique whereby the complier converts the loop body into machine language instructions in a manner that parallels a pipeline so as to improve performance in the instruction execution.” (See para [0007]). “The present invention was conceived in view of the problems described above, and has an object of providing a compiler apparatus which can perform software pipelining optimization so that the number of execution cycles taken to complete a loop process can be significantly reduced.” (See para [0023])).
Regarding claim 16:
The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 6 and is therefore rejected under similar rationale.
Regarding claim 17:
The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 7 and is therefore rejected under similar rationale.
Regarding claim 18:
The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 8 and is therefore rejected under similar rationale.
Regarding claim 19:
The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 9 and is therefore rejected under similar rationale.
Regarding claim 20:
The rejection of base claim 11 is incorporated. All the limitations of this claim have been noted in the rejection of claim 10 and is therefore rejected under similar rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bharadwaj et al. (Pub. No.: US 2015/0007154) discloses the methods and systems that enable such vectorization by using computer program code, applications and/or services, including computer code associated with computer languages available in architectures having hardware/software that support speculative vectorization of loops with runtime data dependences.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HANH THI MINH BUI whose telephone number is (571)270-1976. The examiner can normally be reached Monday - Friday: 7-3.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung S. Sough can be reached at 571-272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HANH THI-MINH BUI/Primary Examiner, Art Unit 2192 August 6th, 2026
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