DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 08/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS statement has been considered by the Examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/ patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/ patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. US 11436160. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent basically claim the same subject matter as the claims of the instant application. For example, the token used in the claims of the patent is replaced with set of bits in the claims of the instant application.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4 of the U.S. Patent No. 11436160. Although the claims at issue are not identical, they are not patentably distinct from each other. The difference is that process token in the patent 11436160 is replaced with set of bits in the instant application.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17 and 18 of the U.S. Patent No. 11436160. Although the claims at issue are not identical, they are not patentably distinct from each other. The difference is that process token in the patent 11436160 is replaced with set of bits in the instant application.
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17 and 18 of the U.S. Patent No. 11436160. Although the claims at issue are not identical, they are not patentably distinct from each other (process token in the patent 11436160 is replaced with set of bits in the instant application and the class of the invention is different (claim 9 is a method claim, but claim 16 is a CRM claim).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12061558. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the patent basically claim the same subject matter as the claims of the instant application. For example, the token used in the claims of the patent is replaced with set of bits in the claims of the instant application.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 4 of the U.S. Patent No. 12061558. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 12 of the U.S. Patent No. 12061558. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 12 of the U.S. Patent No. 12061558. Although the claims at issue are not identical, they are not patentably distinct from each other although claims 16 of Patent No. 12061558 and claim 9 of instant application are of different class (i.e., method and computer-readable storage medium).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 8, 9, 11, 15, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki; Daisuke et al. US 20100122108 (hereinafter Suzuki) in view of Khatri; Mukund P. et al. US 20190272174 (hereinafter Khatri) and further in view of Stark; Tomer et al. US 20180004445 (hereinafter Stark).
As per claim 1, Peter Suzuki teaches: A system, comprising: an integrated circuit (IC) comprising:
Suzuki discloses: an initialization circuit configured to obtain a first set of bits, and store the first set of bits [in the first IC memory portion] (“A SubBytes initialization circuit 502 initializes data input from the intermediate value storage register 406 and stores the data as an operation result in an internal register 503.” Suzuki: para. 78 and fig. 5);
a processing circuit configured to store data corresponding to a process request [in the second IC memory portion] (“At the next cycle, a SubBytes processing circuit 505 processes the data in the internal register and returns the operation result to the intermediate value storage register 406.” Suzuki: para. 78 and fig. 5);
Suzuki does not teach, however; Khatri teaches: a first IC memory portion (“an integrated circuit 200 (or chip) that integrates the processor 102/104 and a field programmable gate array (FPGA) 202 into a single silicon-based device 204 as an embedded computing platform. That is, the processor 102/104 and the FPGA 202 are packaged and/or fabricated together in the same die for male/female mating to a single socket (such as a processor socket on a motherboard). Exemplary embodiments may offload workloads from the processor 102/104 to the FPGA 202, thus accelerating execution of processing tasks and instructions. The processor 102/104 and the FPGA 202 are packaged as a hybrid system on chip (SoC) 206. The processor 102/104 and the FPGA 202 may communicate via a network interface to a communications link 208 (such as the point-to-point QuickPoint Interconnect or UltraPath Interconnect). The processor 102/104 and the FPGA 202 may even share an integrated memory device 210, thus allowing the FPGA 202 to have its own dedicated portion or cache memory [a first or a second memory portion] 212 also fabricated or integrated into the integrated circuit 200.” Khatri: para. 18).
a second IC memory portion (Khatri: para. 18);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Suzuki with the teachings of Khatri to meet the preceding limitations. One of ordinary skill in the art would have been motivated to make such modification since such techniques were known at the time of the instant invention and would have been applied in a predictable manner to offload a portion of the execution to another processing device.
The combination of Suzuki and Khatri does not teach; however, Stark discloses: data protection circuit configured to: receive a request to access the second IC memory portion comprising the data (“In response to receiving a memory access request, the metadata value included in the address pointer associated with the memory access request may be compared to the metadata value included in the metadata data structure pointed to by the at least a portion of the linear address. If the two metadata values are the same, the memory access may be allowed. If the two metadata values are not the same, a fault may be generated.” Stark: para. 50),
determine that a second set of bits matching the first set of bits is not received, and in response to the determination, deny access to the data (In response to receiving a memory access request, the metadata value included in the address pointer associated with the memory access request may be compared to the metadata value included in the metadata data structure pointed to by the at least a portion of the linear address. If the two metadata values are the same, the memory access may be allowed. If the two metadata values are not the same, a fault may be generated.” Stark: para. 50),
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Suzuki and Khatri with the teaching of Stark, to meet the preceding limitations. One of ordinary skill in the art would have been motivated to make such modification since such techniques were known at the time of the instant invention and would have been applied to verify intended data.
As per claim 2, the rejection of claim 1 is incorporated herein, Suzuki does not teach; however, Khatri teaches: the initialization circuit is configured to obtain the first set of bits via one of a register write or a direct memory access (data is received form memory. Khatri: para. 13).
As per claim 4, the rejection of claim 1 is incorporated herein. The combination of Suzuki and Khatri does not explicitly teach, however; Stark discloses: the data protection circuit is configured to determine that the second set of bits matching the first set of bits is not received comprises determining that the second set of bits does not match the first set of bits (“…the comparison failed, precautionary action can be taken at 294.”. Stark: para. 70).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Suzuki and Khatri with the teaching of Stark to meet the preceding limitations. One of ordinary skill in the art would have been motivated to make such modification since such techniques were known at the time of the instant invention and would have been applied to verify intended data.
As per claim 8, the rejection of claim 1 is incorporated herein. Suzuki does not teach, however; Khatri discloses the IC comprises one of a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC) (Khatri:paa.18).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Suzuki with the teaching of Khatri to meet the preceding limitations. One of ordinary skill in the art would have been motivated to make such modification since such techniques were known at the time of the instant invention and would have been applied use the method on an application specific integrated circuit.
As per claim 9, this claim defines a method that corresponds to system of claim 1 and does not define beyond limitations of claim 1. Therefore, claim 9 is rejected with the same rational as the rejection of claim 1.
As per claim 11, this claim defines a method that corresponds to system of claim 4 and does not define beyond limitations of claim 4. Therefore, claim 11 is rejected with the same rational as the rejection of claim 4.
As per claim 15, this claim defines a method that corresponds to system of claim 8 and does not define beyond limitations of claim 8. Therefore, claim 15 is rejected with the same rational as the rejection of claim 8.
As per claim 16, this claim defines a computer-readable storage medium storing instructions corresponding to the system of claim 1 and does not define beyond limitations of claim 1. Therefore, claim 16 is rejected with the same rational as in the rejection of claim 1.
As per claim 18, this claim defines a computer-readable storage medium storing instructions corresponding to the system of claim 4 and does not define beyond limitations of claim 4. Therefore, claim 18 is rejected with the same rational as in the rejection of claim 4.
Claims 3, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki in view of Khatri in view of Stark and further in view of Imbert de Tremiolles, Ghislain US 20010013048 (hereinafter Imbert).
As per claim 3, the rejection of claim 1 is incorporated herein. The combination of Suzuki, Khatri and Stark does not explicitly teach, however, Imbert discloses: the initialization circuit is configured to clear at least one of the first IC memory portion or the second IC memory portion prior to storing the first set of bits (“At initialization, before the evaluation process takes place, all latches 41-1 to 41-p are set to "0" so that all Numbers are selected.”. Imbert: para. 61).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Suzuki, Khatri and Stark with the teaching of Imbert to meet the preceding limitations. One of ordinary skill in the art would have been motivated to make such modification since such techniques were known at the time of the instant invention and would have been applied to prevent unexpected behavior and bugs by ensuring that variables have a known starting state.
As per claim 10, this claim defines a method that corresponds to system of claim 3 and does not define beyond limitations of claim 3. Therefore, claim 10 is rejected with the same rational as the rejection of claim 3.
As per claim 17, this claim defines a computer-readable storage medium storing instructions corresponding to the system of claim 3 and does not define beyond limitations of claim 3. Therefore, claim 17 is rejected with the same rational as in the rejection of claim 3.
Claims 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki in view of Khatri in view of Stark and further in view of Jogand-Coulomb; Fabrice et al. US 8452934 (hereinafter Jogand-Coulomb).
As per claim 5, the rejection of claim 1 is incorporated herein. The combination of Suzuki, Khatri and Stark does not explicitly teach, however, Jogand-Coulomb discloses: the data protection circuit is configured to clear the second IC memory portion in response to determining that the second set of bits matching the first set of bits is not received (“wherein the input includes a second request to modify a second memory address corresponding to a second write protected portion of a file allocation table (FAT) that is stored in the non-volatile memory and that indicates clusters associated with the protected files; and when the authentication data does not match a stored credential, discarding the first request and the second request.” Jogand-Coulomb: col. 16, line 33-41).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Suzuki, Khatri and Stark with the teaching of Jogand-Coulomb to meet the preceding limitations. One of ordinary skill in the art would have been motivated to make such modification since such techniques were known at the time of the instant invention and would have been applied to prevent unauthorized access to system resources.
As per claim 12, this claim defines a method that corresponds to system of claim 5 and does not define beyond limitations of claim 5. Therefore, claim 12 is rejected with the same rational as the rejection of claim 5.
As per claim 19, this claim defines a computer-readable storage medium storing instructions corresponding to the system of claim 5 and does not define beyond limitations of claim 5. Therefore, claim 19 is rejected with the same rational as in the rejection of claim 5.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki in view of Khatri in view of Stark and further in view of Szczepaniak; Alex et al. US 20180304856 (hereinafter Szczepaniak)
As per claim 6, the rejection of claim 1 is incorporated herein. The combination of Suzuki, Khatri and Stark does not explicitly teach, however, Szczepaniak discloses: the data protection circuit is configured to encrypt the data in the second IC memory portion in response to determining that the second set of bits matching the first set of bits is not received. (“the processor is further configured to attempt to locally, wirelessly deliver a copy of a valid encrypted key to the wireless device, responsive to failure of verification of the encrypted key.” Szczepaniak: claim 18).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Suzuki, Khatri and Stark with the teaching of Szczepaniak to meet the preceding limitations. One of ordinary skill in the art would have been motivated to make such modification since such techniques were known at the time of the instant invention and would have been applied to prevent unauthorized access to system resources.
As per claim 13, this claim defines a method that corresponds to system of claim 6 and does not define beyond limitations of claim 6. Therefore, claim 13 is rejected with the same rational as the rejection of claim 6.
Claims 7, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki in view of Khatri in view of Stark and further in view of Tsukazaki; Fumiak US 9058507 (hereinafter Tsukazaki).
As per claim 7, the rejection of claim 1 is incorporated herein. The combination of Suzuki, Khatri and Stark does not explicitly teach, however; Tsukazaki discloses: the first set of bits comprises a sequence of bits generated by a host from which the first set of bits is received (“A signal processor comprising: a host computer; and a semiconductor memory detachably connected to the host computer, the semiconductor memory including a receiving unit that receives encrypted bit strings from the host computer, a key information generation unit that generates a plurality of key information items by variously modifying original data based on a predetermined rule, the original data being read from a memory that stores the original data being a source for the key information items, and a processing unit that generates decrypted bit strings by decrypting the encrypted bit strings received by the receiving unit, each encrypted bit string being decrypted with a different one of the plurality of key information items generated by the key information generation unit.” Tsukazaki: col. 22, lines 16-32)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Suzuki, Khatri and Stark with the teaching of Szczepaniak to meet the preceding limitations. One of ordinary skill in the art would have been motivated to make such modification since such techniques were known at the time of the instant invention and would have been applied to provide system data in a secure manner.
As per claim 14, this claim defines a method that corresponds to system of claim 7 and does not define beyond limitations of claim 7. Therefore, claim 14 is rejected with the same rational as the rejection of claim 7.
As per claim 20, this claim defines a computer-readable storage medium storing instructions corresponding to the system of claim 7 and does not define beyond limitations of claim 7. Therefore, claim 20 is rejected with the same rational as in the rejection of claim 5.
Conclusion
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/GHODRAT JAMSHIDI/Primary Examiner, Art Unit 2493