DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1, 2, 4, 5, 7, 9, 10,12, 13, 15, 17, and 21-24 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claims 1, 9, and 17 have been amended to include “responsive to determining that the host data was not programmed to one of the MLC memory or the TLC memory, identifying one or more single-level cell (SLC) memory units of the memory device to be programmed with the host data”. Paragraph 0037 teaches the most similar aspect in the specification: “The APL handling component 113 may identify a portion of memory device 130 and/or 140 to be programmed using SLC mode (e.g., SLC memory).” However, this fails to teach when the identification occurs. It is not inherent since the APL handling component could identify the portion as part of the manufacturing process and permanently reserve the portion for that purpose. Furthermore, the specification fails to disclose “memory units”. Claims 2, 4, 5, 7, 10,12, 13, 15, and 21-24 are rejected based on their dependence on claims 1, 9, or 17.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 2, 4, 5, 7, 9, 10,12, 13, 15, 17, and 21-24 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
It is unclear what meaning Applicant intended the phrase “memory units” to have. The specification does not use this phrase. This phrase can be used to mean a wide variety of different memory structures, from pages or sectors to packages and other things in between. It is unclear what meaning Applicant intends. Claims 2, 4, 5, 7, 10,12, 13, 15, and 21-24 are rejected based on their dependence on claims 1, 9, or 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al. (US 2023/0129097) in view of Wakchaure et al. (US 2017/0139626).
In regards to claims 1, 9, and 17, Gupta teaches a system comprising:
one or more memory devices (memory die 108, figure 1A); and
a processing device , operatively coupled to the one or more memory devices (controller 122, figure 1A), the processing device to perform operations comprising:
receiving host data to be programmed to one of a multi-level cell (MLC) memory of a memory device or a triple-level cell (TLC) memory of the memory device (“Commands and data are transferred between the host 140 and controller 122 via a data bus 120, and between the controller and the one or more memory die 108 via lines 118.”, paragraph 0062; “The flowchart 1400 shows and describes a process such that during a programming event to a NAND memory device, the inflight data is not lost.”, paragraph 0126; “Although programming is halted, the memory block (e.g., TLC or QLC block) that was being programming is not unselected.”, paragraph 0128));
responsive to determining that the memory device experienced an asynchronous power loss (APL) event (“In step 1402, the method begins with a power loss event and an identification thereof.”, paragraph 0127), determining whether the host data was programmed to one of the MLC memory or the TLC memory (“In step 1404, the programming is suspended. Although programming is halted, the memory block (e.g., TLC or QLC block) that was being programming is not unselected.”, paragraph 0128);
responsive to determining that the host data was not programmed to one of the MLC memory or the TLC memory, identifying one or more single-level cell (SLC) memory units of the memory device to be programmed with the host data (“In step 1408, the first erased page on the same block is selected.”, paragraph 0130; “In step 1412, the data is programmed to the same data block. The programming operation may be similar to that of storing latch data in SLC format.”, paragraph 0133);
programming the host data to the one or more SLC memory without performing a program verify operation (“In step 1410, the existing programming voltage is used to program the inflight data.”, paragraph 0131; “Additionally, the programming operation may occur without a verify operation.”, paragraph 0132; “In step 1412, the data is programmed to the same data block. The programming operation may be similar to that of storing latch data in SLC format.”, paragraph 0133);
responsive to powering on the memory device after the APL event (“In step 1414, when a power up event occurs (after the power loss event)”, paragraph 0134), performing a read operation on the one or more SLC memory to read the host data (“The data can be read from the current location”, paragraph 0134); and
programming the host data (“and programmed to the next word line(s)”, paragraph 0134).
Gupta fails to teach programming the host data to one of the MLC memory or the TLC memory. Wakchaure teaches programming the host data to one of the MLC memory or the TLC memory (“In examples disclosed herein, the memory that was written from the buffer 155 is re-written to a memory location that is operated in a multi-level mode (e.g., 2 bpc MLC mode, TLC mode, QLC mode, etc.).”, paragraph 0082) which “results in a greater data storage density” (paragraph 0082). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gupta with Wakchaure to include programming the host data to one of the MLC memory or the TLC memory which “results in a greater data storage density” (id.).
Claims 2, 4, 5, 7, 10, 12, 13, 15, and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al. (US 2023/0129097) in view of Wakchaure et al. (US 2017/0139626) and Meir et al. (US 2014/0317365).
In regards to claims 2, 10, and 21, Gupta in view of Wakchaure teaches claims 1, 9, and 17. Gupta in view of Wakchaure fails to teach that programming the host data to the one or more SLC memory comprises determining whether a read voltage associated with cells of each of the one or more SLC memory exceeds a target read voltage value. Meir teaches that programming the host data to the one or more SLC memory comprises determining whether a read voltage associated with cells of each of the one or more SLC memory exceeds a target read voltage value (“After executing the emergency command, the cell threshold voltages are distributed in the two programming levels shown in the bottom graph of the figure. This configuration enables recovering the LSB page using a read threshold 96.”, paragraph 0070) in order to minimize data loss or corruption (paragraph 0032). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gupta with Wakchaure and Meir such that programming the host data to the one or more SLC memory comprises determining whether a read voltage associated with cells of each of the one or more SLC memory exceeds a target read voltage value in order to minimize data loss or corruption (id.).
In regards to claims 4, 12, and 22, Gupta in view of Wakchaure teaches claims 1, 9, and 17. Gupta in view of Wakchaure fails to teach that programming the host data to the one or more SLC memory of the memory device comprises updating a program start voltage or a program step size prior to programming the host data. Meir teaches that programming the host data to the one or more SLC memory of the memory device comprises updating a program start voltage or a program step size prior to programming the host data (“In alternative embodiments, the R/W unit programs the memory cells to reach PV2* by applying a single large-magnitude pulse and without verification.”, paragraph 0074) which “increases the probability that the alternative programming will complete successfully before the power interruption” (paragraph 0074). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gupta with Wakchaure and Meir such that programming the host data to the one or more SLC memory of the memory device comprises updating a program start voltage or a program step size prior to programming the host data which “increases the probability that the alternative programming will complete successfully before the power interruption” (id.).
In regards to claims 5, 13, and 23, Meir further teaches that updating the program start voltage or the program step size prior to programming the host data is based on a predetermined number of programming pulses (“In alternative embodiments, the R/W unit programs the memory cells to reach PV2* by applying a single large-magnitude pulse and without verification.”, paragraph 0074).
In regards to claims 7, 15, and 24, Gupta in view of Wakchaure teaches claims 1, 9, and 17. Gupta in view of Wakchaure fails to teach that performing the read operation on the one or more SLC memory to read the host data includes adjusting, prior to the read operation, a pass voltage of the read operation to a predetermined value. Meir teaches that performing the read operation on the one or more SLC memory to read the host data includes adjusting, prior to the read operation, a pass voltage of the read operation to a predetermined value (“After power is resumed, the data is recovered, possibly with a high pass voltage (Vpass) in order to mitigate bit line blockage.”, paragraph 0074) “in order to mitigate bit line blockage” (paragraph 0074). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gupta with Wakchaure and Meir such that performing the read operation on the one or more SLC memory to read the host data includes adjusting, prior to the read operation, a pass voltage of the read operation to a predetermined value “in order to mitigate bit line blockage” (id.).
Response to Arguments
Applicant’s arguments, see pages 6-7, filed 24 July 2026, with respect to the objection and 112 rejection have been fully considered and are persuasive. The objection and 112 rejection have been withdrawn.
Applicant's arguments, see pages 7-10, filed 24 July 2026, with respect to the 103 rejection have been fully considered but they are not persuasive.
In response to the argument regarding SLC memory, the Examiner contends that, since Gupta teaches programming data “similar to that of storing latch data in SLC format” (paragraph 0133), one of ordinary skill in the art would understand Gupta as teaching programming the SLC memory. The claims do not limit the size or structure of the SLC memory. Therefore, any set of cells programmed in the SLC format could be considered the SLC memory.
In response to the argument regarding disabling program verify, the Examiner is not just relying on Gupta’s one-pulse programming. The Examiner finds Gupta’s teaching that “the programming operation may occur without a verify operation” (paragraph 0132) to be convincing that Gupta teaches disabling program verify and programming without program verify. The Examiner is relying on Wakchaure to teach aspects of the programming step that occurs after powering on after the APL event. The claims are silent as to whether program verify occurs for that programming step.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 9 September 2026
