DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
Notice of Claim Interpretation
Claims in this application are not interpreted under 35 U.S.C. 112(f) unless otherwise noted in an office action.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 22 December 2025 has been entered.
Claim Objections
Claims 1, 2, 4, 5, 7, 17, and 21-24 are objected to because of the following informalities: “the memory device” at line 3 of claim 1 and line 5 of claim 17 which lacks antecedent basis in the claim. Appropriate correction is required. Claims 2, 4, 5, 7, and 21-24 are objected to based on their dependence on either claim 1 or claim 17.
Claim 21 objected to because of the following informalities: there are two identical copies of claim 21 included. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 2, 4, 5, 7, 9, 10, 12, 13, 15, 17, and 21-24 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 9, and 17 includes the phrase “a memory device” on lines 11, 15, and 13 respectively. It is unclear whether this phrase is intended to refer to the previously introduced memory device or another memory device. Claims 2, 4, 5, 7, 10, 12, 13, 15, and 21-24 are rejected based on their dependence on one of claims 1, 9, or 17.
Claim 9 includes the phrase “one or more memory devices” and “the memory device”. It is unclear whether “the memory device” is referring to one of the “one or more memory devices” or another memory device. Claims 10, 12, 13, and 15 are rejected based on their dependence on claim 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al. (US 2023/0129097) in view of Wakchaure et al. (US 2017/0139626).
In regards to claims 1, 9, and 17, Gupta teaches a system comprising:
one or more memory devices (memory die 108, figure 1A); and
a processing device , operatively coupled to the one or more memory devices (controller 122, figure 1A), the processing device to perform operations comprising:
receiving host data (“Commands and data are transferred between the host 140 and controller 122 via a data bus 120, and between the controller and the one or more memory die 108 via lines 118.”, paragraph 0062);
responsive to determining that the memory device experienced an asynchronous power loss (APL) event (“In step 1402, the method begins with a power loss event and an identification thereof.”, paragraph 0127), determining whether the host data was programmed to one of a multi-level cell (MLC) memory of a memory device of the one or more memory devices or a triple-level cell (TLC) memory of the memory device (“In step 1404, the programming is suspended. Although programming is halted, the memory block (e.g., TLC or QLC block) that was being programming is not unselected.”, paragraph 0128);
responsive to determining that the host data was not programmed to one of the MLC memory or the TLC memory, disabling program verify (“In step 1410, the existing programming voltage is used to program the inflight data.”, paragraph 0131; “Additionally, the programming operation may occur without a verify operation.”, paragraph 0132);
programming host data to one or more single-level cell (SLC) memory of a memory device (“In step 1412, the data is programmed to the same data block. The programming operation may be similar to that of storing latch data in SLC format.”, paragraph 0133);
responsive to powering on the memory device after the APL event (“In step 1414, when a power up event occurs (after the power loss event)”, paragraph 0134), performing a read operation on the one or more SLC memory to read the host data (“The data can be read from the current location”, paragraph 0134); and
programming the host data (“and programmed to the next word line(s)”, paragraph 0134).
Gupta fails to teaches programming the host data to one of the MLC memory or the TLC memory. Wakchaure teaches programming the host data to one of the MLC memory or the TLC memory (“In examples disclosed herein, the memory that was written from the buffer 155 is re-written to a memory location that is operated in a multi-level mode (e.g., 2 bpc MLC mode, TLC mode, QLC mode, etc.).”, paragraph 0082) which “results in a greater data storage density” (paragraph 0082). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gupta with Wakchaure to include programming the host data to one of the MLC memory or the TLC memory which “results in a greater data storage density” (id.).
Claims 2, 4, 5, 7, 10, 12, 13, 15, and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al. (US 2023/0129097) in view of Wakchaure et al. (US 2017/0139626) and Meir et al. (US 2014/0317365).
In regards to claims 2, 10, and 21, Gupta in view of Wakchaure teaches claims 1, 9, and 17. Gupta in view of Wakchaure fails to teach that programming the host data to one or more SLC memory of the memory device comprises determining whether a read voltage associated with cells of each of the one or more SLC memory exceeds a target read voltage value. Meir teaches that programming the host data to one or more SLC memory of the memory device comprises determining whether a read voltage associated with cells of each of the one or more SLC memory exceeds a target read voltage value (“After executing the emergency command, the cell threshold voltages are distributed in the two programming levels shown in the bottom graph of the figure. This configuration enables recovering the LSB page using a read threshold 96.”, paragraph 0070) in order to minimize data loss or corruption (paragraph 0032). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gupta with Wakchaure and Meir such that programming the host data to one or more SLC memory of the memory device comprises determining whether a read voltage associated with cells of each of the one or more SLC memory exceeds a target read voltage value in order to minimize data loss or corruption (id.).
In regards to claims 4, 12, and 22, Gupta in view of Wakchaure teaches claims 1, 9, and 17. Gupta in view of Wakchaure fails to teach that programming the host data to one or more SLC memory of the memory device comprises updating a program start voltage or a program step size prior to programming the host data. Meir teaches that programming the host data to one or more SLC memory of the memory device comprises updating a program start voltage or a program step size prior to programming the host data (“In alternative embodiments, the R/W unit programs the memory cells to reach PV2* by applying a single large-magnitude pulse and without verification.”, paragraph 0074) which “increases the probability that the alternative programming will complete successfully before the power interruption” (paragraph 0074). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gupta with Wakchaure and Meir such that programming the host data to one or more SLC memory of the memory device comprises updating a program start voltage or a program step size prior to programming the host data which “increases the probability that the alternative programming will complete successfully before the power interruption” (id.).
In regards to claims 5, 13, and 23, Meir further teaches that updating the program start voltage or the program step size prior to programming the host data is based on a predetermined number of programming pulses (“In alternative embodiments, the R/W unit programs the memory cells to reach PV2* by applying a single large-magnitude pulse and without verification.”, paragraph 0074).
In regards to claims 7, 15, and 24, Gupta in view of Wakchaure teaches claims 1, 9, and 17. Gupta in view of Wakchaure fails to teach that performing the read operation on the one or more SLC memory to read the host data includes adjusting, prior to the read operation, a pass voltage of the read operation to a predetermined value. Meir teaches that performing the read operation on the one or more SLC memory to read the host data includes adjusting, prior to the read operation, a pass voltage of the read operation to a predetermined value (“After power is resumed, the data is recovered, possibly with a high pass voltage (Vpass) in order to mitigate bit line blockage.”, paragraph 0074) “in order to mitigate bit line blockage” (paragraph 0074). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Gupta with Wakchaure and Meir such that performing the read operation on the one or more SLC memory to read the host data includes adjusting, prior to the read operation, a pass voltage of the read operation to a predetermined value “in order to mitigate bit line blockage” (id.).
Response to Arguments
The Examiner disagrees with Applicant’s summary of examiner interview.
Applicant’s arguments, see page 8, filed 22 December 2025, with respect to the objection have been fully considered and are persuasive. The objection has been withdrawn.
Applicant's arguments, see pages 9 and 10, filed 22 December 2025, with respect to the obviousness rejections have been fully considered but they are not persuasive. The Examiner has explained above how Gupta teaches the majority of the bolded claim features. Applicant’s arguments with respect to claims 8, 16, and 20 are moot, since Applicant has cancelled those claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN SADLER whose telephone number is (571)270-7699. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/Nathan Sadler/Primary Examiner, Art Unit 2139 23 March 2026