Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4, 7, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi (US 20230128441 A1), in view of Ninomiya (US 11508711 B2), and Park (US 20200123045 A1).
Regarding independent claim 1, Tsutsumi teaches a three-dimensional memory device ([0003], "According to an aspect of the present disclosure, a three-dimensional memory device is provided…"), comprising: an alternating stack of insulating layers and electrically conductive layers that alternate along a vertical direction (Fig. 2, 32, 42; [0041], "In one embodiment, the alternating stack (32, 42) can include insulating layers 32 composed of the first material, and sacrificial material layers 42 composed of a second material different from that of insulating layers 32.", [0046], "The sacrificial material layers 42 are replaced with electrically conductive layers that function as gate electrodes."); memory openings vertically extending through the alternating stack (Fig. 4A, 49; [0055], "The memory openings 49 are formed through the insulating cap layer 70 and the entirety of the alternating stack (32, 42) in the memory array region 100."); memory opening fill structures located in the memory openings and comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel (Fig. 5, 47; [0060], "Each remaining portion of the sacrificial fill material that fills the memory openings 49 comprises a sacrificial memory opening fill material portion 47. "; Fig. 7B, 54; [0073], "Generally, a vertical stack of discrete silicon nitride memory elements 54 can be formed on surface segments of each sacrificial memory opening fill structure (47, 45)."); a dielectric material portion located adjacent to the alternating stack (Fig. 5, 65; [0053], "A retro-stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein."); and at least one semiconductor material portion underlying the dielectric material portion, having a same material composition as the semiconductor source layer (Fig. 5, 10; [0036], "The optional semiconductor material layer 10, if present, can be formed on the top surface of the substrate semiconductor layer 9 prior to, or after, formation of the at least one semiconductor device 700 by deposition of a single crystalline semiconductor material, for example, by selective epitaxy.").
However, Tsutsumi does not teach a semiconductor source layer comprising a polycrystalline doped semiconductor material, underlying a bottommost surface of the alternating stack, and contacting a bottom end of the vertical semiconductor channels; and and having a textured pattern including gaps having a respective gap width in a range from 5 nm to 500 nm.
However, in the same field of endeavor, Ninomiya teaches a semiconductor source layer comprising a polycrystalline doped semiconductor material, underlying a bottommost surface of the alternating stack, and contacting a bottom end of the vertical semiconductor channels (Fig. 23G, 218, 60; (Col. 57, Lines 27-30), "In one embodiment, the source layer 218 comprises a polycrystalline or microcrystalline doped semiconductor material having the same as or an opposite conductivity type than then vertical semiconductor channels 60."); and Park teaches and having a textured pattern including gaps having a respective gap width in a range from 5 nm to 500 nm ([0071], "In an implementation, an average maximum distance between a pair of adjacent bumps each having a height (h) of about 50 mn or more per about 5 μm length in vertical section of the nano-textured substrate may be, e.g., about 100 nm or more.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device of Tsutsumi with the source layer of Ninomiya so as to "provide electrical contact to each distal end of the vertical semiconductor channels", (Ninomiya, Col. 28, Lines 6-7), and with the textured pattern and gap width of Park so as to "have an average of 5 to 100, e.g., 5 to 50, bumps having a height (h) of about 50 nm or more per about 5 um length in vertical section", (Park, [0067]).
Regarding dependent claim 2, Tsutsumi, as previously modified by Ninomiya and Park, teaches the three-dimensional memory device of Claim 1. However, as previously combined, they do not teach wherein the semiconductor source layer contacts doped source layers located in the bottom ends of the vertical semiconductor channels.
However, Ninomiya further teaches wherein the semiconductor source layer contacts doped source layers located in the bottom ends of the vertical semiconductor channels (Fig. 23G, 218, 606; (Col. 31, Lines 43-47), "Each doped semiconductor material layer 218 functions as a source layer that electrically connects a respective set of source cap regions 606 to a respective source-connection pass-through via structures 8P2.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, and Park with the contacting of doped source layers of Ninomiya so as to "electrically connect a respective set of source cap regions to a respective source-connection pass-through via structures", (Ninomiya, Col. 31, Lines 43-47).
Regarding dependent claim 4, Tsutsumi, as previously modified by Ninomiya and Park, teaches the three-dimensional memory device of Claim 1. However, as previously combined, they do not teach wherein the at least one semiconductor material portion comprises an array of discrete semiconductor pillar structures arranged to provide the textured pattern.
However, Ninomiya further teaches wherein the at least one semiconductor material portion comprises an array of discrete semiconductor pillar structures arranged to provide the textured pattern (Fig. 6, 20; (Col. 17 Lines 26-29), "Each of the support pillar structures 20 comprises a semiconductor material portion (i.e., a vertical semiconductor channel 60 of the support pillar structure 20)…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, and Park with the semiconductor pillar array of Ninomiya so as to "mechanically support other elements", (Ninomiya, Col. 13, Lines 36-37).
Regarding dependent claim 7, Tsutsumi, as previously modified by Ninomiya and Park, teaches the three-dimensional memory device of claim 1. However, as previously combined, they do not teach further comprising a dielectric textured-pattern structure contacting a bottom surface of the dielectric material portion and protruding downward from the bottom surface of the dielectric material portion, wherein the at least one semiconductor material portion comprises an array of downward-protruding polycrystalline semiconductor portions that laterally surrounds the dielectric textured-pattern structure.
However, Ninomiya further teaches further comprising a dielectric textured-pattern structure contacting a bottom surface of the dielectric material portion and protruding downward from the bottom surface of the dielectric material portion (Fig. 23A, 50; (Col. 17, Lines 26-33), "Each of the support pillar structures 20 comprises...a dielectric layer stack (i.e., a memory film 50 of a support pillar structure 20)…"), wherein the at least one semiconductor material portion comprises an array of downward-protruding polycrystalline semiconductor portions that laterally surrounds the dielectric textured-pattern structure (Fig. 23G, 62, 60; (Col. 16, Lines 17-19), "Referring to FIG. 5D, the dielectric core layer 62L can be recessed selective to the material of the semiconductor channel layer 60L…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, and Park with the dielectric textured-pattern structure of Ninomiya so as "to fill any remaining portion of the memory cavity", (Ninomiya, Col. 16, Lines 9-10).
Regarding dependent claim 12, Tsutsumi, as previously modified by Ninomiya and Park, teaches the three-dimensional memory device of Claim 1. However, as previously combined, they do not teach further comprising a logic die bonded to a memory die comprising the three-dimensional memory device.
However, Ninomiya further teaches further comprising a logic die bonded to a memory die comprising the three-dimensional memory device (Fig. 16, 700, 1000; (Col. 21, Lines 55-59), "Referring to FIG. 15, a second semiconductor die can be provided, which can be a logic die 700 including various semiconductor devices 710. The semiconductor devices 710 includes a peripheral circuitry for operation of the three-dimensional memory arrays in the memory die 1000.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, and Park with the logic and memory dies of Ninomiya so as to "support operation of the three-dimensional array of memory elements", (Ninomiya, Col. 27, Lines 60-61).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi (US 20230128441 A1), in view of Ninomiya (US 11508711 B2), Park (US 20200123045 A1), and Zhang (US 20220302151 A1).
Regarding dependent claim 3, Tsutsumi, as previously modified by Ninomiya and Park, teaches the three-dimensional memory device of Claim 1. However, as previously combined, they do not teach wherein the at least one semiconductor material portion comprises a semiconductor material plate, and the textured pattern comprises an array of discrete openings in the semiconductor material plate.
However, in the same field of endeavor, Zhang teaches wherein the at least one semiconductor material portion comprises a semiconductor material plate, and the textured pattern comprises an array of discrete openings in the semiconductor material plate (Fig. 3P, 361, 363, 360; [0111], "As illustrated in FIG. 3P, a spacer 362 is formed from spacer layer 371 along the sidewalls of contact openings 363 and 361 to electrically separate doped semiconductor layer 360.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, and Park with the semiconductor material plate and discrete openings of Zhang "such that each opening becomes the location for growing an individual channel structure in the later process", (Zhang, [0083]).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi (US 20230128441 A1), in view of Ninomiya (US 11508711 B2), Park (US 20200123045 A1), and Chin (US 20190172966 A1).
Regarding dependent claim 5, Tsutsumi, as previously modified by Ninomiya and Park, teaches the three-dimensional memory device of Claim 4. However, as previously combined, they do not teach wherein the array of discrete semiconductor pillar structures comprises a two-dimensional periodic array of discrete semiconductor pillar structures each having a diameter in a range from 100 nm to 400 nm.
However, in the same field of endeavor, Chin teaches wherein the array of discrete semiconductor pillar structures comprises a two-dimensional periodic array of discrete semiconductor pillar structures each having a diameter in a range from 100 nm to 400 nm (Fig. 1A, 102; [0036], "In various exemplary embodiments, nanopillars 102 (for example, III-V nanopillars such as InGaAsP) may be formed on a top surface 110 of crystalline semiconductor substrate 100...In various exemplary embodiments, nanopillars 102 may have an average diameter of between about 50 nm and about 900 nm.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, and Park with the diameter range of Chin so as "to optimize the subsequent epitaxial growth", (Chin, [0034]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi (US 20230128441 A1), in view of Ninomiya (US 11508711 B2), Park (US 20200123045 A1), and Yang (US 20230069096 A1).
Regarding dependent claim 6, Tsutsumi, as previously modified by Ninomiya and Park, teaches the three-dimensional memory device of Claim 4. However, as previously combined, they do not teach wherein the array of discrete semiconductor pillar structures is also located on the semiconductor source layer to provide the textured pattern on the semiconductor source layer.
However, in the same field of endeavor, Yang teaches wherein the array of discrete semiconductor pillar structures is also located on the semiconductor source layer to provide the textured pattern on the semiconductor source layer (Fig. 19G, 1924; [0316], "...is doped to form a source/drain 1924.", (Pillars 1906 are in contact with source/drain 1924)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, and Park with the textured pattern on the source layer of Yang so as to "address the density limitation in planar memory cells", (Yang, [0004]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi (US 20230128441 A1), in view of Ninomiya (US 11508711 B2), Park (US 20200123045 A1), and Cui (US 11069410 B1).
Regarding dependent claim 8, Tsutsumi, as previously modified by Ninomiya and Park, teaches the three-dimensional memory device of Claim 7, and Ninomiya further teaches wherein the dielectric textured-pattern structure has a thickness in a range from 100 % to 1,000 % of a thickness of the semiconductor source layer (Fig. 23G, 218, 230; (Col. 30-31, Lines 65-3), "The thickness of the continuous doped semiconductor material layer 218L over a planar surface of the dielectric material portion 65 may be in a range from 50 nm to 600 nm, such as from 100 nm to 300 nm, although lesser and greater thicknesses can also be employed.", (Col. 32, Lines 55-60), "In one embodiment, the backside isolation dielectric layer 230 can include a dielectric material such as undoped silicate glass (e.g., silicon oxide) or a doped silicate glass, and can have a thickness in a range from 100 nm to 2,000 nm, such as from 200 nm to 1,000 nm, although lesser and greater thicknesses can also be employed."); and the gaps in the textured pattern comprise gaps between neighboring pairs of the downward-protruding polycrystalline semiconductor portions (Fig. 23A, 20, (The gaps are between each pillar)).
However, as previously combined, they do not teach and the dielectric textured-pattern structure comprises a two-dimensional periodic array of patterned dielectric material portions each having a lateral dimension in a range from 20 nm to 300 nm.
However, in the same field of endeavor, Cui teaches the dielectric textured-pattern structure comprises a two-dimensional periodic array of patterned dielectric material portions each having a lateral dimension in a range from 20 nm to 300 nm ((Col. 18-19, Lines 66-12), "...and second sacrificial pillar structures 443 that are formed in volumes in which dielectric pillar structures...The lateral dimension of each second sacrificial pillar structure 443 along the lengthwise direction of the second line trenches 449 may be in a range from 30 nm to 600 nm, such as from 60 nm to 300 nm, although lesser and greater lateral dimensions may also be employed.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, and Park with the lateral dimension range of Cui for "providing lateral electrical isolation", (Cui, Col. 19, Line 1).
Claim(s) 9 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi (US 20230128441 A1), in view of Ninomiya (US 11508711 B2), Park (US 20200123045 A1), and Breymesser (US 20170194148 A1).
Regarding dependent claim 9, Tsutsumi, as previously modified by Ninomiya and Park, teaches the three-dimensional memory device of Claim 1. However, as previously combined, they do not teach wherein the at least one semiconductor material portion comprises a semiconductor material plate, and the textured pattern comprises random cracks extending through the semiconductor material plate.
However, in the same field of endeavor, Breymesser teaches wherein the at least one semiconductor material portion comprises a semiconductor material plate (Fig. 2C, 102; [0053], "…structuring a semiconductor region 102 to form a structured surface…"), and the textured pattern comprises random cracks extending through the semiconductor material plate (Fig. 2C, 104; [0082], "...a plurality of protrusions and a plurality of recesses of the structured surface 104…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, and Park with the random cracks of Breymesser "for improving the semiconductor processing", (Breymesser, [0050]).
Regarding dependent claim 11, Tsutsumi, as previously modified by Ninomiya, Park, and Breymesser, teaches the three-dimensional memory device of Claim 9. However, as previously combined, they do not teach further comprising: additional random cracks extending through the semiconductor source layer; and a metallic source layer located on the semiconductor source layer and filling the additional random cracks.
However, Breymesser further teaches further comprising: additional random cracks extending through the semiconductor source layer; and a metallic source layer located on the semiconductor source layer and filling the additional random cracks (Fig. 18C, 1822, 304; [0215], "According to various embodiments, the semiconductor device 1800c may include a metallization layer 1822 formed over the semiconductor region, e.g. over the second structured surface 304 of the semiconductor region 102.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, Park, and Breymesser with the metallic source layer of Breymesser so that a "contact pad may be formed", (Breymesser, [0255]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsumi (US 20230128441 A1), in view of Ninomiya (US 11508711 B2), Park (US 20200123045 A1), Breymesser (US 20170194148 A1), and Davies (US 20090108392 A1).
Regarding dependent claim 10, Tsutsumi, as previously modified by Ninomiya, Park, and Breymesser, teaches the three-dimensional memory device of Claim 9, and Breymesser further teaches and at least 10 % of all random cracks are not connected to any other random crack among the random cracks (Fig. 2C, 104, (None are connected)).
However, as previously combined, they do not teach wherein: the random cracks are filled with a conductive metallic nitride material.
However, in the same field of endeavor, Davies teaches the random cracks are filled with a conductive metallic nitride material ([0137], "The nitride layer may fill in any cracks in the capping layer…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the three-dimensional memory device as described by the combination of Tsutsumi, Ninomiya, Park, and Breymesser with the metallic nitride material of Davies so as to "prevent the propagation of gases into voids", (Davies, [0137]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220051979 A1,.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY JAMES MATTABONI whose telephone number is (571)270-0766. The examiner can normally be reached Monday-Friday 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 5712707996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights