DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-7 and 15-20 in the reply filed on 2/17/2026 is acknowledged. The traversal is on the ground(s) that the claims are similar enough and would not be an additional examination burden. This is not found persuasive because the combination (claims 8-14) further includes details of a PICO line and an interconnect bus, and are not required in the subcombination. The subcombination includes details of a buffer coupled to the POCI line, which is not required in the combination.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 15, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morgensen (Patent #US 11341081 B1) in view of Van (pub # US 20190122007 A1).
Regarding claim 1, Morgensen discloses a device (system shown in figure 1A, details shown in figure 2A) comprising: a peripheral out, controller in (POCI) pin (MISO line 114); wherein the device is configured to: detect a write transaction (send/receive operation) for a header (command) that is addressed to a register (SPI host 102 send or receive data and commands to and from a particular SPI client 104; paragraph 14; data/command exchanged are stored in shift register paragraph 17; for example, register 204 shown in figure 2, paragraph 26).
Morgensen does not disclose explicitly storing the header in a buffer. However, Van discloses a buffer coupled to the POCI pin (storing commands in FIFO queue, paragraph 157), and cause the header to be written to the buffer in response to detecting the write transaction addressed to the register (commands associated with address space access the MMIO registers, paragraph 158). Furthermore, teachings of Morgensen and Van are from the same field of host-peripheral communications.
Therefore, it would have been obvious for a person of ordinary skill in the art before the effective filing date of the invention to combine teachings of Morgensen with Van by using a buffer to store data and commands exchanged between the SPI host and peripheral, for the benefit of temporarily storing data before they are ready for processing.
Regarding claim 4, the above combination discloses the device of claim 1, wherein to cause the header to be written to the buffer, the device is configured to cause an interface circuit to transfer the header from an interconnect bus (SPI interface 1048, figure 10) to the buffer (the device causes transfers across the SPI interface logic as shown in figure 10, Van).
Regarding claims 15 and 18, examiner notes that the claim is substantially similar to claims 1 and 4 above. The same grounds of rejection are applied.
Allowable Subject Matter
Claims 2, 3, 5-7, 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: prior art of record discloses a system including a master and a slave, and an interface (SPI) between the two devices. The SPI interface includes various pins, including clock, master-in slave out, master-out-slave-in, and chip select. Prior art of record further discloses a buffer system between the master and slave devices to temporarily store data and command (header). However, prior art of record does not teach or suggest, inter alia, using a chip select pin, or an interrupt pin to facilitate storing the header in a buffer for a write transaction addressed to a register.
Conclusion
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/SCOTT C SUN/Primary Examiner, Art Unit 2181