Prosecution Insights
Last updated: August 17, 2026
Application No. 18/768,916

LOW DISTORTION AMPLIFIER

Non-Final OA §102§103
Filed
Jul 10, 2024
Priority
Feb 25, 2022 — continuation of PCTJP2022008013
Examiner
RETEBO, METASEBIA T
Art Unit
Tech Center
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
589 granted / 659 resolved
+29.4% vs TC avg
Moderate +5% lift
Without
With
+5.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
29 currently pending
Career history
682
Total Applications
across all art units

Statute-Specific Performance

§101
1.8%
-38.2% vs TC avg
§103
48.1%
+8.1% vs TC avg
§102
30.9%
-9.1% vs TC avg
§112
13.5%
-26.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 659 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 7-8 and 10 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Sjoland et al. (US 2021/0314009 and Sjoland hereinafter) Regarding claim 1, Sjoland discloses a low distortion amplifier [fig. 1] comprising: a first signal source [source generating the input signal for 201] to output a first frequency signal and a second frequency signal [210], the second frequency being different from the first frequency; a second signal source [source generating the input signal for 211] to output the first frequency signal and the second frequency signal; a first amplifier [201] to receive the signal output from the first signal source and to amplify the input signa1; a second amplifier [202] to receive the signal output from the second signal source and to amplify the input signal; and a combiner [203] to combine the signal amplified by the first amplifier and the signal amplified by the second amplifier, wherein an operation is performed in an operation mode in which a phase difference between the first frequency signals input to the first amplifier and the second amplifier and a phase difference between the second frequency signals input to the first amplifier and the second amplifier satisfy a relational equation in which an intermodulation distortion component [par. 0020-0023] included in the signal amplified by the first amplifier and an intermodulation distortion component included in the signal amplified by the second amplifier are in opposite phases [par. 101-115]. Regarding claim 2, Sjoland discloses wherein in a case where n and m are integers, a phase difference between the first frequency signals is represented by ΔθF1, and a phase difference between the second frequency signals is represented by ΔθF2, the relational equations are ((n + 1)ΔθF2 - nΔθF1) =-+ 180 degrees and ((m + 1)ΔθF1 - mΔθF2) =+- 180 degrees [par. 68-70 and par. 101-115]. Regarding claim 3, Sjoland discloses wherein in a case where an order of a low-frequency intermodulation distortion is represented by YIML, an order of a high-frequency intermodulation distortion is represented by ZIMH, a phase difference between the first frequency signals is represented by ΔθF1, and a phase difference between the second frequency signals is represented by ΔθF2, the relational equations are (2 - (YIML - ZIMH))/YIML + ZIMH × +-180 degrees = ΔθF1 and (2 + (YIML - ZIMH))/YIML + ZIMH × -+180 degrees = ΔθF2 [par. 68-70 and 101-115]. Regarding claim 4, Sjoland discloses wherein in a case where a phase difference between the first frequency signals is represented by ΔθF1, a phase difference between the second frequency signals is represented by ΔθF2, and an order of an intermodulation distortion is XIM, the relational equations are +-180 degrees/XIM=ΔθF1 and -+180 degrees/XIM=ΔθF2 [par. 68-70 and 101-115]. Regarding claim 7, Sjoland discloses wherein each of the first signal source and the second signal source includes a signal source to generate the first frequency signal and a signal source to generate the second frequency signal, and the signal source to generate the first frequency signal and the signal source to generate the second frequency signal are digital-to-analog converters [par. 153 and 169]. Regarding claim 8, Sjoland discloses wherein the first signal source and the second signal source are digital-to-analog converters [par. 153 and 169]. Regarding claim 10, Sjoland discloses wherein the combiner emits a signal amplified by the first amplifier and a signal amplified by the second amplifier into space, and vector-combines these signals [par. 104-108]. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Sjoland et al in view of Cozzarelli (US 6359504). Regarding claim 5, Sjoland discloses all the features with respect to claim 1 as indicated above. Sjoland does not explicitly disclose wherein the first amplifier and the second amplifier are transistors having the same size. However, Cozzarelli discloses amplifiers employing field effect transistors [cl. 1, ln. 50-67]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the first amplifier and the second amplifier of Sjoland by incorporating transistors as taught in Cozzarelli in order to utilize known amplifier. Sjoland in view of Cozzarelli does not explicitly disclose transistors having the same size. However, selecting transistors of the same size is a mere design choice that would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to provide predictable and symmetrical amplifier behavior. The use of same sized transistors does not appear to produce any unexpected results and is a predictable and routine modification of known control techniques of amplifier. Regarding claim 6, Sjoland discloses all the features with respect to claim 1 as indicated above. Sjoland does not explicitly disclose wherein the first amplifier and the second amplifier are transistors under the same bias condition. However, Cozzarelli discloses amplifiers employing field effect transistors [cl. 1, ln. 50-67]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the first amplifier and the second amplifier of Sjoland by incorporating transistors as taught in Cozzarelli in order to utilize known amplifier. Sjoland in view of Cozzarelli does not explicitly disclose transistors under the same bias condition. However, selecting transistors of the same bias condition is a mere design choice that would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to provide predictable and symmetrical amplifier behavior. The use of same transistors same bias condition does not appear to produce any unexpected results and is a predictable and routine modification of known control techniques of amplifier. Allowable Subject Matter Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 9, the closest prior art Sjoland et al does not disclose a distortion compensation circuit to add, to a signal generated by the first signal source and input to the first amplifier and a signal generated by the second signal source and input to the second amplifier, signal information compensating for distortions generated in the signals. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Takei et al. (US 20020089373 A1), MATSUURA (JP 2002171136 A), OKAJIMA (JP 2006186838 A), Yamanouchi et al. (US 7821337) and Liao (US 10917128) are cited to teach Low distortion power amplifier. Any inquiry concerning this communication or earlier communications from the examiner should be directed to METASEBIA T RETEBO whose telephone number is (571)272-9299. The examiner can normally be reached M - F 8:30 - 5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /METASEBIA T RETEBO/ Primary Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Jul 10, 2024
Application Filed
Aug 04, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
95%
With Interview (+5.3%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 659 resolved cases by this examiner. Grant probability derived from career allowance rate.

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