DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) filed on July 10th, 2024, is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Reference #235. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The abstract is objected to for failing to be in narrative form. Applicant is reminded of the proper language and format for an abstract of the disclosure: The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
(a) [0007], “… and wherein the second semiconductor chip is configured to receive power through the plurality of third through-electrodes of the at least one third semiconductor chip.[[.]]”;
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 4, 5, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li, et al. (US 2024/0105688 A1; hereinafter referred to as Li) and further in view of Kim, et al. (US 2020/0135683 A1; hereinafter referred to as Kim) and further in view of Chen, et al. (US 2020/0411445 A1; hereinafter referred to as Chen).
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Regarding Claim 1, Li discloses a semiconductor package (package 100, [0069], Fig. 5), comprising:
a first semiconductor chip (integrated device 107, [0075], Fig. 5) comprising a first integrated circuit on a first front surface ([0108], Fig. 5), a plurality of first rear pads on a first rear surface opposite to the first front surface (solder interconnects 170, [0077], Fig. 5), the plurality of first rear pads comprising a first group of first rear pads and a second group of first rear pads (see Annotated Fig. 5);
a second semiconductor chip (chiplet 103, [0075], Fig. 5) comprising a second integrated circuit on a second front surface facing the first rear surface of the first semiconductor chip (active region 132, [0034, 0108], Fig. 5), a plurality of first front pads electrically connected to the second integrated circuit and in contact with the first group of first rear pads (die interconnects 136, see Annotated Fig. 5), a plurality of second rear pads on a second rear surface opposite to the second front surface (die interconnects 136, [0034], Fig. 5), and a plurality of second through-electrodes electrically connecting the second integrated circuit and the plurality of second rear pads (through substrate vias 131, [0034], Fig. 5, “The plurality of through substrate vias 131 may be coupled to the plurality of die interconnects 136. The plurality of through substrate vias 131 may be coupled to the active region 132”);
a first sealing layer on a side surface of the second semiconductor chip (encapsulation layer 108, [0032], Fig. 5);
at least one third semiconductor chip (chiplet 101, [0075], Fig. 5) comprising a third integrated circuit on a third front surface facing the second rear surface of the second semiconductor chip (active region, [0035], Fig. 5), a plurality of second front pads electrically connected to the third integrated circuit and in contact with the plurality of second rear pads (die interconnects 136, [0035], Fig. 5), a plurality of third rear pads on a third rear surface opposite to the third front surface (solder interconnects 110, [0031, 0044], Fig. 5), and a plurality of third through-electrodes electrically connecting the third integrated circuit and the plurality of third rear pads (through substrate vias 131, [0035], Fig. 5);
a plurality of first through-vias penetrating through the first sealing layer and electrically connected to the second group of first rear pads (encapsulation interconnects 182, [0075], Fig. 5); and
a plurality of connection bumps electrically connected to the plurality of third rear pads and the plurality of second through-vias (solder interconnects 129, [0031], Fig. 5),
Li’s embodiment as disclosed in Figure 5 fails to explicitly disclose a first sealing surface on the second front surface of the second semiconductor chip, a second sealing layer on the third rear surface and a side surface of the at least one third semiconductor chip, a plurality of second through-vias penetrating through the second sealing layer, electrically connected to the plurality of first through-vias, and a plurality of connection bumps on the second sealing layer.
However, as further disclosed in Li (e.g., the embodiment disclosed in Figure 4), Li discloses a first sealing surface on the second front surface of the second semiconductor chip (encapsulation layer 408, Fig. 4);
a second sealing layer on the third rear surface and a side surface of the at least one third semiconductor chip (encapsulation layer 108, Fig. 4);
a plurality of second through-vias penetrating through the second sealing layer (encapsulation interconnects 182, Fig. 4) electrically connected to the plurality of first through-vias (encapsulation interconnects 490, Fig. 4);
a plurality of connection bumps on the second sealing layer (solder interconnects 129, Fig. 4)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the structure of the package of the embodiment of Figure 5 of Li with the changes as disclosed in the embodiment of Figure 4 of Li. One would be motivated to do so as the disclosed embodiment of Figure 4 provides improved efficiency in electrical paths as the introduction of a second sealing layer further isolates the stacked chips from one another to improve performance.
Li, in its totality, fails to disclose a first semiconductor chip with a plurality of first through-electrodes electrically connecting the first integrated circuit and the plurality of first rear pads, the plurality of second through-vias having a shape tapered toward the plurality of first through-vias, and wherein a maximum diameter of the plurality of second through-vias is greater than a maximum diameter of the plurality of first through-vias in a horizontal direction.
However, in analogous art, Kim discloses a first semiconductor chip (Kim: semiconductor chip 120, [0024], Fig. 1) with a plurality of first through-electrodes (Kim: through vias 125, [0024], Fig. 1) electrically connecting the first integrated circuit (Kim: element region AR, [0025], Fig. 1) and the plurality of first rear pads (Kim: wiring layer 122, [0024], Fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first semiconductor chip of Li such that it had a plurality of through-electrodes contained within, as disclosed by Kim. One would be motivated to do so as a way of providing electrical connection to the active region of the chip by doing so within the chip itself, and, therefore, reducing the size of the package (Kim: [0003]).
The combination of Li and Kim fails to disclose the plurality of second through-vias having a shape tapered toward the plurality of first through-vias, and wherein a maximum diameter of the plurality of second through-vias is greater than a maximum diameter of the plurality of first through-vias in a horizontal direction.
However, in analogous art, Chen discloses the plurality of second through-vias (Chen: through vias 310, [0040]) having a shape tapered toward the plurality of first through-vias (Chen: Fig. 2); and
wherein a maximum diameter of the plurality of second through-vias is greater than a maximum diameter of the plurality of first through-vias in a horizontal direction (Chen: [0040], Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the through vias of Li/Kim such that the second through vias have a tapered shape toward the first through-vias and the second through-vias have a greater maximum diameter than the first through-vias, as disclosed by Chen. One would be motivated to do so as this structure reduces packaging size and improves integration density, which leads to increased bandwidth (Chen: [0003]).
Regarding Claim 2, Li/Kim/Chen discloses the semiconductor package of claim 1, wherein the plurality of first through-vias comprises:
a first pad portion in contact with the plurality of second through-vias (Li: metallization interconnects 142, Fig. 4);
a second pad portion in contact with the second group of first rear pads (Li: die interconnects 136, Fig. 5); and
a via portion connecting the first pad portion and the second pad portion (Li: pillar interconnect 490, Fig. 4).
Regarding Claim 4, Li/Kim/Chen discloses the semiconductor package of claim 1, wherein the plurality of second through-vias comprise:
a via portion in the second sealing layer (Li: encapsulation interconnects 182, Fig. 4); and
a pad portion extending in the horizontal direction from the via portion and in contact with the plurality of connection bumps (Li: die interconnects 136, Fig. 4).
Regarding Claim 5, Li/Kim/Chen discloses the semiconductor package of claim 1, wherein the plurality of first front pads comprise:
a base portion connected to the second integrated circuit (Li: die interconnects 136, Fig. 5); and
a bonding portion between the base portion and the first group of first rear pads (Li: solder interconnects 190, Fig. 5), and
wherein a height of the bonding portion is greater than a height of the base portion in a vertical direction (Li: Fig. 5).
Regarding Claim 13, Li/Kim/Chen discloses the semiconductor package of claim 1, further comprising:
a redistribution structure (Li: metallization portion 106, [0111], Fig. 4) comprising an insulating material layer on the plurality of third rear pads and the plurality of second through-vias on the second sealing layer (Li: dielectric layer 160, [0111], Fig. 4); and
a redistribution pattern layer in the insulating material layer and electrically connecting the plurality of third rear pads and the plurality of second through-vias to the plurality of connection bumps (Li: metallization interconnects 162, [0111], Fig. 4).
Regarding Claim 14, Li/Kim/Chen discloses the semiconductor package of claim 1, further comprising:
under bump structures between the plurality of third rear pads and the plurality of connection bumps (Li: interconnects 122, [0031], Fig. 5); and
a protective layer on the under bump structures, the plurality of second through-vias, and at least a portion of each of the plurality of connection bumps (Li: see Annotated Fig. 5).
Claim(s) 3 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li/Kim/Chen as applied to claims 1, 2, 4, 5, 13, and 14 above, and further in view of Kim, et al. (US 2013/0069239 A1; hereinafter referred to as Kim239).
Regarding Claim 3, Li/Kim/Chen discloses the semiconductor package of claim 2, wherein the first sealing layer comprises:
a gap-fill portion on the side surface of the second semiconductor chip and a first portion of a side surface of each of the plurality of first front pads (Li: Fig. 4); and
a passivation portion on a second portion of the side surface of each of the plurality of first front pads on the gap-fill portion,
wherein the gap-fill portion is on a side surface of the first pad portion and a side surface of the via portion (Li: Fig. 4), and
wherein the passivation portion is on a side surface of the second pad portion.
The combination of Li/Kim/Chen fails to explicitly disclose the first sealing layer comprising a passivation portion on a second portion of the side surface of each of the plurality of first front pads on the gap-fill portion, and wherein the passivation portion is on a side surface of the second pad portion.
However, in analogous art, Kim239 discloses a sealing layer comprising a passivation portion of the second portion of the side surface of each of the plurality of first front pads on the gap-fill portion (Kim239: passivation layer 182, [0068], Fig. 7); and
wherein the passivation portion is on a side surface of the second pad portion (Kim239: Fig. 7).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the sealing layer of Li/Kim/Chen such that there was a passivation layer, as disclosed by Kim239. One would be motivated to use a passivation layer in the sealing layer to further increase the electrical insulating properties of the sealing layer when in contact with the bonding pads.
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Regarding Claim 6, Li/Kim/Chen discloses the semiconductor package of claim 5, wherein the first sealing layer comprises:
a gap-fill portion on the side surface of the second semiconductor chip and a first portion of a side surface of each of the plurality of first front pads (Li: Annotated Fig. 4); and
wherein the first portion comprises a side surface of the base portion and a portion of a side surface of the bonding portion (Li: Annotated Fig. 4), and
The combination of Li/Kim/Chen fails to explicitly disclose a passivation portion on a second portion of the side surface of each of the plurality of first front pads on the gap-fill portion, wherein the second portion comprises a remaining portion of the side surface of the bonding portion.
However, in analogous art, Kim239 discloses a passivation portion on a second portion of the side surface of each of the plurality of first front pads on the gap-fill portion (Kim239: passivation layer 182, [0058], Fig. 7);
wherein the second portion comprises a remaining portion of the side surface of the bonding portion (Kim239: [0058], Fig. 7).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the sealing layer of Li/Kim/Chen such that there was a passivation layer, as disclosed by Kim239. One would be motivated to use a passivation layer in the sealing layer to further increase the electrical insulating properties of the sealing layer when in contact with the bonding pads.
Claim(s) 7-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li/Kim/Chen as applied to claims 1, 2, 4, 5, 13, and 14 above, and further in view of Lee, et al. (US 2022/0139880 A1; hereinafter referred to as Lee).
Regarding Claim 7, Li/Kim/Chen discloses the semiconductor package of claim 1.
However, the combination of Li/Kim/Chen fails to explicitly disclose wherein the plurality of first through-electrodes comprise: a first group of first through-electrodes connected to the first group of first rear pads; and a second group of first through-electrodes connected to the second group of first rear pads, wherein the first group of first through-electrodes is configured to transmit input/output signals of the first integrated circuit, and wherein the second group of first through-electrodes is configured to transmit a power signal and a ground signal of the first integrated circuit.
However, in analogous art, Lee discloses a package wherein the plurality of first through-electrodes (Lee: through-vias 241, 242, Fig. 1B) comprise:
a first group of first through-electrodes connected to the first group of first rear pads (Lee: through-via 241, Fig. 1B); and
a second group of first through-electrodes connected to the second group of first rear pads (Lee: through-via 242, Fig. 1B),
wherein the first group of first through-electrodes is configured to transmit input/output signals of the first integrated circuit (Lee: [0039], Fig. 1B), and
wherein the second group of first through-electrodes is configured to transmit a power signal and a ground signal of the first integrated circuit (Lee: [0039], Fig. 1B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first through-electrodes such that they either transmit input/output or a power/ground signal, as disclosed by Lee. One would be motivated to structure the through-vias in such a way so as to minimize occupied area while increasing power/signal delivery efficiency, which increases device performance (Lee: [0003]).
Regarding Claim 8, Li/Kim/Chen discloses the semiconductor package of claim 1.
The combination of Li/Kim/Chen fails to explicitly disclose wherein the plurality of second through-electrodes comprise a first group of second through-electrodes and a second group of second through-electrodes, wherein the first group of second through-electrodes is configured to transmit input/output signals of the second integrated circuit, and wherein the second group of second through-electrodes is configured to transmit a power signal and a ground signal of the second integrated circuit.
However, in analogous art, Lee discloses wherein the plurality of second through-electrodes (first through vias 141 and 142, [0023], Fig. 1B) comprise a first group of second through-electrodes (first through vias 142, Fig. 1B) and a second group of second through-electrodes (first through vias 141, Fig. 1B),
wherein the first group of second through-electrodes is configured to transmit input/output signals of the second integrated circuit ([0023], Fig. 1B), and
wherein the second group of second through-electrodes is configured to transmit a power signal and a ground signal of the second integrated circuit ([0023], Fig. 1B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first through-electrodes such that they either transmit input/output or a power/ground signal, as disclosed by Lee. One would be motivated to structure the through-vias in such a way so as to minimize occupied area while increasing power/signal delivery efficiency, which increases device performance (Lee: [0003]).
Regarding Claim 9, Li/Kim/Chen/Lee discloses the semiconductor package of claim 8, further comprising:
a fourth semiconductor chip on the second rear surface of the second semiconductor chip (Li: chiplet 105, Fig. 5) and comprising power through-electrodes connected to the second group of second through-electrodes (Li: through substrate via 131, Fig. 5).
Regarding Claim 10, Li/Kim/Chen/Lee discloses the semiconductor package of claim 9, wherein a maximum diameter of the power through-electrodes is greater than a maximum diameter of the plurality of first through-electrodes, a maximum diameter of the plurality of second through-electrodes, and a maximum diameter of the plurality of third through-electrodes in the horizontal direction (Lee: [0029], Fig. 1B).
Regarding Claim 11, Li/Kim/Chen/Lee discloses the semiconductor package of claim 8, further comprising:
a fifth semiconductor chip comprising a plurality of front pads in contact with a first group of second rear pads connected to the first group of second through-electrodes among the plurality of second rear pads (Li: chiplet 105, Fig. 5),
wherein the second sealing layer is between a rear surface of the fifth semiconductor chip and the plurality of connection bumps (Li: Fig. 5).
Regarding Claim 12, Li/Kim/Chen discloses the semiconductor package of claim 1.
The combination of Li/Kim/Chen fails to explicitly disclose wherein the plurality of third through-electrodes comprises a first group of third through-electrodes and a second group of third through-electrodes, wherein the first group of third through-electrodes is configured to transmit input/output signals of the third integrated circuit, and wherein the second group of third through-electrodes is configured to transmit a power signal and a ground signal of the third integrated circuit.
However, in analogous art, Lee discloses the plurality of third through-electrodes comprises a first group of third through-electrodes and a second group of third through-electrodes (first through vias 141 and 142, [0029], Fig. 1B),
wherein the first group of third through-electrodes is configured to transmit input/output signals of the third integrated circuit (first through via 142, [0029], Fig. 1B), and
wherein the second group of third through-electrodes is configured to transmit a power signal and a ground signal of the third integrated circuit (first through via 141, [0029], Fig. 1B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first through-electrodes such that they either transmit input/output or a power/ground signal, as disclosed by Lee. One would be motivated to structure the through-vias in such a way so as to minimize occupied area while increasing power/signal delivery efficiency, which increases device performance (Lee: [0003]).
Claim(s) 15, 17, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li and further in view of Lee, et al. (US 2021/0358875 A1; hereinafter referred to as Lee875), further in view of Kim, et al. (US 2020/0135683 A1; hereinafter referred to as Kim), and further in view of Khan, et al. (US 2017/0117251 A1; hereinafter referred to as Khan).
Regarding Claim 15, Li discloses a semiconductor package, comprising:
a first semiconductor chip (integrated device 107, [0075], Fig. 5) comprising a first substrate having a first front surface and a first rear surface opposite to each other ([0108], Fig. 5), a plurality of first rear pads on the first rear surface (solder interconnects 170, [0077], Fig. 5;
a second semiconductor chip (chiplet 103, [0075], Fig. 5) comprising a second substrate having a second front surface and a second rear surface opposite to each other (active region 132, [0034, 0108], Fig. 5), a plurality of first front pads on the second front surface and in contact with the plurality of first rear pads (die interconnects 136, see Annotated Fig. 5), a plurality of second rear pads on the second rear surface (die interconnects 136, [0034], Fig. 5), and a plurality of second through-electrodes penetrating through the second substrate and electrically connected to the plurality of second rear pads (through substrate vias 131, [0034], Fig. 5, “The plurality of through substrate vias 131 may be coupled to the plurality of die interconnects 136. The plurality of through substrate vias 131 may be coupled to the active region 132”);
a first sealing layer (encapsulation layer 108, [0032], Fig. 5) comprising a gap-fill portion on a side surface of the second semiconductor chip and at least a portion of each of the plurality of first front pads (see Annotated Fig. 5);
at least one third semiconductor chip (chiplet 101, [0075], Fig. 5) comprising a third substrate having a third front surface and a third rear surface opposite to each other (active region, [0035], Fig. 5), a plurality of second front pads on the third front surface and in contact with the plurality of second rear pads (die interconnects 136, [0035], Fig. 5), a plurality of third rear pads on the third rear surface (solder interconnects 110, [0031, 0044], Fig. 5), and a plurality of third through-electrodes penetrating through the third substrate and electrically connected to the plurality of third rear pads (through substrate vias 131, [0035], Fig. 5);
a plurality of first through-vias penetrating through the first sealing layer and electrically connected to at least some of the plurality of first rear pads (encapsulation interconnects 182, [0075], Fig. 5);
a plurality of connection bumps on the plurality of third rear pads (solder interconnects 129, [0031], Fig. 5),
Li’s embodiment as disclosed in Figure 5 fails to explicitly disclose a second sealing layer on a side surface of the at least one third semiconductor chip, and on at least a portion of each of the plurality of third rear pads, a plurality of second through-vias penetrating through the second sealing layer and electrically connected to the plurality of first through-vias; and a plurality of connection bumps on the plurality of second through-vias.
However, as further disclosed in Li (e.g., the embodiment disclosed in Figure 4), Li discloses a second sealing layer on a side surface of the at least one third semiconductor chip, and on at least a portion of each of the plurality of third rear pads (encapsulation layer 408 is the first sealing layer, and encapsulation layer 108 is the second sealing layer, Fig. 4);
a plurality of second through-vias penetrating through the second sealing layer and electrically connected to the plurality of first through-vias (encapsulation interconnects 182, Fig. 4); and
a plurality of connection bumps on the plurality of second through-vias (solder interconnects 129, Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the structure of the package of the embodiment of Figure 5 of Li with the changes as disclosed in the embodiment of Figure 4 of Li. One would be motivated to do so as the disclosed embodiment of Figure 4 provides improved efficiency in electrical paths as the introduction of a second sealing layer further isolates the stacked chips from one another to improve performance.
Li, in its totality, fails to disclose a first passivation layer on at least a portion of each of the plurality of first rear pads, and a plurality of first through-electrodes penetrating through the first substrate and electrically connected to the plurality of first rear pads, a second passivation layer on at least a portion of each of the plurality of second rear pads, a passivation portion on the gap-fill portion and in contact with the first passivation layer, a third passivation layer on at least a portion of each of the plurality of second front pads and in contact with the second passivation layer, and wherein a material of the first sealing layer is different from a material of the second sealing layer.
However, in analogous art, Lee875 discloses a first passivation layer on at least a portion of the plurality of first rear pads (Lee875: second bond insulation layer BO2, [0036], Fig. 1);
a second passivation layer on at least a portion of the plurality of second rear pads (Lee875: first bond insulation layer BO1, [0036], Fig. 1);
a passivation portion on the gap-fill portion and in contact with the first passivation layer (Lee875: first chip insulation layer 143A, [0044], Fig. 1); and
a third passivation layer on at least a portion of each of the plurality of second front pads and in contact with the second passivation layer (Lee875: second chip insulation layer 143B, [0044], Fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the chip structures of Li such that passivation layers were introduced, as disclosed by Lee875. One would be motivated to do so in order to stack the chips in a vertical direction to reduce the layout area of the package while maintaining electrical insulative properties between chips, as passivation layers reduce parasitic interference (Lee875: [0003]).
The combination of Li/Lee875 fails to explicitly disclose a plurality of first through-electrodes penetrating through the first substrate and electrically connected to the plurality of first rear pads.
However, in analogous art, Kim discloses a first semiconductor chip (Kim: semiconductor chip 120, [0024], Fig. 1) with a plurality of first through-electrodes (Kim: through vias 125, [0024], Fig. 1) electrically connecting the first integrated circuit (Kim: element region AR, [0025], Fig. 1) and the plurality of first rear pads (Kim: wiring layer 122, [0024], Fig. 1).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first semiconductor chip of Li/Lee875 such that it had a plurality of through-electrodes contained within, as disclosed by Kim. One would be motivated to do so as a way of providing electrical connection to the active region of the chip by doing so within the chip itself, and, therefore, reducing the size of the package (Kim: [0003]).
The combination of Li/Lee875/Kim fails to explicitly disclose wherein a material of the first sealing layer is different from a material of the second sealing layer.
However, in analogous art, Khan discloses an analogous structure, wherein a material of the first sealing layer is different from a material of the second sealing layer (Khan: [0037], “The encapsulating material 125 can also be substantially different in type, filler particle material, and properties from encapsulating material 115”).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the material of the first and second sealing layer such that they are different materials. One would be motivated to do so to achieve the desired package electrical, thermal, and mechanical properties that improve IC die and package performance, reliability, and manufacturability (Khan: [0037]).
Regarding Claim 17, Li/Lee875/Kim/Khan discloses the semiconductor package of claim 15, wherein the plurality of first through-vias comprises a first pad portion in the gap-fill portion (Li: metallization interconnects 142, Fig. 4), a second pad portion in the passivation portion (Li: die interconnects 136, Fig. 5), and a first via portion extending in a vertical direction within the gap-fill portion and connecting the first pad portion and the second pad portion (Li: pillar interconnect 490, Fig. 4), and
wherein the plurality of second through-vias comprises a third pad portion on one surface of the second sealing layer opposite to the first pad portion (Li: die interconnects 136, Fig. 4), and a second via portion extending in the vertical direction within the second sealing layer and connecting the third pad portion and the first pad portion (Li: encapsulation interconnects 182, Fig. 4).
Regarding Claim 18, Li/Lee875/Kim/Khan discloses the semiconductor package of claim 15, wherein a first planar area of the first semiconductor chip is greater than a second planar area of the second semiconductor chip (Li: Fig. 5), and
wherein the second planar area of the second semiconductor chip is greater than a third planar area of the at least one third semiconductor chip (Li: Fig. 5).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li/Lee875/Kim/ Khan as applied to claims 15, 17, and 18 above, and further in view of Yang, et al. (US 2023/0170327 A1; hereinafter referred to as Yang).
Regarding Claim 16, Li/Lee875/Kim/Khan discloses the semiconductor package of claim 15,
wherein the second sealing layer comprises a polymer resin (Li: [0114]).
The combination of Li/Lee875/Kim/Khan fails to disclose wherein the first sealing layer comprises at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon carbonitride (SiCN).
However, in analogous art, Yang discloses wherein the first sealing layer comprises at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon carbonitride (SiCN) (Yang: [0099]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the first sealing layer such that it contained SiO, SiN, or SiCN as disclosed by Yang. One would be motivated to use said organic materials as they allow for easier manufacturing of subsequent processes (Yang: [0099]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li and further in view of Lee.
Regarding Claim 19, Li discloses a semiconductor package (package 500, [0075], Fig. 5), comprising:
a first semiconductor chip (integrated device 109, [0075], Fig. 5) comprising a plurality of first rear pads (solder interconnects 190, [0077], Fig. 5);
a second semiconductor chip (chiplet 103, [0075], Fig. 5) comprising a plurality of first front pads in contact with the plurality of first rear pads (die interconnects 136, Fig. 5), a plurality of second rear pads (die interconnects 136, Fig. 5), and a plurality of second through-electrodes electrically connected to the plurality of second rear pads (through substrate vias 131, [0034], Fig. 5);
at least one third semiconductor chip (chiplet 101, [0075], Fig. 5) comprising a plurality of second front pads in contact with the plurality of second rear pads (die interconnects 136, Fig. 5), a plurality of third rear pads (solder interconnects 110, Fig. 5), and a plurality of third through-electrodes electrically connected to the plurality of third rear pads (through substrate vias 131, [0034], Fig. 5);
a plurality of first through-vias on at least one side of the second semiconductor chip and electrically connected to at least some of the plurality of first rear pads (encapsulation interconnects 182, Fig. 5);
a plurality of connection bumps on the plurality of third rear pads (solder interconnects 129, Fig. 5),
Li, through the embodiment disclosed in Figure 5, fails to disclose a plurality of second through-vias on at least one side of the at least one third semiconductor chip and electrically connected to the plurality of first through-vias, and the plurality of connection bumps being on the plurality of second through vias.
However, Li, through the embodiment disclosed in Figure 4, does disclose a plurality of second through vias on at least one side of the at least one third semiconductor chip and electrically connected to the plurality of first through-vias (pillar interconnects 490 act as the first through vias and encapsulation interconnects 182 act as the second through vias, Fig. 4); and
the plurality of connection bumps on the plurality of second through vias (Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the through via structures such that there were two separate through vias. One would be motivated to do so because this allows for increased control of the size/dimensions of the through vias which can lead to increased device performance.
Li, in its totality, fails to disclose a plurality of first through-electrodes electrically connected to the plurality of first rear pads, wherein the first semiconductor chip is configured to receive power through the plurality of first through-vias and the plurality of second through-vias, and wherein the second semiconductor chip is configured to receive power through the plurality of third through-electrodes of the at least one third semiconductor chip.
However, in analogous art, Lee discloses a plurality of first through-electrodes electrically connected to the plurality of first rear pads (Lee: second through vias 241 and 242, [0031], Fig. 1B);
wherein the first semiconductor chip is configured to receive power through the plurality of first through-vias and the plurality of second through-vias (Lee: [0034], Fig. 1B), and
wherein the second semiconductor chip is configured to receive power through the plurality of third through-electrodes of the at least one third semiconductor chip (Lee: [0034], Fig. 1B).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the device of Li such that the first chip had a plurality of first through-electrodes, that the firsts chip was configured to receive power through the first through-vias, and the second chip was configured to receive power through the plurality of third through-electrodes. One would be motivated to do so because said structure leads to a reduction in voltage drop, switching time, and occupied area (Lee: [0004]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li/Lee as applied to claim 19 above, and further in view of Chen.
Regarding Claim 20, Li/Lee discloses the semiconductor package of claim 19,
wherein a third maximum diameter of the plurality of third through-electrodes is less than or equal the first maximum diameter of the plurality of first through-vias in the horizontal direction (Lee: [0037]).
The combination of Li/Lee fails to explicitly disclose wherein a first maximum diameter of the plurality of first through-vias is less than a second maximum diameter of the plurality of second through-vias in a horizontal direction.
However, in analogous art, Chen discloses wherein a first maximum diameter of the plurality of first through-vias is less than a second maximum diameter of the plurality of second through-vias in a horizontal direction (Chen: [0040], Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the through vias of Li/Lee such that the second through vias have a greater maximum diameter than the first through-vias, as disclosed by Chen. One would be motivated to do so as this structure reduces packaging size and improves integration density, which leads to increased bandwidth and device performance (Chen: [0003]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Hwang, et al. (US 2023/0154894 A1); discloses an analogous integrated circuit structure
(b) Suk, et al. (KR 20230025587 A); discloses an analogous IC structure with passivation layers
(c) Li, et al. (US 2024/0429141 A1); discloses a packaging structure with sidewall interconnects for power routing
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/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
