3Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 6-9, 12, 14-15, 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20210343822 A1) hereinafter referred to as "Jeon" in view of Jo (US 20230200194 A1) .
Regarding claim 1, Jeon discloses a substrate (Fig. 4L, element 10; ¶: [0073]) but does not disclose a display area where an image is displayed, the display area including a first area and a second area outside the first area, the first area including a first transmission area.
Jo discloses display area (Fig. 1, element DA; ¶: [0039]) where an image is displayed, the display area including a first area (Fig. 3, element EA2; ¶: [0059]) and a second area (Fig. 3, element EA1; ¶: [0059]) outside the first area, the first area including a first transmission area (Fig. 3, element NEA; ¶: [0104]).
Jeon further teaches a signal line (Fig. 4L, element SL2; ¶: [0061]) disposed on the substrate, the signal line including a first signal line (Fig. 4L, element L2; ¶: [0086]) and a second signal line (Fig. 4L, element L1; ¶: [0086]), wherein a part of the first signal line is disposed at a same layer as the first semiconductor layer (Fig. 4L, element L2, SP1; ¶: [0086]), and wherein the first signal line includes an oxide semiconductor material (Fig. 4L, element L2; ¶: [0087])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include multiple display areas so that an improved reflection visibility can be obtained (Jo, ¶: [0007])
Regarding claim 2, Jeon in view of Jo teaches the display apparatus of claim 1. Jeon further teaches the first signal line including a first layer line (Fig. 4L, element AL; ¶: [0087]) which is disposed in a first layer and a second layer line (Fig. 4L, element CL; ¶: [0087]) which is disposed in a second layer, and the first layer line and the second layer line being electrically connected to each other (Fig. 4L, element AL, CL; ¶: [0087]), and including different materials from each other (Fig. 4L, element AL, CL; ¶: [0087]).
Regarding claim 6, Jeon in view of Jo teaches the display apparatus of claim 1. Jeon further teaches the first signal line being configured with a single layer (Fig. 4L, element CL; ¶: [0103]).
Regarding claim 7, Jeon in view of Jo teaches the display apparatus of claim 6. Jeon further teaches the first signal line including transparent conductive oxide (Fig. 4L, element CL; ¶: [0087]).
Regarding claim 8, Jeon in view of Jo teaches the display apparatus of claim 1. Jeon does not teach a first protective layer on the first thin film transistor; a second protective layer on the first protective layer; a connection electrode between the first protective layer and the second protective layer; and a first line disposed at a same layer as the connection electrode and disposed in the first area.
Jo teaches a first protective layer (Fig. 3, element 111a; ¶: [0067]) on the first thin film transistor; a second protective layer (Fig. 3, element 111b; ¶: [0067]) on the first protective layer; a connection electrode (Fig. 3, element 112b; ¶: [0070]) between the first protective layer and the second protective layer; and a first line (Fig. 3, element 114; ¶: [0067]) disposed at a same layer as the connection electrode and disposed in the first area.
Jeon further teaches the first signal line being electrically connected to the first line through a contact hole (Fig. 4M, element CH3; ¶: [0110]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first line in order to have an electrical connection between the light emitting layer and the thin film transistor (¶: [0068]).
Regarding claim 9, Jeon in view of Jo teaches the display apparatus of claim 8. Jeon further teaches a data line electrically connected to the first line (Fig. 4M, element DL; ¶: [0088]).
Regarding claim 12, Jeon in view of Jo teaches the display apparatus of claim 1. Jeon further teaches a second thin film transistor (Fig. 4M, element TR2; ¶: [0081]) disposed to be spaced apart from the first thin film transistor, the second thin film transistor including a second semiconductor layer (Fig. 4M, element SP2; ¶: [0081]), wherein the first semiconductor layer and the second semiconductor layer are made of different materials (Fig. 4M, element SP1, SP2; ¶: [0006, 0077, 0082]).
Regarding claim 14, Jeon in view of Jo teaches the display apparatus of claim 1. Jeon does not teach the first area including a first light emitting area, the second area including a second light emitting area, and the first light emitting area and the second light emitting area having different pixel structures.
Jo teaches the first area including a first light emitting area (Fig. 2, element EA2; ¶: [0059]), the second area including a second light emitting area (Fig. 2, element EA1; ¶: [0059]), and the first light emitting area and the second light emitting area having different pixel structures (Fig. 2, element SP1, SP2, SP3; ¶: [0059])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include multiple light emitting areas with different pixel structures so that individual colors can separately be emitted (Jo, ¶: [0046]).
Regarding claim 15, Jeon in view of Jo teaches the display apparatus of claim 14. Jeon does not teach a third area outside the first area, wherein the third area includes a third light emitting area, and wherein the first light emitting area and the third light emitting area have different pixel structures.
Jo teaches a third area (Fig. 2, element EA3; ¶: [0059]) outside the first area, wherein the third area includes a third light emitting area (Fig. 2, element EA3; ¶: [0059]), and wherein the first light emitting area and the third light emitting area have different pixel structures (Fig. 2, element SP1, SP4; ¶: [0059]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include multiple light emitting areas with different pixel structures so that individual colors can separately be emitted (Jo, ¶: [0046]).
Regarding claim 17, Jeon in view of Jo teaches the display apparatus of claim 1. Jeon does not teach a plurality of subpixels in the first area, wherein at least one of first signal lines is electrically connected to the plurality of subpixels.
Jo teaches a plurality of subpixels (element SP1, SP2, SP3, SP4; ¶: [0058, 0059]) in the first area, wherein at least one of first signal lines is electrically connected to the plurality of subpixels (element SL1; ¶: [0062]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the signal line connected to a plurality of subpixels so that when external light is reflected towards the signal line, the reflection visibility of the subpixels is sufficient (Jo, ¶: [0063]).
Regarding claim 19, Jeon in view of Jo teaches the display apparatus of claim 1. Jeon further teaches the first signal line including transparent conductive oxide (Fig. 4L, element L2; ¶: [0087]), and the second signal line not including the transparent conductive oxide (Fig. _47, element L1; ¶: [0092]).
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20210343822 A1) hereinafter referred to as "Jeon" in view of Jo (US 20230200194 A1) and further in view of Kim et al. (US 20220399431 A1) hereinafter referred to as "Kim" .
Regarding claim 3, Jeon in view of Jo teach the display apparatus of claim 2. However, neither teach the first layer line including a first side surface, a third side surface opposite the first side surface, and a second surface between the first side surface and the third side surface, and wherein second layer line completely covers the first side surface, the second surface, and the third side surface of the first layer line.
Kim teaches the first layer line including a first side surface (Fig. 8, element 180a; ¶: [0105]), a third side surface (Fig. 8, element 180a; ¶: [0105]) opposite the first side surface, and a second surface (Fig. 8, element 180a; ¶: [0105]) between the first side surface and the third side surface, and wherein second layer line completely covers the first side surface, the second surface, and the third side surface of the first layer line (Fig. 8, element 180c; ¶: [0105]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to cover the side surfaces of the first layer line and involve a material that can induce a galvanic reaction when etched such as indium tin oxide or indium zinc oxide (Kim, ¶: [0105]).
Regarding claim 4, Jeon in view of Jo teach the display apparatus of claim 2. Neither teach the first layer line including a first side surface, the second layer line including a second side surface, and the second side surface of the second layer line covering the first side surface of the first layer line.
Kim teaches the first layer line including a first side surface (Fig. 8, element 180a; ¶: [0105]), the second layer line including a second side surface (Fig. 8, element 180c; ¶: [0105]), and the second side surface of the second layer line covering the first side surface of the first layer line (Fig. 8, element 180a, 180c; ¶: [0105]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to cover the side surfaces of the first layer line and involve a material that can induce a galvanic reaction when etched such as indium tin oxide or indium zinc oxide (Kim, ¶: [0105]).
Regarding claim 5, Jeon in view of Jo teach the display apparatus of claim 2. However, neither teach the first layer line including a first transparent conductive oxide, and the second layer line including a second transparent conductive oxide different from the first transparent conductive oxide.
Kim teaches the first layer line including a first transparent conductive oxide, and the second layer line including a second transparent conductive oxide different from the first transparent conductive oxide (Fig. 8, element 180a, 180c; ¶: [0105]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to cover the side surfaces of the first layer line and involve a material that can induce a galvanic reaction when etched such as indium tin oxide or indium zinc oxide (Kim, ¶: [0105]).
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Claim(s) 10-11, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al. (US 20210343822 A1) hereinafter referred to as "Jeon" in view of Jo (US 20230200194 A1) and further in view of Lee et al. (US 20230036991 A1) hereinafter referred to as "Lee".
Regarding claim 10, Jeon in view of Jo teach the display apparatus of claim 1. Neither teach the first thin film transistor further including a first source electrode and a first drain electrode on the first semiconductor layer, the display apparatus further comprising a second line disposed at a same layer as the first source electrode and the first drain electrode and disposed in the first area, and the first signal line being electrically connected to the second line through a contact hole.
Lee teaches the first thin film transistor further including a first source electrode (Fig. 6, element SE1; ¶: [110]) and a first drain electrode (Fig. 6, element DE1; ¶: [110]) on the first semiconductor layer, the display apparatus further comprising a second line (Fig. 11, element BWL; ¶: [165]) disposed at a same layer as the first source electrode and the first drain electrode and disposed in the first area, and the first signal line being electrically connected to the second line through a contact hole (Fig. 11, element CWL, BWL; ¶: [165]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first signal line be connected to the second line so that the first signal line may have a connection to the pixel circuit (Lee, ¶: [0165]).
Regarding claim 11, Jeon in view of Jo teach the display apparatus of claim 10. However, neither teach a gate line electrically connected to the second line.
Lee teaches a gate line electrically connected to the second line (Fig. 11, element GE1, BWL; ¶: [0110, 0165]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate line be connected to the second line so that the first signal line may have a connection to the signal line (Lee, ¶: [0165]).
Regarding claim 18, Jeon in view of Jo teach the display apparatus of claim 2. However, neither teach an optical device located under the substrate, and overlapping at least a portion of the first area, wherein the optical device performs a selected operation on the basis of light received by transmitting the first area.
Lee teaches an optical device (Fig. 2, element 40; ¶: [0061]) located under the substrate, and overlapping at least a portion of the first area (Fig. 2, element DA2; ¶: [0061]), wherein the optical device performs a selected operation on the basis of light received by transmitting the first area (¶: [0061]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a component such as a camera and exclude common limitations by having the pixel driving circuit in a different area (¶: [0061]).
Regarding claim 20, Jeon in view of Jo teach the display apparatus of claim 1. Neither teach the first signal line being configured with a multilayer, and the second signal line being configured with a single layer.
Lee teaches the first signal line being configured with a multilayer, and the second signal line being configured with a single layer (Fig. 11, element CWL, WL1; ¶: [0157, 0127]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to manipulate the first signal line to be multi-layered as this reduces processing time and cost, as well as positively affects the light transmittance of the respective display area (¶: [0159]).
Allowable Subject Matter
Claims 13 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 16 is objected to due its dependence on claim 13
The following is an examiner’s statement of reasons for allowance:
Regarding claim 13 (and thus the dependent claim 16), Jeon in view of Jo cite similar elements of the claimed invention such as a first electrode (Jo, Fig. 3, element 114) on the signal line; a light emitting layer (Jo, Fig. 3, element 116) on the first electrode; and a second electrode (Jo, Fig. 3, element 117) on the light emitting layer.
However, the prior art of record to the examiner’s knowledge when taken alone or in combination does not teach the element of the invention claimed by the applicant regarding: “the second electrode including a hole within the first transmission area” as recited in claim 13.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IHSAN HAWKINS whose telephone number is (571)272-8594. The examiner can normally be reached Mon-Thu 7:00AM-5:00PM.
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/I.H./Examiner, Art Unit 2899 /LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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