DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed by Applicant on 01/16/2026. This action is made FINAL.
Examiner’s Notes
While not relied upon per se in the forthcoming action, this section is only intended to communicate the best possible manner in which it is believed that the instant application can be disposed. The following is a non-exhaustive list of issues that came up during examination:
The Applicant states that the “present invention can reduce the number of data channels by connecting a plurality of data lines DL to one data channel CH and reduce noise through a data switching circuit that controls the data voltage Vdata.” Exemplary claim 1 does not show any grouping of a plurality of data lines in connecting to one channel.
The Applicant states that “these features are described in paragraph [0101] of the applicant's specification and FIG. 4 as originally filed, "A data switching circuit 190 may include a plurality of switching elements SW1, SW2, and SW3, and may selectively supply the data voltage Vdata transferred through the data channels CH1 and CH2 of the data driving circuit 130 to the data lines DL(1)-DL(m) of the display panel 110 according to the switching signals SS1, SS2, and SS3, for example, output from the timing controller 140. The plurality of switching elements SW1, SW2, and SW3 may be transistors that are turned on or off by the switching signals SS1, SS2, and SS3, respectively." The pending claims do not describe at least the underlined limitations.
The Applicant states that “In addition, the present invention can reduce electromagnetic interference caused by switching signals SS1, SS2, SS3 by supplying a pseudo signal PS that is opposite in phase to the switching signals SS1, SS2, SS3 through a pseudo signal line PL extending along the outer side of the switching signal lines SL1, SL2, SL3.” The pending claims do not show the underlined limitations, in addition to not showing what component supplies the PS, and what component gets controlled by the PS.
Response to Arguments
Applicant’s arguments with respect to claims 1-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al (Publication number: US 2024/0296784) in view of Jang et al (Publication number: US 2021/0020137).
Consider Claim 1, Ma et al shows a display device (see figure 1), comprising:
(a) A display panel including a plurality of subpixels in a display area and a plurality of switching signal lines and a pseudo signal line in a bezel area (see figures 1 and 4; paragraphs 48-50, and 85); (The switching signal lines are read as data lines and the pseudo signal part is read as the portion of data lead 150 that is located in the non-display area).
(b) A data switching circuit including a plurality of switching elements configured to control a data voltage supplied to the display panel (see figures 3-4; and paragraphs 81-83); (A pad 130 may be configured to be coupled to the data driving circuit (i.e., source driver). For example, the pad 130 may be coupled to the data driving circuit through an anisotropic conductive adhesive).
(c) A timing controller configured to supply a plurality of switching signals that control the plurality of switching elements through the plurality of switching signal lines (see paragraph 55); (see timing control circuit 220).
(d) A pseudo signal generation circuit configured to generate a pseudo signal supplied to the pseudo signal line using the plurality of switching signals (see figures 1 and 4; paragraphs 48-50, and 85); (The switching signal lines are read as data lines and the pseudo signal part is read as the portion of data lead 150 that is located in the non-display area).
However, Ma et al does not specifically show that the driving circuit is configured to supply a data voltage to the display panel through a data channel, and a connection between the data channel and the plurality of switching signal lines.
In related art, Jang et al shows that the driving circuit is configured to supply a data voltage to the display panel through a data channel, and a connection between the data channel and the plurality of switching signal lines (see paragraphs 103-105); (The first MUX signal pair MUX1 and PMUX1 include a first MUX signal MUX1 applied to a gate of the first switching element M1 of each of the demultiplexers 21 and 22 to control turning the first switching element M1 on and off and a first pseudo MUX signal PMUX1 that is not applied to the demultiplexers 21 and 22. The first pseudo MUX signal PMUX1 does not affect the output of the demultiplexers 21 and 22 but is a signal generated in the opposite phase of the first MUX signal MUX1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Jang et al into the teaching of Ma et al in order to reduce electromagnetic interference (see Jang et al; paragraphs 103-105).
Consider Claims 2, and 3, Ma et al shows that the pseudo signal line is along an area adjacent to a data driving circuit that is configured to supply the data voltage of the bezel area, wherein the plurality of switching signal lines are between the data driving circuit and the pseudo signal line (see figures 1 and 4; paragraphs 48-50, and 85); (The switching signal lines are read as data lines and the pseudo signal part is read as the portion of data lead 150 that is located in the non-display area).
Consider Claim 4, Ma et al shows that the plurality of switching signal lines and the pseudo signal line extend along a side surface of a source film on which the data driving circuit is mounted (see figures 3 and 4).
Consider Claim 5, Ma et al shows that the plurality of switching elements include: a first switching element connected between a first data channel and a data line of a red subpixel; a second switching element connected between the first data channel and a data line of a green subpixel; and a third switching element connected between the first data channel and a data line of a blue subpixel (see paragraphs 65 and 66); (The light-emitting device E may emit light. For example, the light-emitting device E can emit one of red light, green light, blue light, or white light).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ma et al (Publication number: US 2024/0296784) in view of Jang et al in view of Lou et al (Publication number: US 2023/0246038).
Consider Claim 7, Ma et al in view of Jang et al does not specifically show a turn-on period during which a corresponding one of the plurality of switching elements is turned on; and a buffering period during which a signal of a turn-off level is switched to a turn-on level and the turn-on level is maintained for a predetermined time between turn-on periods.
In related art, Lou et al shows a turn-on period during which a corresponding one of the plurality of switching elements is turned on; and a buffering period during which a signal of a turn-off level is switched to a turn-on level and the turn-on level is maintained for a predetermined time between turn-on periods (see paragraph 72); (During the light-emitting period T3, the light-emitting control signal line Emit provides a low level, and the first transistor T1 and the ninth transistor T9 transmit a driving current, which is converted by the positive power supply voltage provided by the first positive power supply signal line PVDD1 and the data voltage provided by the data line Data to the first light-emitting device 41, to drive the first light-emitting device 41 to emit light).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Lou et al into the teaching of Ma et al, and Jang et al in order to reduce an overall line load (see Lou et al; paragraphs 72 and 73).
Claims 19-22 are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al (Publication number: US 2024/0296784) in view of Jang et al in view of Wang et al (Publication number: US 2020/0380931).
Consider Claim 19, Ma et al in view of Jang et al does not specifically show that the data switching circuit further includes a phase delay circuit configured to match phases of the plurality of switching signals and the pseudo signal.
In related art, Wang et al shows that the data switching circuit further includes a phase delay circuit configured to match phases of the plurality of switching signals and the pseudo signal (see paragraphs 8-11); ( A positive phase control end of the first transmission gate is connected to the second clock signal input end, an inverted phase control end of the first transmission gate is connected to the first clock signal input end, and an input end of the first transmission gate is connected to an output end of the first NAND gate. An input end of the phase inverter is connected to an output end of the first transmission gate).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Wang et al et al into the teaching of Ma et al, and Jang et al in order to ensure normal operation of the display panel (see Wang et al; paragraphs 3 and 4).
Consider Claim 20, Ma et al shows a display panel (see figure 1), comprising:
(a) A plurality of subpixels in a display area; a plurality of switching signal lines in a bezel area to transfer a plurality of switching signals; a pseudo signal line outside the plurality of switching signal lines (see figures 1 and 4; paragraphs 48-50, and 85); (The switching signal lines are read as data lines and the pseudo signal part is read as the portion of data lead 150 that is located in the non-display area).
(b) A data switching circuit including a plurality of switching elements configured to control a data voltage transferred through a data line according to the plurality of switching signals (see figures 3-4; and paragraphs 81-83); (A pad 130 may be configured to be coupled to the data driving circuit (i.e., source driver). For example, the pad 130 may be coupled to the data driving circuit through an anisotropic conductive adhesive).
However, Ma et al does not specifically show that the driving circuit is configured to supply a data voltage to the display panel through a data channel, and a connection between the data channel and the plurality of switching signal lines.
In related art, Jang et al shows that the driving circuit is configured to supply a data voltage to the display panel through a data channel, and a connection between the data channel and the plurality of switching signal lines (see paragraphs 103-105); (The first MUX signal pair MUX1 and PMUX1 include a first MUX signal MUX1 applied to a gate of the first switching element M1 of each of the demultiplexers 21 and 22 to control turning the first switching element M1 on and off and a first pseudo MUX signal PMUX1 that is not applied to the demultiplexers 21 and 22. The first pseudo MUX signal PMUX1 does not affect the output of the demultiplexers 21 and 22 but is a signal generated in the opposite phase of the first MUX signal MUX1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Jang et al into the teaching of Ma et al in order to reduce electromagnetic interference (see Jang et al; paragraphs 103-105).
However, Ma et al in view of Jang et al do not specifically show transferring a pseudo signal opposite in phase to at least some of the plurality of switching signals.
In related art, Wang et al shows transferring a pseudo signal opposite in phase to at least some of the plurality of switching signals (see paragraphs 8-11); ( A positive phase control end of the first transmission gate is connected to the second clock signal input end, an inverted phase control end of the first transmission gate is connected to the first clock signal input end, and an input end of the first transmission gate is connected to an output end of the first NAND gate. An input end of the phase inverter is connected to an output end of the first transmission gate).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Wang et al et al into the teaching of Ma et al and Jang et al in order to ensure normal operation of the display panel (see Wang et al; paragraphs 3 and 4).
Consider Claims 21 and 22, Ma et al shows that the pseudo signal line is along an area adjacent to a data driving circuit that is configured to supply the data voltage of the bezel area, wherein the plurality of switching signal lines are between the data driving circuit and the pseudo signal line (see figures 1 and 4; paragraphs 48-50, and 85); (The switching signal lines are read as data lines and the pseudo signal part is read as the portion of data lead 150 that is located in the non-display area).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Ma et al (Publication number: US 2024/0296784) in view of Jang et al in view of Wang et al (Publication number: US 2020/0380931) in view of Lou et al (Publication number: US 2023/0246038).
Consider Claim 23, Ma et al in view of Jang et al in view of Wang et al does not specifically show a turn-on period during which a corresponding one of the plurality of switching elements is turned on; and a buffering period during which a signal of a turn-off level is switched to a turn-on level and the turn-on level is maintained for a predetermined time between turn-on periods.
In related art, Lou et al shows a turn-on period during which a corresponding one of the plurality of switching elements is turned on; and a buffering period during which a signal of a turn-off level is switched to a turn-on level and the turn-on level is maintained for a predetermined time between turn-on periods (see paragraph 72); (During the light-emitting period T3, the light-emitting control signal line Emit provides a low level, and the first transistor T1 and the ninth transistor T9 transmit a driving current, which is converted by the positive power supply voltage provided by the first positive power supply signal line PVDD1 and the data voltage provided by the data line Data to the first light-emitting device 41, to drive the first light-emitting device 41 to emit light).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Lou et al into the teaching of Ma et al, Jang et al and Wang et al in order to reduce an overall line load (see Lou et al; paragraphs 72 and 73).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ma et al (Publication number: US 2024/0296784) in view of Jang et al in view of Yuan et al (Publication number: US 2023/0043145).
Consider Claim 6, Ma et al in view of Jang et al do not specifically show that the plurality of switching elements include a P-type MOS transistor.
In related art, Yuan et al shows that the plurality of switching elements include a P-type MOS transistor (see paragraph 47).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Yuan et al into the teaching of Ma et al and Jang et al in order to activate a semiconductor layer (see Yuan et al; paragraphs 46-48).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ma et al (Publication number: US 2024/0296784) in view of Jang et al in view of Sun (Publication number: US 2018/0367036).
Consider Claim 18, Ma et al in view of Jang et al does not specifically show that the data switching circuit further includes an amplifier configured to maintain levels of the plurality of switching signals and the pseudo signal at a same level.
In related art, Sun shows that the data switching circuit further includes an amplifier configured to maintain levels of the plurality of switching signals and the pseudo signal at a same level (see paragraphs 21 and 22).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the application to incorporate the teaching of Sun into the teaching of Ma et al and Jang et al in order to provide a correction signal (see Sun; paragraphs 21-23).
Allowable Subject Matter
Claims 8-17, and 24-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL A FARAGALLA/Primary Examiner, Art Unit 2624 05/13/2026
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