DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 15, 16 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sarkeshi et al. (A novel Doherty amplifier for enhanced load modulation and higher bandwidth Mehdi Sarkeshi, O. B. Leong, A. V. van Roermund Published in IEEE MTT-S International… 15 June 2008 Engineering, Physics)
Re claims 1 and 17: The reference to Sarkeshi et al, see figure below, shows a Doherty
amplifier, with a carrier amplification transistor(carrier) configured to amplify a first input
radio frequency (1st input RF) signal; a carrier bias circuit(supply rail with inductor coil)
configured to supply a carrier bias voltage(VGG) to the carrier amplification transistor;
a peaking amplification transistor (peaking)configured to amplify a second input RF signal(2nd
input RF); a peaking bias circuit configured to supply a peaking bias voltage to the peaking
amplification transistor(Vdd bias );
a first linearization circuit (phase shifter)connected between a first terminal( peaking
transistor) to which the second input RF signal is input and a second terminal (via inductor coil
to peaking transistor from wave shaper)to which the peaking bias voltage is output in the
peaking bias circuit,
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439
882
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As noted on p765, top right column:
“The bias voltages of the varactors have been set by the wave shaping circuit to adaptively realize the transformation shown in Table.I in the carrier amplifier path and simultaneously, compensate for its phase delay, in the peak amplifier path.”
configured to couple a portion of the second input RF signal to the second terminal and serve to
bias the peaking transistor to achieve a more linear output, as noted on page 765, and figure 7.
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594
630
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RE claim 4: As can be seen in the figures the Doherty amplifier with a magnitude of a coupled
signal coupled by the first linearization circuit is changed according to a power mode, that is,
enhanced class AB mode.
Re claim 15 The Doherty amplifier of claim 1, further comprising a power divider/SPLITTER
configured to generate the first input RF signal and the second input RF signal based on an
input RF signal.
Re claim 16. The Doherty amplifier inherently has the carrier amplification transistor biased as
Class AB by the carrier bias voltage, and the peaking amplification transistor is biased as Class
C(enhanced) by the peaking bias voltage.
Allowable Subject Matter
Claims 2, 3, 5-14 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The reference to Yang et al, Electronics 2021, MDPI shows Doherty amp implementation with carrier and peak amplifiers and power adjustment. A general teaching for the subject matter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARNOLD M KINKEAD whose telephone number is (571)272-1763. The examiner can normally be reached M-F 7am-5:30pm(Fri-Flex).
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/ARNOLD M KINKEAD/Primary Examiner, Art Unit 2836
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